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completed LPC43xx memorymap.h

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This commit is contained in:
Michael Ossmann
2012-05-28 14:45:03 -06:00
parent 713a210b59
commit 8f19691438
1 changed files with 40 additions and 10 deletions
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50
include/libopencm3/lpc43xx/memorymap.h
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@@ -34,7 +34,7 @@
/* Register boundary addresses */
/* AHB */
/* AHB (0x4000 0000 - 0x4001 2000) */
#define SCT_BASE (PERIPH_BASE_AHB + 0x00000)
/* PERIPH_BASE_AHB + 0x01000 (0x4000 1000 - 0x4000 1FFF): Reserved */
#define DMA_BASE (PERIPH_BASE_AHB + 0x02000)
@@ -50,14 +50,25 @@
/* 0x4001 2000 - 0x4003 FFFF Reserved */
/* RTC domain peripherals */
//TODO
#define ATIMER_BASE 0x40040000
#define BACKUP_REG_BASE 0x40041000
#define PMC_BASE 0x40042000
#define CREG_BASE 0x40043000
#define EVENTROUTER_BASE 0x40044000
#define OTP_BASE 0x40045000
#define RTC_BASE 0x40046000
/* 0x4004 7000 - 0x4004 FFFF Reserved */
/* clocking/reset control peripherals */
//TODO
#define CGU_BASE 0x40050000
#define CCU1_BASE 0x40051000
#define CCU2_BASE 0x40052000
#define RGU_BASE 0x40053000
/* 0x4005 4000 - 0x4005 FFFF Reserved */
/* 0x4006 0000 - 0x4007 FFFF Reserved */
/* APB0 */
/* APB0 ( 0x4008 0000 - 0x4008 FFFF) */
#define WWDT_BASE (PERIPH_BASE_APB0 + 0x00000)
#define USART0_BASE (PERIPH_BASE_APB0 + 0x01000)
#define UART1_BASE (PERIPH_BASE_APB0 + 0x02000)
@@ -68,21 +79,40 @@
#define GPIO_PIN_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x07000)
#define GPIO_GROUP0_INTRRUPT_BASE (PERIPH_BASE_APB0 + 0x08000)
#define GPIO_GROUP1_INTRRUPT_BASE (PERIPH_BASE_APB0 + 0x09000)
/* 0x4008 A000 - 0x4008 FFFF Reserved */
/* 0x4009 0000 - 0x4009 FFFF Reserved */
/* APB1 */
//TODO
/* APB1 (0x400A 0000 - 0x400A FFFF) */
#define MCPWM_BASE (PERIPH_BASE_APB1 + 0x00000)
#define I2C0_BASE (PERIPH_BASE_APB1 + 0x01000)
#define I2S0_BASE (PERIPH_BASE_APB1 + 0x02000)
#define I2S1_BASE (PERIPH_BASE_APB1 + 0x03000)
#define C_CCAN1_BASE (PERIPH_BASE_APB1 + 0x04000)
/* 0x400A 5000 - 0x400A FFFF Reserved */
/* 0x400B 0000 - 0x400B FFFF Reserved */
/* APB2 */
//TODO
/* APB2 (0x400C 0000 - 0x400C FFFF) */
#define RITIMER_BASE (PERIPH_BASE_APB2 + 0x00000)
#define USART2_BASE (PERIPH_BASE_APB2 + 0x01000)
#define USART3_BASE (PERIPH_BASE_APB2 + 0x02000)
#define TIMER2_BASE (PERIPH_BASE_APB2 + 0x03000)
#define TIMER3_BASE (PERIPH_BASE_APB2 + 0x04000)
#define SSP1_BASE (PERIPH_BASE_APB2 + 0x05000)
#define QEI_BASE (PERIPH_BASE_APB2 + 0x06000)
#define GIMA_BASE (PERIPH_BASE_APB2 + 0x07000)
/* 0x400C 8000 - 0x400C FFFF Reserved */
/* 0x400D 0000 - 0x400D FFFF Reserved */
/* APB3 */
//TODO
/* APB3 (0x400E 0000 - 0x400E FFFF) */
#define I2C1_BASE (PERIPH_BASE_APB3 + 0x00000)
#define DAC_BASE (PERIPH_BASE_APB3 + 0x01000)
#define C_CAN0_BASE (PERIPH_BASE_APB3 + 0x02000)
#define ADC0_BASE (PERIPH_BASE_APB3 + 0x03000)
#define ADC1_BASE (PERIPH_BASE_APB3 + 0x04000)
/* 0x400E 5000 - 0x400E FFFF Reserved */
/* 0x400F 0000 - 0x400F 0FFF Reserved */