Work on scs.h register and also nvic.h.

ARM Interrupt API (see nvic.h). ARM SysTick API (see systick.h). Example using both Interrupt and SysTick and blink LED1/2/3 see systickdemo.c.
2012-06-09 18:27:42 +02:00
parent 161aad0139
commit 8d97dbc7c3
9 changed files with 741 additions and 1 deletions
--- a/include/libopencm3/cm3/scs.h
+++ b/include/libopencm3/cm3/scs.h
@@ -2,6 +2,7 @@
 * This file is part of the libopencm3 project.
 *
 * Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
+ * Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
 *
 * This library is free software: you can redistribute it and/or modify
 * it under the terms of the GNU Lesser General Public License as published by
@@ -20,9 +21,85 @@
 #ifndef LIBOPENCM3_CM3_SCS_H
 #define LIBOPENCM3_CM3_SCS_H

+/* 
+ * All the definition hereafter are generic for CortexMx ARMv7-M
+ * See ARM document "ARMv7-M Architecture Reference Manual" for more details.
+ * See also ARM document "ARM Compiler toolchain Developing Software for ARM Processors" for details on System Timer/SysTick.
+ */
+
+/*
+ * The System Control Space (SCS) is a memory-mapped 4KB address space that provides 32-bit registers for
+ * configuration, status reporting and control. The SCS registers divide into the following groups:
+ * - system control and identification
+ * - the CPUID processor identification space
+ * - system configuration and status
+ * - fault reporting
+ * - a system timer, SysTick
+ * - a Nested Vectored Interrupt Controller (NVIC)
+ * - a Protected Memory System Architecture (PMSA)
+ * - system debug.
+ */
+
+/* System Handler Priority 8 bits Registers, SHPR1/2/3 */
+/* Note: 12 8bit Registers */
+#define SCS_SHPR(ipr_id)		MMIO8(SCS_BASE + 0xD18 + ipr_id)
+
+/*
+ * Debug Halting Control and Status Register (DHCSR).
+ * 
+ * Purpose Controls halting debug.
+ * Usage constraints: The effect of modifying the C_STEP or C_MASKINTS bit when the system
+ * is running with halting debug enabled is UNPREDICTABLE. 
+ * Halting debug is enabled when C_DEBUGEN is set to 1. The system is running when S_HALT is set to 0.
+ * - When C_DEBUGEN is set to 0, the processor ignores the values of all other bits in this register.
+ * - For more information about the use of DHCSR see Debug stepping on
+ * page C1-824.
+ * Configurations Always implemented.
+ */
+/* SCS_DHCSR register */
 #define SCS_DHCSR		MMIO32(SCS_BASE + 0xDF0)
+/*
+ * Debug Core Register Selector Register (DCRSR).
+ * 
+ * Purpose With the DCRDR, the DCRSR provides debug access to the ARM core registers,
+ * special-purpose registers, and Floating-point extension registers. A write to DCRSR
+ * specifies the register to transfer, whether the transfer is a read or a write, and starts
+ * the transfer.
+ * Usage constraints: Only accessible in Debug state.
+ * Configurations Always implemented.
+ *
+ */
+/* SCS_DCRS register */
 #define SCS_DCRSR		MMIO32(SCS_BASE + 0xDF4)
+/*
+ * Debug Core Register Data Register (DCRDR)
+ * 
+ * Purpose With the DCRSR, see Debug Core Register Selector Register, 
+ * the DCRDR provides debug access to the ARM core registers,
+ * special-purpose registers, and Floating-point extension registers. The
+ * DCRDR is the data register for these accesses.
+ * - Used on its own, the DCRDR provides a message passing resource between
+ * an external debugger and a debug agent running on the processor.
+ * Note:
+ * The architecture does not define any handshaking mechanism for this use of DCRDR.
+ * Usage constraints: See Use of DCRSR and DCRDR for constraints that apply to
+ * particular transfers using the DCRSR and DCRDR.
+ * Configurations Always implemented.
+ *
+ */
+/* SCS_DCRDR register */
 #define SCS_DCRDR		MMIO32(SCS_BASE + 0xDF8)
+/*
+ * Debug Exception and Monitor Control Register (DEMCR).
+ *
+ * Purpose Manages vector catch behavior and DebugMonitor handling when debugging.
+ * Usage constraints:
+ * - Bits [23:16] provide DebugMonitor exception control.
+ * - Bits [15:0] provide Debug state, halting debug, control.
+ * Configurations Always implemented.
+ * 
+ */
+/* SCS_DEMCR register */
 #define SCS_DEMCR		MMIO32(SCS_BASE + 0xDFC)

 /* Debug Halting Control and Status Register (DHCSR) */
@@ -64,4 +141,169 @@
 /* Bits 3:1 - Reserved */
 #define SCS_DEMCR_VC_CORERESET	(1 << 0)

+/*
+ * System Control Space (SCS) => System timer register support in the SCS.
+ * To configure SysTick, load the interval required between SysTick events to the SysTick Reload
+ * Value register. The timer interrupt, or COUNTFLAG bit in the SysTick Control and Status
+ * register, is activated on the transition from 1 to 0, therefore it activates every n+1 clock ticks.
+ * If you require a period of 100, write 99 to the SysTick Reload Value register. The SysTick Reload
+ * Value register supports values between 0x1 and 0x00FFFFFF.
+ *
+ * If you want to use SysTick to generate an event at a timed interval, for example 1ms, you can
+ * use the SysTick Calibration Value Register to scale your value for the Reload register. The
+ * SysTick Calibration Value Register is a read-only register that contains the number of pulses for
+ * a period of 10ms, in the TENMS field, bits[23:0].
+ *
+ * This register also has a SKEW bit. Bit[30] == 1 indicates that the calibration for 10ms in the
+ * TENMS section is not exactly 10ms due to clock frequency. Bit[31] == 1 indicates that the
+ * reference clock is not provided.
+ */
+/*
+ * SysTick Control and Status Register (CSR).
+ * Purpose Controls the system timer and provides status data.
+ * Usage constraints: There are no usage constraints.
+ * Configurations Always implemented.
+*/
+#define SCS_SYST_CSR		MMIO32(SCS_BASE + 0x10)
+
+/* SysTick Reload Value Register (CVR).
+ * Purpose Reads or clears the current counter value.
+ * Usage constraints:
+ * - Any write to the register clears the register to zero.
+ * - The counter does not provide read-modify-write protection.
+ * - Unsupported bits are read as zero
+ * Configurations Always implemented.
+ */
+#define CM_SCS_SYST_RVR		MMIO32(SCS_BASE + 0x14)
+
+/* SysTick Current Value Register (RVR). 
+ * Purpose Holds the reload value of the SYST_CVR.
+ * Usage constraints There are no usage constraints.
+ * Configurations Always implemented.
+ */
+#define CM_SCS_SYST_CVR		MMIO32(SCS_BASE + 0x18)
+
+/* 
+ * SysTick Calibration value Register(Read Only) (CALIB)
+ * Purpose Reads the calibration value and parameters for SysTick.
+ * Usage constraints: There are no usage constraints.
+ * Configurations Always implemented.
+ */
+#define CM_SCS_SYST_CALIB	MMIO32(SCS_BASE + 0x1C)
+
+/* --- SCS_SYST_CSR values ----------------------------------------------- */
+/* Counter is operating. */
+#define SCS_SYST_CSR_ENABLE			(BIT0)
+/* Count to 0 changes the SysTick exception status to pending. */
+#define SCS_SYST_CSR_TICKINT		(BIT1)
+/* SysTick uses the processor clock. */
+#define SCS_SYST_CSR_CLKSOURCE		(BIT2)
+/* 
+ * Indicates whether the counter has counted to 0 since the last read of this register:
+ *  0 = Timer has not counted to 0
+ *  1 = Timer has counted to 0. 
+ */
+#define SCS_SYST_CSR_COUNTFLAG		(BIT16)
+
+/* --- CM_SCS_SYST_RVR values ----------------------------------------------- */
+/* Bit 0 to 23 => RELOAD The value to load into the SYST_CVR when the counter reaches 0. */
+/* Bit 24 to 31 are Reserved */
+
+/* --- CM_SCS_SYST_CVR values ----------------------------------------------- */
+/* Bit0 to 31 => Reads or clears the current counter value. */
+
+/* --- CM_SCS_SYST_CALIB values ----------------------------------------------- */
+/* 
+ * Bit0 to 23 => TENMS Optionally, holds a reload value to be used for 10ms (100Hz) timing, subject to system clock
+ * skew errors. If this field is zero, the calibration value is not known.
+ */
+#define SCS_SYST_SYST_CALIB_TENMS_MASK		(BIT24-1)
+
+/* 
+ * Bit30 => SKEW Indicates whether the 10ms calibration value is exact:
+ * 0 = 10ms calibration value is exact.
+ * 1 = 10ms calibration value is inexact, because of the clock frequency
+ */
+#define SCS_SYST_SYST_CALIB_VALUE_INEXACT	(BIT30)
+/* 
+ * Bit31 => NOREF Indicates whether the IMPLEMENTATION DEFINED reference clock is implemented:
+ * 0 = The reference clock is implemented.
+ * 1 = The reference clock is not implemented.
+ * When this bit is 1, the CLKSOURCE bit of the SYST_CSR register is forced to 1 and cannot
+ * be cleared to 0.
+ */
+#define SCS_SYST_SYST_CALIB_REF_NOT_IMPLEMENTED	(BIT31)
+
+/* 
+ * System Control Space (SCS) =>  Data Watchpoint and Trace (DWT).
+ * See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0403c/index.html (ARMv7-M Architecture Reference Manual)
+ * The DWT is an optional debug unit that provides watchpoints, data tracing, and system profiling
+ * for the processor.
+ */
+/* 
+ * DWT Control register 
+ * Purpose Provides configuration and status information for the DWT block, and used to control features of the block
+ * Usage constraints: There are no usage constraints.
+ * Configurations Always implemented.
+ */
+#define SCS_DWT_CTRL		MMIO32(DWT_BASE + 0x00)
+/*
+ * DWT_CYCCNT register
+ * Cycle Count Register (Shows or sets the value of the processor cycle counter, CYCCNT) 
+ * When enabled, CYCCNT increments on each processor clock cycle. On overflow, CYCCNT wraps to zero.
+ *
+ * Purpose Shows or sets the value of the processor cycle counter, CYCCNT.
+ * Usage constraints: The DWT unit suspends CYCCNT counting when the processor is in Debug state.
+ * Configurations Implemented: only when DWT_CTRL.NOCYCCNT is RAZ, see Control register, DWT_CTRL.
+ * When DWT_CTRL.NOCYCCNT is RAO no cycle counter is implemented and this register is UNK/SBZP.
+*/
+#define SCS_DWT_CYCCNT		MMIO32(DWT_BASE + 0x04)
+
+/* DWT_CPICNT register 
+ * Purpose Counts additional cycles required to execute multi-cycle instructions and instruction fetch stalls.
+ * Usage constraints: The counter initializes to 0 when software enables its counter overflow event by
+ * setting the DWT_CTRL.CPIEVTENA bit to 1.
+ * Configurations Implemented: only when DWT_CTRL.NOPRFCNT is RAZ, see Control register, DWT_CTRL.
+ * If DWT_CTRL.NOPRFCNT is RAO, indicating that the implementation does not
+ * include the profiling counters, this register is UNK/SBZP.
+ */
+#define SCS_DWT_CPICNT		MMIO32(DWT_BASE + 0x08)
+
+/* DWT_EXCCNT register */
+#define SCS_DWT_EXCCNT		MMIO32(DWT_BASE + 0x0C)
+
+/* DWT_EXCCNT register */
+#define SCS_DWT_SLEEPCNT	MMIO32(DWT_BASE + 0x10)
+
+/* DWT_EXCCNT register */
+#define SCS_DWT_LSUCNT		MMIO32(DWT_BASE + 0x14)
+
+/* DWT_EXCCNT register */
+#define SCS_DWT_FOLDCNT		MMIO32(DWT_BASE + 0x18)
+
+/* DWT_PCSR register */
+#define SCS_DWT_PCSR		MMIO32(DWT_BASE + 0x18)
+
+/* --- SCS_DWT_CTRL values ----------------------------------------------- */
+/* 
+ * Enables CYCCNT:
+ * 0 = Disabled, 1 = Enabled
+ * This bit is UNK/SBZP if the NOCYCCNT bit is RAO.
+ */
+#define SCS_DWT_CTRL_CYCCNTENA	(BIT0)
+
+/* TODO bit definition values for other DWT_XXX register */
+
+/* Macro to be called at startup to enable SCS & Cycle Counter */
+#define SCS_DWT_CYCLE_COUNTER_ENABLED()	( (SCS_DEMCR |= SCS_DEMCR_TRCENA)\
+										(SCS_DWT_CTRL  |= SCS_DWT_CTRL_CYCCNTENA) )
+
+#define SCS_SYSTICK_DISABLED()	(SCS_SYST_CSR=0)
+
+/* Macro to be called at startup to Enable CortexMx SysTick (but IRQ not enabled) */
+#define SCS_SYSTICK_ENABLED()	(SCS_SYST_CSR=(SCS_SYST_CSR_ENABLE | SCS_SYST_CSR_CLKSOURCE))
+
+/* Macro to be called at startup to Enable CortexMx SysTick and IRQ */
+#define SCS_SYSTICK_AND_IRQ_ENABLED()	(SCS_SYST_CSR=(SCS_SYST_CSR_ENABLE | SCS_SYST_CSR_CLKSOURCE | SCS_SYST_CSR_TICKINT))
+
 #endif
--- a/include/libopencm3/lpc43xx/nvic.h
+++ b/include/libopencm3/lpc43xx/nvic.h
@@ -3,6 +3,7 @@
 *
 * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
 * Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
+ * Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
 *
 * This library is free software: you can redistribute it and/or modify
 * it under the terms of the GNU Lesser General Public License as published by
@@ -22,8 +23,48 @@
 #define LPC43XX_NVIC_H

 #include <libopencm3/cm3/common.h>
+#include <libopencm3/cm3/memorymap.h>
 #include <libopencm3/lpc43xx/memorymap.h>

+/* --- NVIC Registers ------------------------------------------------------ */
+
+/* ISER: Interrupt Set Enable Registers */
+/* Note: 8 32bit Registers */
+#define NVIC_ISER(iser_id)		MMIO32(NVIC_BASE + 0x00 + (iser_id * 4))
+
+/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */
+
+/* ICER: Interrupt Clear Enable Registers */
+/* Note: 8 32bit Registers */
+#define NVIC_ICER(icer_id)		MMIO32(NVIC_BASE + 0x80 + (icer_id * 4))
+
+/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */
+
+/* ISPR: Interrupt Set Pending Registers */
+/* Note: 8 32bit Registers */
+#define NVIC_ISPR(ispr_id)		MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4))
+
+/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */
+
+/* ICPR: Interrupt Clear Pending Registers */
+/* Note: 8 32bit Registers */
+#define NVIC_ICPR(icpr_id)		MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4))
+
+/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */
+
+/* IABR: Interrupt Active Bit Register */
+/* Note: 8 32bit Registers */
+#define NVIC_IABR(iabr_id)		MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4))
+
+/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */
+
+/* IPR: Interrupt Priority Registers */
+/* Note: 240 8bit Registers */
+#define NVIC_IPR(ipr_id)		MMIO8(NVIC_BASE + 0x300 + ipr_id)
+
+/* STIR: Software Trigger Interrupt Register */
+#define NVIC_STIR			MMIO32(STIR_BASE)
+
 /* --- IRQ channel numbers-------------------------------------------------- */

 /* Cortex M4 System Interrupts */
@@ -91,4 +132,16 @@
 /* LPC43xx M0 specific user interrupts */
 //TODO

+/* --- NVIC functions ------------------------------------------------------ */
+
+void nvic_enable_irq(u8 irqn);
+void nvic_disable_irq(u8 irqn);
+u8 nvic_get_pending_irq(u8 irqn);
+void nvic_set_pending_irq(u8 irqn);
+void nvic_clear_pending_irq(u8 irqn);
+u8 nvic_get_active_irq(u8 irqn);
+u8 nvic_get_irq_enabled(u8 irqn);
+void nvic_set_priority(u8 irqn, u8 priority);
+void nvic_generate_software_interrupt(u8 irqn);
+
 #endif
--- a/include/libopencm3/lpc43xx/systick.h
+++ b/include/libopencm3/lpc43xx/systick.h
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ * Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_SYSTICK_H
+#define LIBOPENCM3_SYSTICK_H
+
+#include <libopencm3/lpc43xx/memorymap.h>
+#include <libopencm3/cm3/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- SYSTICK registers --------------------------------------------------- */
+/* See also libopencm3\cm3\scs.h for details on SysTicks registers */
+
+/* Control and status register (STK_CTRL) */
+#define STK_CTRL			MMIO32(SYS_TICK_BASE + 0x00)
+
+/* reload value register (STK_LOAD) */
+#define STK_LOAD			MMIO32(SYS_TICK_BASE + 0x04)
+
+/* current value register (STK_VAL) */
+#define STK_VAL				MMIO32(SYS_TICK_BASE + 0x08)
+
+/* calibration value register (STK_CALIB) */
+#define STK_CALIB			MMIO32(SYS_TICK_BASE + 0x0C)
+
+/* --- STK_CTRL values ----------------------------------------------------- */
+/* Bits [31:17] Reserved, must be kept cleared. */
+/* COUNTFLAG: */
+#define STK_CTRL_COUNTFLAG		(1 << 16)
+/* Bits [15:3] Reserved, must be kept cleared. */
+/* CLKSOURCE: Clock source selection */
+#define STK_CTRL_CLKSOURCE		(1 << 2)
+/* TICKINT: SysTick exception request enable */
+#define STK_CTRL_TICKINT		(1 << 1)
+/* ENABLE: Counter enable */
+#define STK_CTRL_ENABLE			(1 << 0)
+
+/* --- STK_LOAD values ----------------------------------------------------- */
+/* Bits [31:24] Reserved, must be kept cleared. */
+/* RELOAD[23:0]: RELOAD value */
+
+/* --- STK_VAL values ------------------------------------------------------ */
+/* Bits [31:24] Reserved, must be kept cleared. */
+/* CURRENT[23:0]: Current counter value */
+
+/* --- STK_CALIB values ---------------------------------------------------- */
+/* NOREF: NOREF flag */
+#define STK_CALIB_NOREF			(1 << 31)
+/* SKEW: SKEW flag */
+#define STK_CALIB_SKEW			(1 << 30)
+/* Bits [29:24] Reserved, must be kept cleared. */
+/* TENMS[23:0]: Calibration value */
+
+/* --- Function Prototypes ------------------------------------------------- */
+
+void systick_set_reload(u32 value);
+u32 systick_get_value(void);
+void systick_set_clocksource(u8 clocksource);
+void systick_interrupt_enable(void);
+void systick_interrupt_disable(void);
+void systick_counter_enable(void);
+void systick_counter_disable(void);
+u8 systick_get_countflag(void);
+
+u32 systick_get_calib(void);
+
+#endif