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Additional updates to STM32U5

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Reference manual indicates that SRAM4 is always at 0x28000000 which makes
it generally discontinuous with other RAM so RAM values that included it were
reduced by 16K and the STM32U5 END line updated to have both the SRAM4 size
and offset.
This commit is contained in:
Chuck McManis
2025-07-13 21:54:52 -07:00
committed by Piotr Esden-Tempski
parent 842d64152c
commit 8a96a9d95a
1 changed files with 16 additions and 16 deletions
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32
ld/devices.data
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@@ -194,26 +194,26 @@ stm32f730* stm32f7ccm ROM=64K RAM=192K CCM=64K
# group # group
# #
# RM0456, Rev 6 plus individual device data sheets. # RM0456, Rev 6 plus individual device data sheets.
# SRAM4 is added with the stm32u5 END line further down in the file
# #
# STM32U535/U545 have SRAM1, 2, and 4 and 128K, 256K, and 512K of FLASH # STM32U535/U545 have SRAM1, 2, and 4 and 128K, 256K, and 512K of FLASH
stm32u5[34]5*e stm32u5 ROM=512K RAM=256K SRAM4=16K SRAM4_OFFSET=0x200C0000 stm32u5[34]5*e stm32u5 ROM=512K RAM=256K
stm32u5[34]5*c stm32u5 ROM=256K RAM=256K SRAM4=16K SRAM4_OFFSET=0x200C0000 stm32u5[34]5*c stm32u5 ROM=256K RAM=256K
stm32u5[34]5*b stm32u5 ROM=128K RAM=256K SRAM4=16K SRAM4_OFFSET=0x200C0000 stm32u5[34]5*b stm32u5 ROM=128K RAM=256K
stm32u5[34]5* stm32u5 ROM=128K RAM=256K SRAM4=16K SRAM4_OFFSET=0x200C0000 stm32u5[34]5* stm32u5 ROM=128K RAM=256K
# STM32U575/U585 have SRAM1, SRAM2, SRAM3, SRAM4 # STM32U575/U585 have SRAM1, SRAM2, SRAM3, SRAM4
stm32u575*g stm32u5 ROM=2048K RAM=768K SRAM4=16K SRAM4_OFFSET=0x200C0000 stm32u575*g stm32u5 ROM=2048K RAM=752K
stm32u575*i stm32u5 ROM=1024K RAM=768K SRAM4=16K SRAM4_OFFSET=0x200C0000 stm32u575*i stm32u5 ROM=1024K RAM=752K
stm32u575* stm32u5 ROM=1024K RAM=768K SRAM4=16K SRAM4_OFFSET=0x200C0000 stm32u575* stm32u5 ROM=1024K RAM=752K
stm32u585* stm32u5 ROM=2048K RAM=768K SRAM4=16K SRAM4_OFFSET=0x200C0000 stm32u585* stm32u5 ROM=2048K RAM=752K
# STM32U59* have SRAM1, SRAM2, SRAM3, SRAM4, SRAM5 (SRAM 4 in the middle of # STM32U59* have SRAM1, SRAM2, SRAM3, SRAM4, SRAM5
# that, still is "special" in that it works while asleep stm32u59*j stm32u5 ROM=4096K RAM=2496K
stm32u59*j stm32u5 ROM=4096K RAM=2512K stm32u59*i stm32u5 ROM=2048K RAM=2496K
stm32u59*i stm32u5 ROM=2048K RAM=2512K stm32u59* stm32u5 ROM=2048K RAM=2495K
stm32u59* stm32u5 ROM=2048K RAM=2512K
# STM32U5A* have same memories as 595 (1-5) # STM32U5A* have same memories as 595 (1-5)
stm32u5a* stm32u5 ROM=4096K RAM=2512K stm32u5a* stm32u5 ROM=4096K RAM=2495K
# STM32U5F* Adds SRAM6 and U5G dual banks flash (so 8192K but only 4096K active) # STM32U5F* Adds SRAM6 and U5G dual banks flash (so 8192K but only 4096K active)
stm32u5[fg]* stm32u5 ROM=4096K RAM=3024K stm32u5[fg]* stm32u5 ROM=4096K RAM=3008K
stm32l01??3* stm32l0 ROM=8K RAM=2K stm32l01??3* stm32l0 ROM=8K RAM=2K
stm32l0[12]??4* stm32l0 ROM=16K RAM=2K stm32l0[12]??4* stm32l0 ROM=16K RAM=2K
@@ -623,7 +623,7 @@ stm32f7 END ROM_OFF=0x08000000 RAM_OFF=0x20010000 CPU=cortex-m7 FPU=hard-fpv5-sp
stm32l0 END ROM_OFF=0x08000000 RAM_OFF=0x20000000 CPU=cortex-m0plus FPU=soft stm32l0 END ROM_OFF=0x08000000 RAM_OFF=0x20000000 CPU=cortex-m0plus FPU=soft
stm32l1 END ROM_OFF=0x08000000 RAM_OFF=0x20000000 CPU=cortex-m3 FPU=soft stm32l1 END ROM_OFF=0x08000000 RAM_OFF=0x20000000 CPU=cortex-m3 FPU=soft
stm32l4 END ROM_OFF=0x08000000 RAM_OFF=0x20000000 RAM2_OFF=0x10000000 RAM3_OFF=0x20040000 CPU=cortex-m4 FPU=hard-fpv4-sp-d16 stm32l4 END ROM_OFF=0x08000000 RAM_OFF=0x20000000 RAM2_OFF=0x10000000 RAM3_OFF=0x20040000 CPU=cortex-m4 FPU=hard-fpv4-sp-d16
stm32u5 END ROM_OFF=0x08000000 RAM_OFF=0x20000000 SRAM4_OFF=0x200C0000 CPU=cortex-m33 FPU=hard-fpv5-sp-d16 stm32u5 END ROM_OFF=0x08000000 RAM_OFF=0x20000000 SRAM4=16K SRAM4_OFF=0x28000000 CPU=cortex-m33 FPU=hard-fpv5-sp-d16
stm32g0 END ROM_OFF=0x08000000 RAM_OFF=0x20000000 CPU=cortex-m0plus FPU=soft stm32g0 END ROM_OFF=0x08000000 RAM_OFF=0x20000000 CPU=cortex-m0plus FPU=soft
stm32g4 END ROM_OFF=0x08000000 RAM_OFF=0x20000000 CPU=cortex-m4 FPU=hard-fpv4-sp-d16 stm32g4 END ROM_OFF=0x08000000 RAM_OFF=0x20000000 CPU=cortex-m4 FPU=hard-fpv4-sp-d16
stm32h7 END ROM_OFF=0x08000000 ROM2_OFF=0x08100000 RAM_OFF=0x24000000 RAM2_OFF=0x30000000 RAM3_OFF=0x30020000 RAM4_OFF=0x30040000 RAM5_OFF=0x38000000 CCM_OFF=0x20000000 CPU=cortex-m7 FPU=hard-fpv5-d16 stm32h7 END ROM_OFF=0x08000000 ROM2_OFF=0x08100000 RAM_OFF=0x24000000 RAM2_OFF=0x30000000 RAM3_OFF=0x30020000 RAM4_OFF=0x30040000 RAM5_OFF=0x38000000 CCM_OFF=0x20000000 CPU=cortex-m7 FPU=hard-fpv5-d16