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stm32:rcc: update _get_clock (uart/i2c) to handle all cases

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Adds handling for missing cases.  While i2c only has 3 cases, uarts have
all 4, so make sure they're handled properly.
Removes duplicated/redundant definitions.
Adds doxygen wrappers, even if only for internal use.

Fixes: e41ac6ea71 stm32: added peripheral clock get helpers for all stm32
Signed-of-by: Karl Palsson <karlp@tweak.au>
This commit is contained in:
Karl Palsson
2023-01-13 02:06:34 +00:00
parent df654d7f28
commit 88e91c9a7c
11 changed files with 175 additions and 168 deletions
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38
include/libopencm3/stm32/f0/rcc.h
View File

@@ -385,36 +385,30 @@ Control</b>
/**@}*/ /**@}*/
/* --- RCC_CFGR3 values ---------------------------------------------------- */ /* --- RCC_CFGR3 values ---------------------------------------------------- */
/** @defgroup rcc_cfgr3_uart_choices UART for clock source selecting
* @note This is only used internally.
* @{
*/
#define RCC_CFGR3_USART3SW_SHIFT 18 #define RCC_CFGR3_USART3SW_SHIFT 18
#define RCC_CFGR3_USART3SW (3 << RCC_CFGR3_USART2SW_SHIFT)
#define RCC_CFGR3_USART3SW_PCLK (0 << RCC_CFGR3_USART2SW_SHIFT)
#define RCC_CFGR3_USART3SW_SYSCLK (1 << RCC_CFGR3_USART2SW_SHIFT)
#define RCC_CFGR3_USART3SW_LSE (2 << RCC_CFGR3_USART2SW_SHIFT)
#define RCC_CFGR3_USART3SW_HSI (3 << RCC_CFGR3_USART2SW_SHIFT)
#define RCC_CFGR3_USART2SW_SHIFT 16 #define RCC_CFGR3_USART2SW_SHIFT 16
#define RCC_CFGR3_USART2SW (3 << RCC_CFGR3_USART2SW_SHIFT) #define RCC_CFGR3_USART1SW_SHIFT 0
#define RCC_CFGR3_USART2SW_PCLK (0 << RCC_CFGR3_USART2SW_SHIFT) /**@}*/
#define RCC_CFGR3_USART2SW_SYSCLK (1 << RCC_CFGR3_USART2SW_SHIFT)
#define RCC_CFGR3_USART2SW_LSE (2 << RCC_CFGR3_USART2SW_SHIFT) /** @defgroup rcc_cfgr3_uart_clksel UART Clock source selections
#define RCC_CFGR3_USART2SW_HSI (3 << RCC_CFGR3_USART2SW_SHIFT) * @{
*/
#define RCC_CFGR3_USARTxSW_PCLK 0x0
#define RCC_CFGR3_USARTxSW_SYSCLK 0x1
#define RCC_CFGR3_USARTxSW_LSE 0x2
#define RCC_CFGR3_USARTxSW_HSI 0x3
/**@}*/
#define RCC_CFGR3_USARTxSW_MASK 0x3
#define RCC_CFGR3_ADCSW (1 << 8) #define RCC_CFGR3_ADCSW (1 << 8)
#define RCC_CFGR3_USBSW (1 << 7) #define RCC_CFGR3_USBSW (1 << 7)
#define RCC_CFGR3_CECSW (1 << 6) #define RCC_CFGR3_CECSW (1 << 6)
#define RCC_CFGR3_I2C1SW (1 << 4) #define RCC_CFGR3_I2C1SW (1 << 4)
#define RCC_CFGR3_USART1SW_SHIFT 0
#define RCC_CFGR3_USART1SW (3 << RCC_CFGR3_USART1SW_SHIFT)
#define RCC_CFGR3_USART1SW_PCLK (0 << RCC_CFGR3_USART1SW_SHIFT)
#define RCC_CFGR3_USART1SW_SYSCLK (1 << RCC_CFGR3_USART1SW_SHIFT)
#define RCC_CFGR3_USART1SW_LSE (2 << RCC_CFGR3_USART1SW_SHIFT)
#define RCC_CFGR3_USART1SW_HSI (3 << RCC_CFGR3_USART1SW_SHIFT)
#define RCC_CFGR3_USARTxSW_MASK 3
/* --- RCC_CFGR3 values ---------------------------------------------------- */
#define RCC_CR2_HSI48CAL_SHIFT 24 #define RCC_CR2_HSI48CAL_SHIFT 24
#define RCC_CR2_HSI48CAL (0xFF << RCC_CR2_HSI48CAL_SHIFT) #define RCC_CR2_HSI48CAL (0xFF << RCC_CR2_HSI48CAL_SHIFT)
#define RCC_CR2_HSI48RDY (1 << 17) #define RCC_CR2_HSI48RDY (1 << 17)

39
include/libopencm3/stm32/f3/rcc.h
View File

@@ -405,36 +405,25 @@
#define RCC_CFGR3_TIM1SW (1 << 8) #define RCC_CFGR3_TIM1SW (1 << 8)
#define RCC_CFGR3_I2C2SW (1 << 5) #define RCC_CFGR3_I2C2SW (1 << 5)
#define RCC_CFGR3_I2C1SW (1 << 4) #define RCC_CFGR3_I2C1SW (1 << 4)
/* UART5SW: UART5 clock source selection */ /** @defgroup rcc_cfgr3_uart_choices UART for clock sour selecting
* @{
*/
#define RCC_CFGR3_UART5SW_SHIFT 22 #define RCC_CFGR3_UART5SW_SHIFT 22
#define RCC_CFGR3_UART5SW_PCLK 0x0
#define RCC_CFGR3_UART5SW_SYSCLK 0x1
#define RCC_CFGR3_UART5SW_LSE 0x2
#define RCC_CFGR3_UART5SW_HSI 0x3
/* UART4SW: UART4 clock source selection */
#define RCC_CFGR3_UART4SW_SHIFT 20 #define RCC_CFGR3_UART4SW_SHIFT 20
#define RCC_CFGR3_UART4SW_PCLK 0x0
#define RCC_CFGR3_UART4SW_SYSCLK 0x1
#define RCC_CFGR3_UART4SW_LSE 0x2
#define RCC_CFGR3_UART4SW_HSI 0x3
/* UART3SW: UART3 clock source selection */
#define RCC_CFGR3_UART3SW_SHIFT 18 #define RCC_CFGR3_UART3SW_SHIFT 18
#define RCC_CFGR3_UART3SW_PCLK 0x0
#define RCC_CFGR3_UART3SW_SYSCLK 0x1
#define RCC_CFGR3_UART3SW_LSE 0x2
#define RCC_CFGR3_UART3SW_HSI 0x3
/* UART2SW: UART2 clock source selection */
#define RCC_CFGR3_UART2SW_SHIFT 16 #define RCC_CFGR3_UART2SW_SHIFT 16
#define RCC_CFGR3_UART2SW_PCLK 0x0
#define RCC_CFGR3_UART2SW_SYSCLK 0x1
#define RCC_CFGR3_UART2SW_LSE 0x2
#define RCC_CFGR3_UART2SW_HSI 0x3
/* UART1SW: UART1 clock source selection */
#define RCC_CFGR3_UART1SW_SHIFT 0 #define RCC_CFGR3_UART1SW_SHIFT 0
#define RCC_CFGR3_UART1SW_PCLK 0x0 /**@}*/
#define RCC_CFGR3_UART1SW_SYSCLK 0x1
#define RCC_CFGR3_UART1SW_LSE 0x2 /** @defgroup rcc_cfgr3_uart_clksel UART Clock source selections
#define RCC_CFGR3_UART1SW_HSI 0x3 * @note This is only used internally.
* @{
*/
#define RCC_CFGR3_UARTxSW_PCLK 0x0
#define RCC_CFGR3_UARTxSW_SYSCLK 0x1
#define RCC_CFGR3_UARTxSW_LSE 0x2
#define RCC_CFGR3_UARTxSW_HSI 0x3
/**@}*/
/* Shared mask for UART clock source. */ /* Shared mask for UART clock source. */
#define RCC_CFGR3_UARTxSW_MASK 0x3 #define RCC_CFGR3_UARTxSW_MASK 0x3

33
include/libopencm3/stm32/f7/rcc.h
View File

@@ -622,33 +622,36 @@
#define RCC_DCKCFGR2_CECSEL (1<<26) #define RCC_DCKCFGR2_CECSEL (1<<26)
#define RCC_DCKCFGR2_LPTIM1SEL_MASK 0x3 #define RCC_DCKCFGR2_LPTIM1SEL_MASK 0x3
#define RCC_DCKCFGR2_LPTIM1SEL_SHIFT 24 #define RCC_DCKCFGR2_LPTIM1SEL_SHIFT 24
#define RCC_DCKCFGR2_I2C4SEL_MASK 0x3 #define RCC_DCKCFGR2_I2CxSEL_MASK 0x3
#define RCC_DCKCFGR2_I2C4SEL_SHIFT 22 #define RCC_DCKCFGR2_I2C4SEL_SHIFT 22
#define RCC_DCKCFGR2_I2C3SEL_MASK 0x3
#define RCC_DCKCFGR2_I2C3SEL_SHIFT 20 #define RCC_DCKCFGR2_I2C3SEL_SHIFT 20
#define RCC_DCKCFGR2_I2C2SEL_MASK 0x3
#define RCC_DCKCFGR2_I2C2SEL_SHIFT 18 #define RCC_DCKCFGR2_I2C2SEL_SHIFT 18
#define RCC_DCKCFGR2_I2C1SEL_MASK 0x3
#define RCC_DCKCFGR2_I2C1SEL_SHIFT 16 #define RCC_DCKCFGR2_I2C1SEL_SHIFT 16
#define RCC_DCKCFGR2_UART8SEL_MASK 0x3
#define RCC_DCKCFGR2_UARTxSEL_MASK 0x3
/** @defgroup rcc_dckcfgr2_uart_choices UART for clock source selecting
* @note This is only used internally.
* @{
*/
#define RCC_DCKCFGR2_UART8SEL_SHIFT 14 #define RCC_DCKCFGR2_UART8SEL_SHIFT 14
#define RCC_DCKCFGR2_UART7SEL_MASK 0x3
#define RCC_DCKCFGR2_UART7SEL_SHIFT 12 #define RCC_DCKCFGR2_UART7SEL_SHIFT 12
#define RCC_DCKCFGR2_USART6SEL_MASK 0x3
#define RCC_DCKCFGR2_USART6SEL_SHIFT 10 #define RCC_DCKCFGR2_USART6SEL_SHIFT 10
#define RCC_DCKCFGR2_UART5SEL_MASK 0x3
#define RCC_DCKCFGR2_UART5SEL_SHIFT 8 #define RCC_DCKCFGR2_UART5SEL_SHIFT 8
#define RCC_DCKCFGR2_UART4SEL_MASK 0x3
#define RCC_DCKCFGR2_UART4SEL_SHIFT 6 #define RCC_DCKCFGR2_UART4SEL_SHIFT 6
#define RCC_DCKCFGR2_UART3SEL_MASK 0x3
#define RCC_DCKCFGR2_UART3SEL_SHIFT 4 #define RCC_DCKCFGR2_UART3SEL_SHIFT 4
#define RCC_DCKCFGR2_UART2SEL_MASK 0x3
#define RCC_DCKCFGR2_UART2SEL_SHIFT 2 #define RCC_DCKCFGR2_UART2SEL_SHIFT 2
#define RCC_DCKCFGR2_UART1SEL_MASK 0x3
#define RCC_DCKCFGR2_UART1SEL_SHIFT 0 #define RCC_DCKCFGR2_UART1SEL_SHIFT 0
#define RCC_DCKCFGR2_UARTxSEL_PCLK 0 /**@}*/
#define RCC_DCKCFGR2_UARTxSEL_SYSCLK 1
#define RCC_DCKCFGR2_UARTxSEL_HSI 2 /** @defgroup rcc_dckcfgr2_uart_clksel UART Clock source selections
* @{
*/
#define RCC_DCKCFGR2_UARTxSEL_PCLK 0x0
#define RCC_DCKCFGR2_UARTxSEL_SYSCLK 0x1
#define RCC_DCKCFGR2_UARTxSEL_HSI 0x2
#define RCC_DCKCFGR2_UARTxSEL_LSE 0x3
/**@}*/
extern uint32_t rcc_ahb_frequency; extern uint32_t rcc_ahb_frequency;

45
include/libopencm3/stm32/g0/rcc.h
View File

@@ -537,23 +537,25 @@
#define RCC_CCIPR_I2S1SEL_I2S_CKIN 3 #define RCC_CCIPR_I2S1SEL_I2S_CKIN 3
/**@}*/ /**@}*/
#define RCC_CCIPR_I2C1SEL_MASK 0x3 #define RCC_CCIPR_I2CxSEL_MASK 0x3
#define RCC_CCIPR_I2C1SEL_SHIFT 12 #define RCC_CCIPR_I2C1SEL_SHIFT 12
#define RCC_CCIPR_I2C2SEL_SHIFT 14
/** @defgroup rcc_ccipr_i2c1sel I2C1SEL I2C1 Clock source selection /** @defgroup rcc_ccipr_i2c1sel I2C1SEL I2C1 Clock source selection
@{*/ @{*/
#define RCC_CCIPR_I2C1SEL_PCLK 0 #define RCC_CCIPR_I2CxSEL_PCLK 0
#define RCC_CCIPR_I2C1SEL_SYSCLK 1 #define RCC_CCIPR_I2CxSEL_SYSCLK 1
#define RCC_CCIPR_I2C1SEL_HSI16 2 #define RCC_CCIPR_I2CxSEL_HSI16 2
/**@}*/ /**@}*/
#define RCC_CCIPR_LPUART1SEL_MASK 0x3 #define RCC_CCIPR_LPUARTxSEL_MASK 0x3
#define RCC_CCIPR_LPUART1SEL_SHIFT 10 #define RCC_CCIPR_LPUART1SEL_SHIFT 10
/** @defgroup rcc_ccipr_lpuart1sel LPUART1SEL LPUART1 Clock source selection #define RCC_CCIPR_LPUART2SEL_SHIFT 8
/** @defgroup rcc_ccipr_lpuartxsel LPUARTxSEL LPUART1 Clock source selection
@{*/ @{*/
#define RCC_CCIPR_LPUART1SEL_PCLK 0 #define RCC_CCIPR_LPUARTxSEL_PCLK 0
#define RCC_CCIPR_LPUART1SEL_SYSCLK 1 #define RCC_CCIPR_LPUARTxSEL_SYSCLK 1
#define RCC_CCIPR_LPUART1SEL_HSI16 2 #define RCC_CCIPR_LPUARTxSEL_HSI16 2
#define RCC_CCIPR_LPUART1SEL_LSE 3 #define RCC_CCIPR_LPUARTxSEL_LSE 3
/**@}*/ /**@}*/
#define RCC_CCIPR_CECSEL_MASK 0x1 #define RCC_CCIPR_CECSEL_MASK 0x1
@@ -564,25 +566,18 @@
#define RCC_CCIPR_CECSEL_LSE 1 #define RCC_CCIPR_CECSEL_LSE 1
/**@}*/ /**@}*/
#define RCC_CCIPR_USART2SEL_MASK 0x3 #define RCC_CCIPR_USARTxSEL_MASK RCC_CCIPR_LPUARTxSEL_MASK
#define RCC_CCIPR_USART3SEL_SHIFT 4
#define RCC_CCIPR_USART2SEL_SHIFT 2 #define RCC_CCIPR_USART2SEL_SHIFT 2
/** @defgroup rcc_ccipr_usart2sel USART2SEL USART2 Clock source selection #define RCC_CCIPR_USART1SEL_SHIFT 0
/** @defgroup rcc_ccipr_usartxsel USARTxSEL USARTx Clock source selection
@{*/ @{*/
#define RCC_CCIPR_USART2SEL_PCLK 0 #define RCC_CCIPR_USARTxSEL_PCLK RCC_CCIPR_LPUARTxSEL_PCLK
#define RCC_CCIPR_USART2SEL_SYSCLK 1 #define RCC_CCIPR_USARTxSEL_SYSCLK RCC_CCIPR_LPUARTxSEL_SYSCLK
#define RCC_CCIPR_USART2SEL_HSI16 2 #define RCC_CCIPR_USARTxSEL_HSI16 RCC_CCIPR_LPUARTxSEL_HSI16
#define RCC_CCIPR_USART2SEL_LSE 3 #define RCC_CCIPR_USARTxSEL_LSE RCC_CCIPR_LPUARTxSEL_LSE
/**@}*/ /**@}*/
#define RCC_CCIPR_USART1SEL_MASK 0x3
#define RCC_CCIPR_USART1SEL_SHIFT 0
/** @defgroup rcc_ccipr_usart1sel USART1SEL USART1 Clock source selection
@{*/
#define RCC_CCIPR_USART1SEL_PCLK 0
#define RCC_CCIPR_USART1SEL_SYSCLK 1
#define RCC_CCIPR_USART1SEL_HSI16 2
#define RCC_CCIPR_USART1SEL_LSE 3
/**@}*/
/**@}*/ /**@}*/
/** @defgroup rcc_bdcr BDCR Backup Domain Control Register /** @defgroup rcc_bdcr BDCR Backup Domain Control Register

62
include/libopencm3/stm32/l0/rcc.h
View File

@@ -443,38 +443,48 @@
#define RCC_CCIPR_LPTIM1SEL_SHIFT 18 #define RCC_CCIPR_LPTIM1SEL_SHIFT 18
#define RCC_CCIPR_LPTIM1SEL_MASK 0x3 #define RCC_CCIPR_LPTIM1SEL_MASK 0x3
#define RCC_CCIPR_I2C3SEL_APB 0 /** @defgroup rcc_ccipr_i2c_clksel I2C Clock source selections
#define RCC_CCIPR_I2C3SEL_SYS 1 * @{
#define RCC_CCIPR_I2C3SEL_HSI16 2 */
#define RCC_CCIPR_I2CxSEL_PCLK 0
#define RCC_CCIPR_I2CxSEL_SYSCLK 1
#define RCC_CCIPR_I2CxSEL_HSI 2
/**@}*/
#define RCC_CCIPR_I2CxSEL_MASK 0x3
/** @defgroup rcc_ccipr_i2c_choices I2C for clock source selecting
* @note This is only used internally.
* @{
*/
#define RCC_CCIPR_I2C3SEL_SHIFT 16 #define RCC_CCIPR_I2C3SEL_SHIFT 16
#define RCC_CCIPR_I2C3SEL_MASK 0x3
#define RCC_CCIPR_I2C1SEL_APB 0
#define RCC_CCIPR_I2C1SEL_SYS 1
#define RCC_CCIPR_I2C1SEL_HSI16 2
#define RCC_CCIPR_I2C1SEL_SHIFT 12 #define RCC_CCIPR_I2C1SEL_SHIFT 12
#define RCC_CCIPR_I2C1SEL_MASK 0x3 /**@}*/
#define RCC_CCIPR_LPUART1SEL_APB 0 /** @defgroup rcc_ccipr_uart_clksel UART Clock source selections
#define RCC_CCIPR_LPUART1SEL_SYS 1 * @{
#define RCC_CCIPR_LPUART1SEL_HSI16 2 */
#define RCC_CCIPR_LPUART1SEL_LSE 3 #define RCC_CCIPR_USARTxSEL_PCLK 0
#define RCC_CCIPR_USARTxSEL_SYSCLK 1
#define RCC_CCIPR_USARTxSEL_HSI 2
#define RCC_CCIPR_USARTxSEL_LSE 3
/**@}*/
#define RCC_CCIPR_LPUARTxSEL_PCLK RCC_CCIPR_USARTxSEL_PCLK
#define RCC_CCIPR_LPUARTxSEL_SYSCK RCC_CCIPR_USARTxSEL_SYSCLK
#define RCC_CCIPR_LPUARTxSEL_HSI RCC_CCIPR_USARTxSEL_HSI
#define RCC_CCIPR_LPUARTxSEL_LSE RCC_CCIPR_USARTxSEL_LSE
#define RCC_CCIPR_LPUARTxSEL_MASK 0x3
#define RCC_CCIPR_USARTxSEL_MASK RCC_CCIPR_LPUARTxSEL_MASK
/** @defgroup rcc_ccipr_uart_choices UART for clock source selecting
* @note This is only used internally.
* @{
*/
#define RCC_CCIPR_LPUART1SEL_SHIFT 10 #define RCC_CCIPR_LPUART1SEL_SHIFT 10
#define RCC_CCIPR_LPUART1SEL_MASK 0x3
#define RCC_CCIPR_USART2SEL_APB 0
#define RCC_CCIPR_USART2SEL_SYS 1
#define RCC_CCIPR_USART2SEL_HSI16 2
#define RCC_CCIPR_USART2SEL_LSE 3
#define RCC_CCIPR_USART2SEL_SHIFT 2 #define RCC_CCIPR_USART2SEL_SHIFT 2
#define RCC_CCIPR_USART2SEL_MASK 0x3
#define RCC_CCIPR_USART1SEL_APB 0
#define RCC_CCIPR_USART1SEL_SYS 1
#define RCC_CCIPR_USART1SEL_HSI16 2
#define RCC_CCIPR_USART1SEL_LSE 3
#define RCC_CCIPR_USART1SEL_SHIFT 0 #define RCC_CCIPR_USART1SEL_SHIFT 0
#define RCC_CCIPR_USART1SEL_MASK 0x3 /**@}*/
/* --- RCC_CSRT - Control/Status register */ /* --- RCC_CSRT - Control/Status register */

8
lib/stm32/f0/rcc.c
View File

@@ -630,11 +630,13 @@ static uint32_t rcc_get_usart_clksel_freq(uint8_t shift) {
uint8_t clksel = (RCC_CFGR3 >> shift) & RCC_CFGR3_USARTxSW_MASK; uint8_t clksel = (RCC_CFGR3 >> shift) & RCC_CFGR3_USARTxSW_MASK;
uint8_t hpre = (RCC_CFGR >> RCC_CFGR_HPRE_SHIFT) & RCC_CFGR_HPRE_MASK; uint8_t hpre = (RCC_CFGR >> RCC_CFGR_HPRE_SHIFT) & RCC_CFGR_HPRE_MASK;
switch (clksel) { switch (clksel) {
case RCC_CFGR3_USART1SW_PCLK: case RCC_CFGR3_USARTxSW_PCLK:
return rcc_apb1_frequency; return rcc_apb1_frequency;
case RCC_CFGR3_USART1SW_SYSCLK: case RCC_CFGR3_USARTxSW_SYSCLK:
return rcc_ahb_frequency * rcc_get_div_from_hpre(hpre); return rcc_ahb_frequency * rcc_get_div_from_hpre(hpre);
case RCC_CFGR3_USART1SW_HSI: case RCC_CFGR3_USARTxSW_LSE:
return 32768;
case RCC_CFGR3_USARTxSW_HSI:
return 8000000U; return 8000000U;
} }
cm3_assert_not_reached(); cm3_assert_not_reached();

8
lib/stm32/f3/rcc.c
View File

@@ -498,11 +498,13 @@ static uint32_t rcc_get_usart_clksel_freq(uint32_t apb_clk, uint8_t shift) {
uint8_t clksel = (RCC_CFGR3 >> shift) & RCC_CFGR3_UARTxSW_MASK; uint8_t clksel = (RCC_CFGR3 >> shift) & RCC_CFGR3_UARTxSW_MASK;
uint8_t hpre = (RCC_CFGR >> RCC_CFGR_HPRE_SHIFT) & RCC_CFGR_HPRE_MASK; uint8_t hpre = (RCC_CFGR >> RCC_CFGR_HPRE_SHIFT) & RCC_CFGR_HPRE_MASK;
switch (clksel) { switch (clksel) {
case RCC_CFGR3_UART1SW_PCLK: case RCC_CFGR3_UARTxSW_PCLK:
return apb_clk; return apb_clk;
case RCC_CFGR3_UART1SW_SYSCLK: case RCC_CFGR3_UARTxSW_SYSCLK:
return rcc_ahb_frequency * rcc_get_div_from_hpre(hpre); return rcc_ahb_frequency * rcc_get_div_from_hpre(hpre);
case RCC_CFGR3_UART1SW_HSI: case RCC_CFGR3_UARTxSW_LSE:
return 32768;
case RCC_CFGR3_UARTxSW_HSI:
return 8000000U; return 8000000U;
} }
cm3_assert_not_reached(); cm3_assert_not_reached();

8
lib/stm32/f7/rcc.c
View File

@@ -485,18 +485,20 @@ void rcc_clock_setup_hsi(const struct rcc_clock_scale *clock)
} }
static uint32_t rcc_usart_i2c_clksel_freq(uint32_t apb_clk, uint8_t shift) { static uint32_t rcc_usart_i2c_clksel_freq(uint32_t apb_clk, uint8_t shift) {
uint8_t clksel = (RCC_DCKCFGR2 >> shift) & RCC_DCKCFGR2_UART1SEL_MASK; uint8_t clksel = (RCC_DCKCFGR2 >> shift) & RCC_DCKCFGR2_UARTxSEL_MASK;
uint8_t hpre = (RCC_CFGR >> RCC_CFGR_HPRE_SHIFT) & RCC_CFGR_HPRE_MASK; uint8_t hpre = (RCC_CFGR >> RCC_CFGR_HPRE_SHIFT) & RCC_CFGR_HPRE_MASK;
switch (clksel) { switch (clksel) {
case RCC_DCKCFGR2_UARTxSEL_PCLK: case RCC_DCKCFGR2_UARTxSEL_PCLK:
return apb_clk; return apb_clk;
case RCC_DCKCFGR2_UARTxSEL_SYSCLK: case RCC_DCKCFGR2_UARTxSEL_SYSCLK:
return rcc_ahb_frequency * rcc_get_div_from_hpre(hpre); return rcc_ahb_frequency * rcc_get_div_from_hpre(hpre);
/* This case is only valid for uarts, not for i2c! */
case RCC_DCKCFGR2_UARTxSEL_LSE:
return 32768;
case RCC_DCKCFGR2_UARTxSEL_HSI: case RCC_DCKCFGR2_UARTxSEL_HSI:
return 16000000U; return 16000000U;
default:
cm3_assert_not_reached();
} }
cm3_assert_not_reached();
} }
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/

28
lib/stm32/g0/rcc.c
View File

@@ -532,11 +532,11 @@ void rcc_set_peripheral_clk_sel(uint32_t periph, uint32_t sel)
break; break;
case USART2_BASE: case USART2_BASE:
shift = RCC_CCIPR_USART2SEL_SHIFT; shift = RCC_CCIPR_USART2SEL_SHIFT;
mask = RCC_CCIPR_USART2SEL_MASK; mask = RCC_CCIPR_USARTxSEL_MASK;
break; break;
case USART1_BASE: case USART1_BASE:
shift = RCC_CCIPR_USART1SEL_SHIFT; shift = RCC_CCIPR_USART1SEL_SHIFT;
mask = RCC_CCIPR_USART1SEL_MASK; mask = RCC_CCIPR_USARTxSEL_MASK;
break; break;
default: default:
cm3_assert_not_reached(); cm3_assert_not_reached();
@@ -548,14 +548,16 @@ void rcc_set_peripheral_clk_sel(uint32_t periph, uint32_t sel)
} }
static uint32_t rcc_get_clksel_freq(uint8_t shift) { static uint32_t rcc_get_clksel_freq(uint8_t shift) {
uint8_t clksel = (RCC_CCIPR >> shift) & RCC_CCIPR_USART1SEL_MASK; uint8_t clksel = (RCC_CCIPR >> shift) & RCC_CCIPR_USARTxSEL_MASK;
uint8_t hpre = (RCC_CFGR >> RCC_CFGR_HPRE_SHIFT) & RCC_CFGR_HPRE_MASK; uint8_t hpre = (RCC_CFGR >> RCC_CFGR_HPRE_SHIFT) & RCC_CFGR_HPRE_MASK;
switch (clksel) { switch (clksel) {
case RCC_CCIPR_USART1SEL_PCLK: case RCC_CCIPR_USARTxSEL_PCLK:
return rcc_apb1_frequency; return rcc_apb1_frequency;
case RCC_CCIPR_USART1SEL_SYSCLK: case RCC_CCIPR_USARTxSEL_SYSCLK:
return rcc_ahb_frequency * rcc_get_div_from_hpre(hpre); return rcc_ahb_frequency * rcc_get_div_from_hpre(hpre);
case RCC_CCIPR_USART1SEL_HSI16: case RCC_CCIPR_USARTxSEL_LSE:
return 32768;
case RCC_CCIPR_USARTxSEL_HSI16:
return 16000000U; return 16000000U;
} }
cm3_assert_not_reached(); cm3_assert_not_reached();
@@ -571,11 +573,14 @@ uint32_t rcc_get_usart_clk_freq(uint32_t usart)
return rcc_get_clksel_freq(RCC_CCIPR_USART1SEL_SHIFT); return rcc_get_clksel_freq(RCC_CCIPR_USART1SEL_SHIFT);
} else if (usart == USART2_BASE) { } else if (usart == USART2_BASE) {
return rcc_get_clksel_freq(RCC_CCIPR_USART2SEL_SHIFT); return rcc_get_clksel_freq(RCC_CCIPR_USART2SEL_SHIFT);
} else if (usart == USART3_BASE) {
return rcc_get_clksel_freq(RCC_CCIPR_USART3SEL_SHIFT);
} else if (usart == LPUART1_BASE) { } else if (usart == LPUART1_BASE) {
return rcc_get_clksel_freq(RCC_CCIPR_LPUART1SEL_SHIFT); return rcc_get_clksel_freq(RCC_CCIPR_LPUART1SEL_SHIFT);
} else { } else if (usart == LPUART2_BASE) {
return rcc_apb1_frequency; return rcc_get_clksel_freq(RCC_CCIPR_LPUART2SEL_SHIFT);
} }
cm3_assert_not_reached();
} }
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
@@ -593,13 +598,14 @@ uint32_t rcc_get_timer_clk_freq(uint32_t timer __attribute__((unused)))
/** @brief Get the peripheral clock speed for the I2C device at base specified. /** @brief Get the peripheral clock speed for the I2C device at base specified.
* @param i2c Base address of I2C to get clock frequency for. * @param i2c Base address of I2C to get clock frequency for.
*/ */
uint32_t rcc_get_i2c_clk_freq(uint32_t i2c __attribute__((unused))) uint32_t rcc_get_i2c_clk_freq(uint32_t i2c)
{ {
if (i2c == I2C1_BASE) { if (i2c == I2C1_BASE) {
return rcc_get_clksel_freq(RCC_CCIPR_I2C1SEL_SHIFT); return rcc_get_clksel_freq(RCC_CCIPR_I2C1SEL_SHIFT);
} else { } else if (i2c == I2C2_BASE) {
return rcc_apb1_frequency; return rcc_get_clksel_freq(RCC_CCIPR_I2C2SEL_SHIFT);
} }
cm3_assert_not_reached();
} }
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/

16
lib/stm32/h7/rcc.c
View File

@@ -277,17 +277,21 @@ uint32_t rcc_get_usart_clk_freq(uint32_t usart)
} }
/* Based on extracted clksel value, return the clock. */ /* Based on extracted clksel value, return the clock. */
if (clksel == RCC_D2CCIP2R_USARTSEL_PCLK) { switch(clksel) {
case RCC_D2CCIP2R_USARTSEL_PCLK:
return pclk; return pclk;
} else if (clksel == RCC_D2CCIP2R_USARTSEL_PLL2Q) { case RCC_D2CCIP2R_USARTSEL_PLL2Q:
return rcc_clock_tree.pll2.q_mhz * HZ_PER_MHZ; return rcc_clock_tree.pll2.q_mhz * HZ_PER_MHZ;
} else if (clksel == RCC_D2CCIP2R_USARTSEL_PLL3Q) { case RCC_D2CCIP2R_USARTSEL_PLL3Q:
return rcc_clock_tree.pll3.q_mhz * HZ_PER_MHZ; return rcc_clock_tree.pll3.q_mhz * HZ_PER_MHZ;
} else if (clksel == RCC_D2CCIP2R_USARTSEL_HSI) { case RCC_D2CCIP2R_USARTSEL_HSI:
return RCC_HSI_BASE_FREQUENCY; return RCC_HSI_BASE_FREQUENCY;
} else { case RCC_D2CCIP2R_USARTSEL_CSI:
return 0U; return 4000000;
case RCC_D2CCIP2R_USARTSEL_LSE:
return 32768;
} }
cm3_assert_not_reached();
} }
uint32_t rcc_get_timer_clk_freq(uint32_t timer __attribute__((unused))) uint32_t rcc_get_timer_clk_freq(uint32_t timer __attribute__((unused)))

24
lib/stm32/l0/rcc.c
View File

@@ -420,7 +420,7 @@ void rcc_set_lptim1_sel(uint32_t lptim1_sel)
*/ */
void rcc_set_lpuart1_sel(uint32_t lpuart1_sel) void rcc_set_lpuart1_sel(uint32_t lpuart1_sel)
{ {
RCC_CCIPR &= ~(RCC_CCIPR_LPUART1SEL_MASK << RCC_CCIPR_LPTIM1SEL_SHIFT); RCC_CCIPR &= ~(RCC_CCIPR_LPUARTxSEL_MASK << RCC_CCIPR_LPTIM1SEL_SHIFT);
RCC_CCIPR |= (lpuart1_sel << RCC_CCIPR_LPTIM1SEL_SHIFT); RCC_CCIPR |= (lpuart1_sel << RCC_CCIPR_LPTIM1SEL_SHIFT);
} }
@@ -431,7 +431,7 @@ void rcc_set_lpuart1_sel(uint32_t lpuart1_sel)
*/ */
void rcc_set_usart1_sel(uint32_t usart1_sel) void rcc_set_usart1_sel(uint32_t usart1_sel)
{ {
RCC_CCIPR &= ~(RCC_CCIPR_USART1SEL_MASK << RCC_CCIPR_USART1SEL_SHIFT); RCC_CCIPR &= ~(RCC_CCIPR_USARTxSEL_MASK << RCC_CCIPR_USART1SEL_SHIFT);
RCC_CCIPR |= (usart1_sel << RCC_CCIPR_USART1SEL_SHIFT); RCC_CCIPR |= (usart1_sel << RCC_CCIPR_USART1SEL_SHIFT);
} }
@@ -442,7 +442,7 @@ void rcc_set_usart1_sel(uint32_t usart1_sel)
*/ */
void rcc_set_usart2_sel(uint32_t usart2_sel) void rcc_set_usart2_sel(uint32_t usart2_sel)
{ {
RCC_CCIPR &= ~(RCC_CCIPR_USART2SEL_MASK << RCC_CCIPR_USART2SEL_SHIFT); RCC_CCIPR &= ~(RCC_CCIPR_USARTxSEL_MASK << RCC_CCIPR_USART2SEL_SHIFT);
RCC_CCIPR |= (usart2_sel << RCC_CCIPR_USART2SEL_SHIFT); RCC_CCIPR |= (usart2_sel << RCC_CCIPR_USART2SEL_SHIFT);
} }
@@ -464,27 +464,27 @@ void rcc_set_peripheral_clk_sel(uint32_t periph, uint32_t sel)
case I2C3_BASE: case I2C3_BASE:
shift = RCC_CCIPR_I2C3SEL_SHIFT; shift = RCC_CCIPR_I2C3SEL_SHIFT;
mask = RCC_CCIPR_I2C3SEL_MASK; mask = RCC_CCIPR_I2CxSEL_MASK;
break; break;
case I2C1_BASE: case I2C1_BASE:
shift = RCC_CCIPR_I2C1SEL_SHIFT; shift = RCC_CCIPR_I2C1SEL_SHIFT;
mask = RCC_CCIPR_I2C1SEL_MASK; mask = RCC_CCIPR_I2CxSEL_MASK;
break; break;
case LPUART1_BASE: case LPUART1_BASE:
shift = RCC_CCIPR_LPUART1SEL_SHIFT; shift = RCC_CCIPR_LPUART1SEL_SHIFT;
mask = RCC_CCIPR_LPUART1SEL_MASK; mask = RCC_CCIPR_LPUARTxSEL_MASK;
break; break;
case USART2_BASE: case USART2_BASE:
shift = RCC_CCIPR_USART2SEL_SHIFT; shift = RCC_CCIPR_USART2SEL_SHIFT;
mask = RCC_CCIPR_USART2SEL_MASK; mask = RCC_CCIPR_USARTxSEL_MASK;
break; break;
case USART1_BASE: case USART1_BASE:
shift = RCC_CCIPR_USART1SEL_SHIFT; shift = RCC_CCIPR_USART1SEL_SHIFT;
mask = RCC_CCIPR_USART1SEL_MASK; mask = RCC_CCIPR_USARTxSEL_MASK;
break; break;
default: default:
@@ -498,14 +498,14 @@ void rcc_set_peripheral_clk_sel(uint32_t periph, uint32_t sel)
/* Helper to calculate the frequency of a clksel based clock. */ /* Helper to calculate the frequency of a clksel based clock. */
static uint32_t rcc_uart_i2c_clksel_freq_hz(uint32_t apb_clk, uint8_t shift) { static uint32_t rcc_uart_i2c_clksel_freq_hz(uint32_t apb_clk, uint8_t shift) {
uint8_t clksel = (RCC_CCIPR >> shift) & RCC_CCIPR_I2C1SEL_MASK; uint8_t clksel = (RCC_CCIPR >> shift) & RCC_CCIPR_I2CxSEL_MASK;
uint8_t hpre = (RCC_CFGR >> RCC_CFGR_HPRE_SHIFT) & RCC_CFGR_HPRE_MASK; uint8_t hpre = (RCC_CFGR >> RCC_CFGR_HPRE_SHIFT) & RCC_CFGR_HPRE_MASK;
switch (clksel) { switch (clksel) {
case RCC_CCIPR_USART1SEL_APB: case RCC_CCIPR_USARTxSEL_PCLK:
return apb_clk; return apb_clk;
case RCC_CCIPR_USART1SEL_SYS: case RCC_CCIPR_USARTxSEL_SYSCLK:
return rcc_ahb_frequency * rcc_get_div_from_hpre(hpre); return rcc_ahb_frequency * rcc_get_div_from_hpre(hpre);
case RCC_CCIPR_USART1SEL_HSI16: case RCC_CCIPR_USARTxSEL_HSI:
return 16000000U; return 16000000U;
} }
cm3_assert_not_reached(); cm3_assert_not_reached();