From 8526d7095c65bec5abbafed651756ebbf29e7616 Mon Sep 17 00:00:00 2001 From: Benedikt Spranger Date: Sun, 23 Jul 2023 11:09:00 +0200 Subject: [PATCH] stm32g4: rcc: Add support for 24MHz external clocks The ST Nucleo 64 boards NUCLEO-G431RB, NUCLEO-G474RE and NUCLEO-G491RE are equipped with a 24 MHz crystal. Add RCC clock support for these boards. Signed-off-by: Benedikt Spranger --- include/libopencm3/stm32/g4/rcc.h | 1 + lib/stm32/g4/rcc.c | 75 ++++++++++++++++++++++++++++++- 2 files changed, 75 insertions(+), 1 deletion(-) diff --git a/include/libopencm3/stm32/g4/rcc.h b/include/libopencm3/stm32/g4/rcc.h index b1acf9fc..a456cc14 100644 --- a/include/libopencm3/stm32/g4/rcc.h +++ b/include/libopencm3/stm32/g4/rcc.h @@ -766,6 +766,7 @@ extern const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_3V3_END]; extern const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END]; extern const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END]; extern const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END]; +extern const struct rcc_clock_scale rcc_hse_24mhz_3v3[RCC_CLOCK_3V3_END]; enum rcc_osc { RCC_HSI48, diff --git a/lib/stm32/g4/rcc.c b/lib/stm32/g4/rcc.c index 5d234c61..596817d7 100644 --- a/lib/stm32/g4/rcc.c +++ b/lib/stm32/g4/rcc.c @@ -357,7 +357,80 @@ const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = { }, }; - +const struct rcc_clock_scale rcc_hse_24mhz_3v3[RCC_CLOCK_3V3_END] = { + { /* 24MHz */ + .pllm = 2, + .plln = 8, + .pllp = 0, + .pllq = 2, + .pllr = 4, + .pll_source = RCC_PLLCFGR_PLLSRC_HSE, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPREx_NODIV, + .ppre2 = RCC_CFGR_PPREx_NODIV, + .vos_scale = PWR_SCALE2, + .boost = false, + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN, + .flash_waitstates = 1, + .ahb_frequency = 24e6, + .apb1_frequency = 24e6, + .apb2_frequency = 24e6, + }, + { /* 48MHz */ + .pllm = 2, + .plln = 8, + .pllp = 0, + .pllq = 2, + .pllr = 2, + .pll_source = RCC_PLLCFGR_PLLSRC_HSE, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPREx_NODIV, + .ppre2 = RCC_CFGR_PPREx_NODIV, + .vos_scale = PWR_SCALE1, + .boost = false, + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN, + .flash_waitstates = 1, + .ahb_frequency = 48e6, + .apb1_frequency = 48e6, + .apb2_frequency = 48e6, + }, + { /* 96MHz */ + .pllm = 2, + .plln = 16, + .pllp = 0, + .pllq = 4, + .pllr = 2, + .pll_source = RCC_PLLCFGR_PLLSRC_HSE, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPREx_NODIV, + .ppre2 = RCC_CFGR_PPREx_NODIV, + .vos_scale = PWR_SCALE1, + .boost = false, + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN, + .flash_waitstates = 3, + .ahb_frequency = 96e6, + .apb1_frequency = 96e6, + .apb2_frequency = 96e6, + }, + { /* 170MHz */ + .pllm = 6, + .plln = 85, + .pllp = 0, + .pllq = 0, /* USB requires CRS at this speed. */ + .pllr = 2, + .pll_source = RCC_PLLCFGR_PLLSRC_HSE, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre1 = RCC_CFGR_PPREx_NODIV, + .ppre2 = RCC_CFGR_PPREx_NODIV, + .vos_scale = PWR_SCALE1, + .boost = true, + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN, + .flash_waitstates = 4, + .ahb_frequency = 170e6, + .apb1_frequency = 170e6, + .apb2_frequency = 170e6, + }, +}; void rcc_osc_ready_int_clear(enum rcc_osc osc) {