stm32/h7: Fixed the QuadSPI headers not working with multiple peripehrals
This commit is contained in:
dragonmux
committed by
Piotr Esden-Tempski
Piotr Esden-Tempski
parent
c38a37c387
commit
83e571db67
@@ -10,45 +10,73 @@
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* @{
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*/
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/** QUADSPI Control register */
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#define QUADSPI_CR MMIO32(QUADSPI_BASE + 0x0U)
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#define QUADSPI_CR(quadspi_base) MMIO32(quadspi_base + 0x0U)
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#define QUADSPI1_CR QUADSPI_CR(QUADSPI1_BASE)
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#define QUADSPI2_CR QUADSPI_CR(QUADSPI2_BASE)
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/** QUADSPI Device Configuration */
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#define QUADSPI_DCR MMIO32(QUADSPI_BASE + 0x4U)
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#define QUADSPI_DCR(quadspi_base) MMIO32(quadspi_base + 0x4U)
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#define QUADSPI1_DCR QUADSPI_DCR(QUADSPI1_BASE)
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#define QUADSPI2_DCR QUADSPI_DCR(QUADSPI2_BASE)
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/** QUADSPI Status Register */
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#define QUADSPI_SR MMIO32(QUADSPI_BASE + 0x8U)
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#define QUADSPI_SR(quadspi_base) MMIO32(quadspi_base + 0x8U)
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#define QUADSPI1_SR QUADSPI_SR(QUADSPI1_BASE)
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#define QUADSPI2_SR QUADSPI_SR(QUADSPI2_BASE)
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/** QUADSPI Flag Clear Register */
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#define QUADSPI_FCR MMIO32(QUADSPI_BASE + 0xCU)
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#define QUADSPI_FCR(quadspi_base) MMIO32(quadspi_base + 0xCU)
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#define QUADSPI1_FCR QUADSPI_FCR(QUADSPI1_BASE)
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#define QUADSPI2_FCR QUADSPI_FCR(QUADSPI2_BASE)
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/** QUADSPI Data Length Register */
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#define QUADSPI_DLR MMIO32(QUADSPI_BASE + 0x10U)
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#define QUADSPI_DLR(quadspi_base) MMIO32(quadspi_base + 0x10U)
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#define QUADSPI1_DLR QUADSPI_DLR(QUADSPI1_BASE)
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#define QUADSPI2_DLR QUADSPI_DLR(QUADSPI2_BASE)
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/** QUADSPI Communication Configuration Register */
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#define QUADSPI_CCR MMIO32(QUADSPI_BASE + 0x14U)
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#define QUADSPI_CCR(quadspi_base) MMIO32(quadspi_base + 0x14U)
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#define QUADSPI1_CCR QUADSPI_CCR(QUADSPI1_BASE)
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#define QUADSPI2_CCR QUADSPI_CCR(QUADSPI2_BASE)
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/** QUADSPI address register */
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#define QUADSPI_AR MMIO32(QUADSPI_BASE + 0x18U)
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#define QUADSPI_AR(quadspi_base) MMIO32(quadspi_base + 0x18U)
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#define QUADSPI1_AR QUADSPI_AR(QUADSPI1_BASE)
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#define QUADSPI2_AR QUADSPI_AR(QUADSPI2_BASE)
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/** QUADSPI alternate bytes register */
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#define QUADSPI_ABR MMIO32(QUADSPI_BASE + 0x1CU)
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#define QUADSPI_ABR(quadspi_base) MMIO32(quadspi_base + 0x1CU)
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#define QUADSPI1_ABR QUADSPI_ABR(QUADSPI1_BASE)
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#define QUADSPI2_ABR QUADSPI_ABR(QUADSPI2_BASE)
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/** QUADSPI data register */
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#define QUADSPI_DR MMIO32(QUADSPI_BASE + 0x20U)
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#define QUADSPI_DR(quadspi_base) MMIO32(quadspi_base + 0x20U)
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#define QUADSPI1_DR QUADSPI_DR(QUADSPI1_BASE)
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#define QUADSPI2_DR QUADSPI_DR(QUADSPI2_BASE)
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/** BYTE addressable version for fetching bytes from the interface */
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#define QUADSPI_BYTE_DR MMIO8(QUADSPI_BASE + 0x20U)
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#define QUADSPI_BYTE_DR(quadspi_base) MMIO8(quadspi_base + 0x20U)
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#define QUADSPI1_BYTE_DR QUADSPI_BYTE_DR(QUADSPI1_BASE)
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#define QUADSPI2_BYTE_DR QUADSPI_BYTE_DR(QUADSPI2_BASE)
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/** QUADSPI polling status */
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#define QUADSPI_PSMKR MMIO32(QUADSPI_BASE + 0x24U)
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#define QUADSPI_PSMKR(quadspi_base) MMIO32(quadspi_base + 0x24U)
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#define QUADSPI1_PSMKR QUADSPI_PSMKR(QUADSPI1_BASE)
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#define QUADSPI2_PSMKR QUADSPI_PSMKR(QUADSPI2_BASE)
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/** QUADSPI polling status match */
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#define QUADSPI_PSMAR MMIO32(QUADSPI_BASE + 0x28U)
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#define QUADSPI_PSMAR(quadspi_base) MMIO32(quadspi_base + 0x28U)
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#define QUADSPI1_PSMAR QUADSPI_PSMAR(QUADSPI1_BASE)
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#define QUADSPI2_PSMAR QUADSPI_PSMAR(QUADSPI2_BASE)
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/** QUADSPI polling interval register */
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#define QUADSPI_PIR MMIO32(QUADSPI_BASE + 0x2CU)
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#define QUADSPI_PIR(quadspi_base) MMIO32(quadspi_base + 0x2CU)
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#define QUADSPI1_PIR QUADSPI_PIR(QUADSPI1_BASE)
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#define QUADSPI2_PIR QUADSPI_PIR(QUADSPI2_BASE)
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/** QUADSPI low power timeout */
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#define QUADSPI_LPTR MMIO32(QUADSPI_BASE + 0x30U)
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#define QUADSPI_LPTR(quadspi_base) MMIO32(quadspi_base + 0x30U)
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#define QUADSPI1_LPTR QUADSPI_LPTR(QUADSPI1_BASE)
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#define QUADSPI2_LPTR QUADSPI_LPTR(QUADSPI2_BASE)
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/**@}*/
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#define QUADSPI_CR_PRESCALE_MASK 0xff
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@@ -163,12 +191,12 @@ BEGIN_DECLS
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/**
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* Enable the quadspi peripheral.
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*/
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void quadspi_enable(void);
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void quadspi_enable(uint32_t quadspi);
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/**
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* Disable the quadspi peripheral.
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*/
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void quadspi_disable(void);
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void quadspi_disable(uint32_t quadspi);
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END_DECLS
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@@ -5,12 +5,28 @@
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* @{
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*/
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#pragma once
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#ifndef LIBOPENCM3_QUADSPI_H
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#define LIBOPENCM3_QUADSPI_H
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/stm32/common/quadspi_common_v1.h>
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/**@{*/
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/** @defgroup quadspi_reg_base QuadSPI register base addresses
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* Holds all the QuadSPI peripherals supported.
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* @{
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*/
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#define QUADSPI1 QUADSPI1_BASE
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#define QUADSPI2 QUADSPI2_BASE
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/**@}*/
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BEGIN_DECLS
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END_DECLS
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/** Enable free running clock mode, for testing */
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#define QUADSPI_CCR_FRCM (1 << 29)
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/**@}*/
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/**@}*/
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#endif
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@@ -1,12 +1,12 @@
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#include <libopencm3/stm32/quadspi.h>
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void quadspi_enable(void)
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void quadspi_enable(uint32_t quadspi)
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{
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QUADSPI_CR |= QUADSPI_CR_EN;
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QUADSPI_CR(quadspi) |= QUADSPI_CR_EN;
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}
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void quadspi_disable(void)
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void quadspi_disable(uint32_t quadspi)
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{
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QUADSPI_CR &= ~QUADSPI_CR_EN;
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}
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QUADSPI_CR(quadspi) &= ~QUADSPI_CR_EN;
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}
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