More progress towards L1 support.
Believe gpio is complete, but untested without finishing at least the RCC defines. RCC defines are a work in progress
This commit is contained in:
Karl Palsson
241
include/libopencm3/stm32/l1/gpio.h
Normal file
241
include/libopencm3/stm32/l1/gpio.h
Normal file
@@ -0,0 +1,241 @@
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2012 Piotr Esden-Tempski <piotr@esden.net>
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* Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
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||||
*
|
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
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* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_GPIO_H
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#define LIBOPENCM3_GPIO_H
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/cm3/common.h>
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/* --- Convenience macros -------------------------------------------------- */
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/* GPIO port base addresses (for convenience) */
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#define GPIOA GPIO_PORT_A_BASE
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#define GPIOB GPIO_PORT_B_BASE
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#define GPIOC GPIO_PORT_C_BASE
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#define GPIOD GPIO_PORT_D_BASE
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#define GPIOE GPIO_PORT_E_BASE
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#define GPIOH GPIO_PORT_H_BASE
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/* GPIO number definitions (for convenience) */
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#define GPIO0 (1 << 0)
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#define GPIO1 (1 << 1)
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#define GPIO2 (1 << 2)
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#define GPIO3 (1 << 3)
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#define GPIO4 (1 << 4)
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#define GPIO5 (1 << 5)
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#define GPIO6 (1 << 6)
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#define GPIO7 (1 << 7)
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#define GPIO8 (1 << 8)
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#define GPIO9 (1 << 9)
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#define GPIO10 (1 << 10)
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#define GPIO11 (1 << 11)
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#define GPIO12 (1 << 12)
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#define GPIO13 (1 << 13)
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#define GPIO14 (1 << 14)
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#define GPIO15 (1 << 15)
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#define GPIO_ALL 0xffff
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/* --- GPIO registers ------------------------------------------------------ */
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/* Port mode register (GPIOx_MODER) */
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#define GPIO_MODER(port) MMIO32(port + 0x00)
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#define GPIOA_MODER GPIO_MODER(GPIOA)
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#define GPIOB_MODER GPIO_MODER(GPIOB)
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#define GPIOC_MODER GPIO_MODER(GPIOC)
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#define GPIOD_MODER GPIO_MODER(GPIOD)
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#define GPIOE_MODER GPIO_MODER(GPIOE)
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#define GPIOH_MODER GPIO_MODER(GPIOH)
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/* Port output type register (GPIOx_OTYPER) */
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#define GPIO_OTYPER(port) MMIO32(port + 0x04)
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#define GPIOA_OTYPER GPIO_OTYPER(GPIOA)
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#define GPIOB_OTYPER GPIO_OTYPER(GPIOB)
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#define GPIOC_OTYPER GPIO_OTYPER(GPIOC)
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#define GPIOD_OTYPER GPIO_OTYPER(GPIOD)
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#define GPIOE_OTYPER GPIO_OTYPER(GPIOE)
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#define GPIOH_OTYPER GPIO_OTYPER(GPIOH)
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/* Port output speed register (GPIOx_OSPEEDR) */
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#define GPIO_OSPEEDR(port) MMIO32(port + 0x08)
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#define GPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA)
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#define GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB)
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#define GPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC)
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#define GPIOD_OSPEEDR GPIO_OSPEEDR(GPIOD)
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#define GPIOE_OSPEEDR GPIO_OSPEEDR(GPIOE)
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#define GPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH)
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/* Port pull-up/pull-down register (GPIOx_PUPDR) */
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#define GPIO_PUPDR(port) MMIO32(port + 0x0c)
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#define GPIOA_PUPDR GPIO_PUPDR(GPIOA)
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#define GPIOB_PUPDR GPIO_PUPDR(GPIOB)
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#define GPIOC_PUPDR GPIO_PUPDR(GPIOC)
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#define GPIOD_PUPDR GPIO_PUPDR(GPIOD)
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#define GPIOE_PUPDR GPIO_PUPDR(GPIOE)
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#define GPIOH_PUPDR GPIO_PUPDR(GPIOH)
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/* Port input data register (GPIOx_IDR) */
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#define GPIO_IDR(port) MMIO32(port + 0x10)
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#define GPIOA_IDR GPIO_IDR(GPIOA)
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#define GPIOB_IDR GPIO_IDR(GPIOB)
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#define GPIOC_IDR GPIO_IDR(GPIOC)
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#define GPIOD_IDR GPIO_IDR(GPIOD)
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#define GPIOE_IDR GPIO_IDR(GPIOE)
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#define GPIOH_IDR GPIO_IDR(GPIOH)
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/* Port output data register (GPIOx_ODR) */
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#define GPIO_ODR(port) MMIO32(port + 0x14)
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#define GPIOA_ODR GPIO_ODR(GPIOA)
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#define GPIOB_ODR GPIO_ODR(GPIOB)
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#define GPIOC_ODR GPIO_ODR(GPIOC)
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#define GPIOD_ODR GPIO_ODR(GPIOD)
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#define GPIOE_ODR GPIO_ODR(GPIOE)
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#define GPIOH_ODR GPIO_ODR(GPIOH)
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/* Port bit set/reset register (GPIOx_BSRR) */
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#define GPIO_BSRR(port) MMIO32(port + 0x18)
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#define GPIOA_BSRR GPIO_BSRR(GPIOA)
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#define GPIOB_BSRR GPIO_BSRR(GPIOB)
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#define GPIOC_BSRR GPIO_BSRR(GPIOC)
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#define GPIOD_BSRR GPIO_BSRR(GPIOD)
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#define GPIOE_BSRR GPIO_BSRR(GPIOE)
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#define GPIOH_BSRR GPIO_BSRR(GPIOH)
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/* Port configuration lock register (GPIOx_LCKR) */
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#define GPIO_LCKR(port) MMIO32(port + 0x1C)
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#define GPIOA_LCKR GPIO_LCKR(GPIOA)
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#define GPIOB_LCKR GPIO_LCKR(GPIOB)
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#define GPIOC_LCKR GPIO_LCKR(GPIOC)
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#define GPIOD_LCKR GPIO_LCKR(GPIOD)
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#define GPIOE_LCKR GPIO_LCKR(GPIOE)
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#define GPIOH_LCKR GPIO_LCKR(GPIOH)
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/* Alternate function low register (GPIOx_AFRL) */
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#define GPIO_AFRL(port) MMIO32(port + 0x20)
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#define GPIOA_AFRL GPIO_AFRL(GPIOA)
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#define GPIOB_AFRL GPIO_AFRL(GPIOB)
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#define GPIOC_AFRL GPIO_AFRL(GPIOC)
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#define GPIOD_AFRL GPIO_AFRL(GPIOD)
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#define GPIOE_AFRL GPIO_AFRL(GPIOE)
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#define GPIOH_AFRL GPIO_AFRL(GPIOH)
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/* Alternate function high register (GPIOx_AFRH) */
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#define GPIO_AFRH(port) MMIO32(port + 0x24)
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#define GPIOA_AFRH GPIO_AFRH(GPIOA)
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#define GPIOB_AFRH GPIO_AFRH(GPIOB)
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#define GPIOC_AFRH GPIO_AFRH(GPIOC)
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#define GPIOD_AFRH GPIO_AFRH(GPIOD)
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#define GPIOE_AFRH GPIO_AFRH(GPIOE)
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#define GPIOH_AFRH GPIO_AFRH(GPIOH)
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/* --- GPIOx_MODER values-------------------------------------------- */
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#define GPIO_MODE(n, mode) (mode << (2 * (n)))
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#define GPIO_MODE_MASK(n) (0x3 << (2 * (n)))
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#define GPIO_MODE_INPUT 0x00 /* Default */
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#define GPIO_MODE_OUTPUT 0x01
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#define GPIO_MODE_ALTFN 0x02
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#define GPIO_MODE_ANALOG 0x03
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/* --- GPIOx_OTYPER values -------------------------------------------- */
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/* Output type (OTx values) */
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#define GPIO_OTYPE_PP 0x0
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#define GPIO_OTYPE_OD 0x1
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/* Output speed values */
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#define GPIO_OSPEED(n, speed) (speed << (2 * (n)))
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#define GPIO_OSPEED_MASK(n) (0x3 << (2 * (n)))
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#define GPIO_OSPEED_400KHZ 0x0
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#define GPIO_OSPEED_2MHZ 0x1
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#define GPIO_OSPEED_10MHZ 0x2
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#define GPIO_OSPEED_40MHZ 0x3
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/* --- GPIOx_PUPDR values ------------------------------------------- */
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#define GPIO_PUPD(n, pupd) (pupd << (2 * (n)))
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#define GPIO_PUPD_MASK(n) (0x3 << (2 * (n)))
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#define GPIO_PUPD_NONE 0x0
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#define GPIO_PUPD_PULLUP 0x1
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#define GPIO_PUPD_PULLDOWN 0x2
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/* --- GPIO_IDR values ----------------------------------------------------- */
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/* GPIO_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */
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/* --- GPIO_ODR values ----------------------------------------------------- */
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/* GPIO_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */
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/* --- GPIO_BSRR values ---------------------------------------------------- */
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/* GPIO_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */
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/* GPIO_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */
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/* --- GPIO_LCKR values ---------------------------------------------------- */
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#define GPIO_LCKK (1 << 16)
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/* GPIO_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */
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/* --- GPIOx_AFRL/H values ------------------------------------------------- */
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/* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */
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/* See datasheet table 5, page 35 for the definitions */
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#define GPIO_AFR(n, af) (af << ((n) * 4))
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#define GPIO_AFR_MASK(n) (0xf << ((n) * 4))
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#define GPIO_AF0 0x0
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#define GPIO_AF1 0x1
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#define GPIO_AF2 0x2
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#define GPIO_AF3 0x3
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#define GPIO_AF4 0x4
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#define GPIO_AF5 0x5
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#define GPIO_AF6 0x6
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#define GPIO_AF7 0x7
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#define GPIO_AF8 0x8
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#define GPIO_AF9 0x9
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#define GPIO_AF10 0xa
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#define GPIO_AF11 0xb
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#define GPIO_AF12 0xc
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#define GPIO_AF13 0xd
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#define GPIO_AF14 0xe
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#define GPIO_AF15 0xf
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/* --- Function prototypes ------------------------------------------------- */
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/*
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* L1, like F2 and F4, has the "new" GPIO peripheral, so use that style
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* TODO: this should all really be moved to a "common" gpio header
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*/
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void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios);
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void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios);
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void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios);
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/* F1 compatible api */
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void gpio_set(u32 gpioport, u16 gpios);
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void gpio_clear(u32 gpioport, u16 gpios);
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u16 gpio_get(u32 gpioport, u16 gpios);
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void gpio_toggle(u32 gpioport, u16 gpios);
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u16 gpio_port_read(u32 gpioport);
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void gpio_port_write(u32 gpioport, u16 data);
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void gpio_port_config_lock(u32 gpioport, u16 gpios);
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#endif
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453
include/libopencm3/stm32/l1/rcc.h
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453
include/libopencm3/stm32/l1/rcc.h
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@@ -0,0 +1,453 @@
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/** @file
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@ingroup STM32L1xx
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@brief <b>libopencm3 STM32L1xx Reset and Clock Control</b>
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2009 Federico Ruiz-Ugalde \<memeruiz at gmail dot com\>
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@author @htmlonly © @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
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@author @htmlonly © @endhtmlonly 2012 Karl Palsson <karlp@tweak.net.au>
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@date 18 May 2012
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LGPL License Terms @ref lgpl_license
|
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*/
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/** @defgroup STM32L1xx_rcc_defines
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@brief Defined Constants and Types for the STM32L1xx Reset and Clock Control
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@ingroup STM32L1xx_defines
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LGPL License Terms @ref lgpl_license
|
||||
|
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*/
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/*
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* This file is part of the libopencm3 project.
|
||||
*
|
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
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* Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
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* Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
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*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Originally based on the F1 code, as it seemed most similar to the L1
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||||
* TODO: very incomplete still!
|
||||
*/
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#ifndef LIBOPENCM3_RCC_H
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#define LIBOPENCM3_RCC_H
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/cm3/common.h>
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/* --- RCC registers ------------------------------------------------------- */
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#define RCC_CR MMIO32(RCC_BASE + 0x00)
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#define RCC_ICSCR MMIO32(RCC_BASE + 0x04)
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#define RCC_CFGR MMIO32(RCC_BASE + 0x08)
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#define RCC_CIR MMIO32(RCC_BASE + 0x0c)
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#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x10)
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#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x14)
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#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x18)
|
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#define RCC_AHBENR MMIO32(RCC_BASE + 0x1c)
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#define RCC_APB2ENR MMIO32(RCC_BASE + 0x20)
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#define RCC_APB1ENR MMIO32(RCC_BASE + 0x24)
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#define RCC_AHBLPENR MMIO32(RCC_BASE + 0x28)
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#define RCC_APB2LPENR MMIO32(RCC_BASE + 0x2c)
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#define RCC_APB1LPENR MMIO32(RCC_BASE + 0x30)
|
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#define RCC_CSR MMIO32(RCC_BASE + 0x34)
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|
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/* --- RCC_CR values ------------------------------------------------------- */
|
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/* RTCPRE[1:0] at 30:29 */
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#define RCC_CR_CSSON (1 << 28)
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#define RCC_CR_PLLRDY (1 << 25)
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#define RCC_CR_PLLON (1 << 24)
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#define RCC_CR_HSEBYP (1 << 18)
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#define RCC_CR_HSERDY (1 << 17)
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#define RCC_CR_HSEON (1 << 16)
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||||
#define RCC_CR_MSIRDY (1 << 9)
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#define RCC_CR_MSION (1 << 8)
|
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#define RCC_CR_HSIRDY (1 << 1)
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#define RCC_CR_HSION (1 << 0)
|
||||
|
||||
/* --- RCC_ICSCR values ---------------------------------------------------- */
|
||||
|
||||
// TODO
|
||||
|
||||
/* --- RCC_CFGR values ----------------------------------------------------- */
|
||||
|
||||
/* MCOPRE */
|
||||
#define RCC_CFGR_MCOPRE_DIV1 0
|
||||
#define RCC_CFGR_MCOPRE_DIV2 1
|
||||
#define RCC_CFGR_MCOPRE_DIV4 2
|
||||
#define RCC_CFGR_MCOPRE_DIV8 3
|
||||
#define RCC_CFGR_MCOPRE_DIV16 4
|
||||
|
||||
/* MCO: Microcontroller clock output */
|
||||
#define RCC_CFGR_MCO_NOCLK 0x0
|
||||
#define RCC_CFGR_MCO_SYSCLK 0x1
|
||||
#define RCC_CFGR_MCO_HSICLK 0x2
|
||||
#define RCC_CFGR_MCO_MSICLK 0x3
|
||||
#define RCC_CFGR_MCO_HSECLK 0x4
|
||||
#define RCC_CFGR_MCO_PLLCLK 0x5
|
||||
#define RCC_CFGR_MCO_LSICLK 0x6
|
||||
#define RCC_CFGR_MCO_LSECLK 0x7
|
||||
|
||||
/* PLL Output division selection */
|
||||
#define RCC_CFGR_PLLDIV_DIV2 0x1
|
||||
#define RCC_CFGR_PLLDIV_DIV3 0x2
|
||||
#define RCC_CFGR_PLLDIV_DIV4 0x3
|
||||
|
||||
/* PLLMUL: PLL multiplication factor */
|
||||
#define RCC_CFGR_PLLMUL_MUL3 0x0
|
||||
#define RCC_CFGR_PLLMUL_MUL4 0x1
|
||||
#define RCC_CFGR_PLLMUL_MUL6 0x2
|
||||
#define RCC_CFGR_PLLMUL_MUL8 0x3
|
||||
#define RCC_CFGR_PLLMUL_MUL12 0x4
|
||||
#define RCC_CFGR_PLLMUL_MUL16 0x5
|
||||
#define RCC_CFGR_PLLMUL_MUL24 0x6
|
||||
#define RCC_CFGR_PLLMUL_MUL32 0x7
|
||||
#define RCC_CFGR_PLLMUL_MUL48 0x8
|
||||
|
||||
/* PLLSRC: PLL entry clock source */
|
||||
#define RCC_CFGR_PLLSRC_HSI_CLK 0x0
|
||||
#define RCC_CFGR_PLLSRC_HSE_CLK 0x1
|
||||
|
||||
/* PPRE2: APB high-speed prescaler (APB2) */
|
||||
#define RCC_CFGR_PPRE2_HCLK_NODIV 0x0
|
||||
#define RCC_CFGR_PPRE2_HCLK_DIV2 0x4
|
||||
#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5
|
||||
#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6
|
||||
#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7
|
||||
|
||||
/* PPRE1: APB low-speed prescaler (APB1) */
|
||||
#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0
|
||||
#define RCC_CFGR_PPRE1_HCLK_DIV2 0x4
|
||||
#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5
|
||||
#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6
|
||||
#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7
|
||||
|
||||
/* HPRE: AHB prescaler */
|
||||
#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0
|
||||
#define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8
|
||||
#define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9
|
||||
#define RCC_CFGR_HPRE_SYSCLK_DIV8 0xa
|
||||
#define RCC_CFGR_HPRE_SYSCLK_DIV16 0xb
|
||||
#define RCC_CFGR_HPRE_SYSCLK_DIV64 0xc
|
||||
#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd
|
||||
#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe
|
||||
#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf
|
||||
|
||||
/* SWS: System clock switch status */
|
||||
#define RCC_CFGR_SWS_SYSCLKSEL_MSICLK 0x0
|
||||
#define RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x1
|
||||
#define RCC_CFGR_SWS_SYSCLKSEL_HSECLK 0x2
|
||||
#define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x3
|
||||
|
||||
/* SW: System clock switch */
|
||||
#define RCC_CFGR_SW_SYSCLKSEL_MSICLK 0x0
|
||||
#define RCC_CFGR_SW_SYSCLKSEL_HSICLK 0x1
|
||||
#define RCC_CFGR_SW_SYSCLKSEL_HSECLK 0x2
|
||||
#define RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x3
|
||||
|
||||
/* --- RCC_CIR values ------------------------------------------------------ */
|
||||
|
||||
/* Clock security system interrupt clear bit */
|
||||
#define RCC_CIR_CSSC (1 << 23)
|
||||
|
||||
/* OSC ready interrupt clear bits */
|
||||
#define RCC_CIR_MSIRDYC (1 << 21)
|
||||
#define RCC_CIR_PLLRDYC (1 << 20)
|
||||
#define RCC_CIR_HSERDYC (1 << 19)
|
||||
#define RCC_CIR_HSIRDYC (1 << 18)
|
||||
#define RCC_CIR_LSERDYC (1 << 17)
|
||||
#define RCC_CIR_LSIRDYC (1 << 16)
|
||||
|
||||
/* OSC ready interrupt enable bits */
|
||||
#define RCC_CIR_MSIRDYIE (1 << 13)
|
||||
#define RCC_CIR_PLLRDYIE (1 << 12)
|
||||
#define RCC_CIR_HSERDYIE (1 << 11)
|
||||
#define RCC_CIR_HSIRDYIE (1 << 10)
|
||||
#define RCC_CIR_LSERDYIE (1 << 9)
|
||||
#define RCC_CIR_LSIRDYIE (1 << 8)
|
||||
|
||||
/* Clock security system interrupt flag bit */
|
||||
#define RCC_CIR_CSSF (1 << 7)
|
||||
|
||||
/* OSC ready interrupt flag bits */
|
||||
#define RCC_CIR_MSIRDYF (1 << 5) /* (**) */
|
||||
#define RCC_CIR_PLLRDYF (1 << 4)
|
||||
#define RCC_CIR_HSERDYF (1 << 3)
|
||||
#define RCC_CIR_HSIRDYF (1 << 2)
|
||||
#define RCC_CIR_LSERDYF (1 << 1)
|
||||
#define RCC_CIR_LSIRDYF (1 << 0)
|
||||
|
||||
/* --- RCC_AHBRSTR values ------------------------------------------------- */
|
||||
#define RCC_AHBRSTR_DMA1RST (1 << 24)
|
||||
#define RCC_AHBRSTR_FLITFRST (1 << 15)
|
||||
#define RCC_AHBRSTR_CRCRST (1 << 12)
|
||||
#define RCC_AHBRSTR_GPIOHRST (1 << 5)
|
||||
#define RCC_AHBRSTR_GPIOERST (1 << 4)
|
||||
#define RCC_AHBRSTR_GPIODRST (1 << 3)
|
||||
#define RCC_AHBRSTR_GPIOCRST (1 << 2)
|
||||
#define RCC_AHBRSTR_GPIOBRST (1 << 1)
|
||||
#define RCC_AHBRSTR_GPIOARST (1 << 0)
|
||||
|
||||
/* --- RCC_APB2RSTR values ------------------------------------------------- */
|
||||
|
||||
#define RCC_APB2RSTR_USART1RST (1 << 14)
|
||||
#define RCC_APB2RSTR_SPI1RST (1 << 12)
|
||||
#define RCC_APB2RSTR_ADC1RST (1 << 9)
|
||||
#define RCC_APB2RSTR_TIM11RST (1 << 4)
|
||||
#define RCC_APB2RSTR_TIM10RST (1 << 3)
|
||||
#define RCC_APB2RSTR_TIM9RST (1 << 2)
|
||||
#define RCC_APB2RSTR_SYSCFGRST (1 << 0)
|
||||
|
||||
/* --- RCC_APB1RSTR values ------------------------------------------------- */
|
||||
|
||||
TODO : up to here
|
||||
|
||||
#define RCC_APB1RSTR_DACRST (1 << 29)
|
||||
#define RCC_APB1RSTR_PWRRST (1 << 28)
|
||||
#define RCC_APB1RSTR_BKPRST (1 << 27)
|
||||
#define RCC_APB1RSTR_CAN2RST (1 << 26) /* (**) */
|
||||
#define RCC_APB1RSTR_CAN1RST (1 << 25) /* (**) */
|
||||
#define RCC_APB1RSTR_CANRST (1 << 25) /* (XX) Alias for CAN1RST */
|
||||
#define RCC_APB1RSTR_USBRST (1 << 23) /* (XX) */
|
||||
#define RCC_APB1RSTR_I2C2RST (1 << 22)
|
||||
#define RCC_APB1RSTR_I2C1RST (1 << 21)
|
||||
#define RCC_APB1RSTR_UART5RST (1 << 20)
|
||||
#define RCC_APB1RSTR_UART4RST (1 << 19)
|
||||
#define RCC_APB1RSTR_USART3RST (1 << 18)
|
||||
#define RCC_APB1RSTR_USART2RST (1 << 17)
|
||||
#define RCC_APB1RSTR_SPI3RST (1 << 15)
|
||||
#define RCC_APB1RSTR_SPI2RST (1 << 14)
|
||||
#define RCC_APB1RSTR_WWDGRST (1 << 11)
|
||||
#define RCC_APB1RSTR_TIM7RST (1 << 5)
|
||||
#define RCC_APB1RSTR_TIM6RST (1 << 4)
|
||||
#define RCC_APB1RSTR_TIM5RST (1 << 3)
|
||||
#define RCC_APB1RSTR_TIM4RST (1 << 2)
|
||||
#define RCC_APB1RSTR_TIM3RST (1 << 1)
|
||||
#define RCC_APB1RSTR_TIM2RST (1 << 0)
|
||||
|
||||
/* --- RCC_AHBENR values --------------------------------------------------- */
|
||||
|
||||
/** @defgroup rcc_ahbenr_en RCC_AHBENR enable values
|
||||
@ingroup STM32L1xx_rcc_defines
|
||||
|
||||
@{*/
|
||||
#define RCC_AHBENR_ETHMACENRX (1 << 16)
|
||||
#define RCC_AHBENR_ETHMACENTX (1 << 15)
|
||||
#define RCC_AHBENR_ETHMACEN (1 << 14)
|
||||
#define RCC_AHBENR_OTGFSEN (1 << 12)
|
||||
#define RCC_AHBENR_SDIOEN (1 << 10)
|
||||
#define RCC_AHBENR_FSMCEN (1 << 8)
|
||||
#define RCC_AHBENR_CRCEN (1 << 6)
|
||||
#define RCC_AHBENR_FLITFEN (1 << 4)
|
||||
#define RCC_AHBENR_SRAMEN (1 << 2)
|
||||
#define RCC_AHBENR_DMA2EN (1 << 1)
|
||||
#define RCC_AHBENR_DMA1EN (1 << 0)
|
||||
/*@}*/
|
||||
|
||||
/* --- RCC_APB2ENR values -------------------------------------------------- */
|
||||
|
||||
/** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values
|
||||
@ingroup STM32L1xx_rcc_defines
|
||||
|
||||
@{*/
|
||||
#define RCC_APB2ENR_ADC3EN (1 << 15) /* (XX) */
|
||||
#define RCC_APB2ENR_USART1EN (1 << 14)
|
||||
#define RCC_APB2ENR_TIM8EN (1 << 13) /* (XX) */
|
||||
#define RCC_APB2ENR_SPI1EN (1 << 12)
|
||||
#define RCC_APB2ENR_TIM1EN (1 << 11)
|
||||
#define RCC_APB2ENR_ADC2EN (1 << 10)
|
||||
#define RCC_APB2ENR_ADC1EN (1 << 9)
|
||||
#define RCC_APB2ENR_IOPGEN (1 << 8) /* (XX) */
|
||||
#define RCC_APB2ENR_IOPFEN (1 << 7) /* (XX) */
|
||||
#define RCC_APB2ENR_IOPEEN (1 << 6)
|
||||
#define RCC_APB2ENR_IOPDEN (1 << 5)
|
||||
#define RCC_APB2ENR_IOPCEN (1 << 4)
|
||||
#define RCC_APB2ENR_IOPBEN (1 << 3)
|
||||
#define RCC_APB2ENR_IOPAEN (1 << 2)
|
||||
#define RCC_APB2ENR_AFIOEN (1 << 0)
|
||||
/*@}*/
|
||||
|
||||
/* --- RCC_APB1ENR values -------------------------------------------------- */
|
||||
|
||||
/** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values
|
||||
@ingroup STM32L1xx_rcc_defines
|
||||
|
||||
@{*/
|
||||
#define RCC_APB1ENR_DACEN (1 << 29)
|
||||
#define RCC_APB1ENR_PWREN (1 << 28)
|
||||
#define RCC_APB1ENR_BKPEN (1 << 27)
|
||||
#define RCC_APB1ENR_CAN2EN (1 << 26) /* (**) */
|
||||
#define RCC_APB1ENR_CAN1EN (1 << 25) /* (**) */
|
||||
#define RCC_APB1ENR_CANEN (1 << 25) /* (XX) Alias for CAN1EN */
|
||||
#define RCC_APB1ENR_USBEN (1 << 23) /* (XX) */
|
||||
#define RCC_APB1ENR_I2C2EN (1 << 22)
|
||||
#define RCC_APB1ENR_I2C1EN (1 << 21)
|
||||
#define RCC_APB1ENR_UART5EN (1 << 20)
|
||||
#define RCC_APB1ENR_UART4EN (1 << 19)
|
||||
#define RCC_APB1ENR_USART3EN (1 << 18)
|
||||
#define RCC_APB1ENR_USART2EN (1 << 17)
|
||||
#define RCC_APB1ENR_SPI3EN (1 << 15)
|
||||
#define RCC_APB1ENR_SPI2EN (1 << 14)
|
||||
#define RCC_APB1ENR_WWDGEN (1 << 11)
|
||||
#define RCC_APB1ENR_TIM7EN (1 << 5)
|
||||
#define RCC_APB1ENR_TIM6EN (1 << 4)
|
||||
#define RCC_APB1ENR_TIM5EN (1 << 3)
|
||||
#define RCC_APB1ENR_TIM4EN (1 << 2)
|
||||
#define RCC_APB1ENR_TIM3EN (1 << 1)
|
||||
#define RCC_APB1ENR_TIM2EN (1 << 0)
|
||||
/*@}*/
|
||||
|
||||
/* --- RCC_BDCR values ----------------------------------------------------- */
|
||||
|
||||
#define RCC_BDCR_BDRST (1 << 16)
|
||||
#define RCC_BDCR_RTCEN (1 << 15)
|
||||
/* RCC_BDCR[9:8]: RTCSEL */
|
||||
#define RCC_BDCR_LSEBYP (1 << 2)
|
||||
#define RCC_BDCR_LSERDY (1 << 1)
|
||||
#define RCC_BDCR_LSEON (1 << 0)
|
||||
|
||||
/* --- RCC_CSR values ------------------------------------------------------ */
|
||||
|
||||
#define RCC_CSR_LPWRRSTF (1 << 31)
|
||||
#define RCC_CSR_WWDGRSTF (1 << 30)
|
||||
#define RCC_CSR_IWDGRSTF (1 << 29)
|
||||
#define RCC_CSR_SFTRSTF (1 << 28)
|
||||
#define RCC_CSR_PORRSTF (1 << 27)
|
||||
#define RCC_CSR_PINRSTF (1 << 26)
|
||||
#define RCC_CSR_RMVF (1 << 24)
|
||||
#define RCC_CSR_LSIRDY (1 << 1)
|
||||
#define RCC_CSR_LSION (1 << 0)
|
||||
|
||||
/* --- RCC_AHBRSTR values -------------------------------------------------- */
|
||||
|
||||
#define RCC_AHBRSTR_ETHMACRST (1 << 14)
|
||||
#define RCC_AHBRSTR_OTGFSRST (1 << 12)
|
||||
|
||||
/* --- RCC_CFGR2 values ---------------------------------------------------- */
|
||||
|
||||
/* I2S3SRC: I2S3 clock source */
|
||||
#define RCC_CFGR2_I2S3SRC_SYSCLK 0x0
|
||||
#define RCC_CFGR2_I2S3SRC_PLL3_VCO_CLK 0x1
|
||||
|
||||
/* I2S2SRC: I2S2 clock source */
|
||||
#define RCC_CFGR2_I2S2SRC_SYSCLK 0x0
|
||||
#define RCC_CFGR2_I2S2SRC_PLL3_VCO_CLK 0x1
|
||||
|
||||
/* PREDIV1SRC: PREDIV1 entry clock source */
|
||||
#define RCC_CFGR2_PREDIV1SRC_HSE_CLK 0x0
|
||||
#define RCC_CFGR2_PREDIV1SRC_PLL2_CLK 0x1
|
||||
|
||||
#define RCC_CFGR2_PLL2MUL (1 << 0)
|
||||
#define RCC_CFGR2_PREDIV2 (1 << 0)
|
||||
#define RCC_CFGR2_PREDIV1 (1 << 0)
|
||||
|
||||
/* PLL3MUL: PLL3 multiplication factor */
|
||||
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL8 0x6
|
||||
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL9 0x7
|
||||
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL10 0x8
|
||||
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL11 0x9
|
||||
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL12 0xa
|
||||
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL13 0xb
|
||||
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL14 0xc
|
||||
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL16 0xe
|
||||
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL20 0xf
|
||||
|
||||
/* PLL2MUL: PLL2 multiplication factor */
|
||||
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL8 0x6
|
||||
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL9 0x7
|
||||
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL10 0x8
|
||||
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL11 0x9
|
||||
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL12 0xa
|
||||
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL13 0xb
|
||||
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL14 0xc
|
||||
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL16 0xe
|
||||
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL20 0xf
|
||||
|
||||
/* PREDIV2: PREDIV2 division factor */
|
||||
#define RCC_CFGR2_PREDIV2_NODIV 0x0
|
||||
#define RCC_CFGR2_PREDIV2_DIV2 0x1
|
||||
#define RCC_CFGR2_PREDIV2_DIV3 0x2
|
||||
#define RCC_CFGR2_PREDIV2_DIV4 0x3
|
||||
#define RCC_CFGR2_PREDIV2_DIV5 0x4
|
||||
#define RCC_CFGR2_PREDIV2_DIV6 0x5
|
||||
#define RCC_CFGR2_PREDIV2_DIV7 0x6
|
||||
#define RCC_CFGR2_PREDIV2_DIV8 0x7
|
||||
#define RCC_CFGR2_PREDIV2_DIV9 0x8
|
||||
#define RCC_CFGR2_PREDIV2_DIV10 0x9
|
||||
#define RCC_CFGR2_PREDIV2_DIV11 0xa
|
||||
#define RCC_CFGR2_PREDIV2_DIV12 0xb
|
||||
#define RCC_CFGR2_PREDIV2_DIV13 0xc
|
||||
#define RCC_CFGR2_PREDIV2_DIV14 0xd
|
||||
#define RCC_CFGR2_PREDIV2_DIV15 0xe
|
||||
#define RCC_CFGR2_PREDIV2_DIV16 0xf
|
||||
|
||||
/* --- Variable definitions ------------------------------------------------ */
|
||||
extern u32 rcc_ppre1_frequency;
|
||||
extern u32 rcc_ppre2_frequency;
|
||||
|
||||
/* --- Function prototypes ------------------------------------------------- */
|
||||
|
||||
typedef enum {
|
||||
PLL, HSE, HSI, LSE, LSI
|
||||
} osc_t;
|
||||
|
||||
void rcc_osc_ready_int_clear(osc_t osc);
|
||||
void rcc_osc_ready_int_enable(osc_t osc);
|
||||
void rcc_osc_ready_int_disable(osc_t osc);
|
||||
int rcc_osc_ready_int_flag(osc_t osc);
|
||||
void rcc_css_int_clear(void);
|
||||
int rcc_css_int_flag(void);
|
||||
void rcc_wait_for_osc_ready(osc_t osc);
|
||||
void rcc_osc_on(osc_t osc);
|
||||
void rcc_osc_off(osc_t osc);
|
||||
void rcc_css_enable(void);
|
||||
void rcc_css_disable(void);
|
||||
void rcc_osc_bypass_enable(osc_t osc);
|
||||
void rcc_osc_bypass_disable(osc_t osc);
|
||||
void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en);
|
||||
void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en);
|
||||
void rcc_peripheral_reset(volatile u32 *reg, u32 reset);
|
||||
void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset);
|
||||
void rcc_set_sysclk_source(u32 clk);
|
||||
void rcc_set_pll_multiplication_factor(u32 mul);
|
||||
void rcc_set_pll_source(u32 pllsrc);
|
||||
void rcc_set_pllxtpre(u32 pllxtpre);
|
||||
void rcc_set_adcpre(u32 adcpre);
|
||||
void rcc_set_ppre2(u32 ppre2);
|
||||
void rcc_set_ppre1(u32 ppre1);
|
||||
void rcc_set_hpre(u32 hpre);
|
||||
void rcc_set_usbpre(u32 usbpre);
|
||||
u32 rcc_get_system_clock_source(int i);
|
||||
void rcc_clock_setup_in_hsi_out_64mhz(void);
|
||||
void rcc_clock_setup_in_hsi_out_48mhz(void);
|
||||
|
||||
/**
|
||||
* Maximum speed possible for F100 (Value Line) on HSI
|
||||
*/
|
||||
void rcc_clock_setup_in_hsi_out_24mhz(void);
|
||||
void rcc_clock_setup_in_hse_8mhz_out_24mhz(void);
|
||||
void rcc_clock_setup_in_hse_8mhz_out_72mhz(void);
|
||||
void rcc_clock_setup_in_hse_12mhz_out_72mhz(void);
|
||||
void rcc_clock_setup_in_hse_16mhz_out_72mhz(void);
|
||||
void rcc_backupdomain_reset(void);
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user