First coarse run to fix coding style in locm3.
Added --terse and --mailback options to the make stylecheck target. It also does continue even if it enounters a possible error. We decided on two exceptions from the linux kernel coding standard: - Empty wait while loops may end with ; on the same line. - All blocks after while, if, for have to be in brackets even if they only contain one statement. Otherwise it is easy to introduce an error. Checkpatch needs to be adapted to reflect those changes.
This commit is contained in:
Piotr Esden-Tempski
@@ -28,506 +28,513 @@
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u32 rcc_ppre1_frequency = 16000000;
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u32 rcc_ppre2_frequency = 16000000;
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const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] =
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{
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{ /* 48MHz */
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.pllm = 8,
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.plln = 96,
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.pllp = 2,
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.pllq = 2,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.power_save = 1,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS,
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.apb1_frequency = 12000000,
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.apb2_frequency = 24000000,
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},
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{ /* 120MHz */
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.pllm = 8,
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.plln = 240,
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.pllp = 2,
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.pllq = 5,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.power_save = 1,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS,
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.apb1_frequency = 30000000,
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.apb2_frequency = 60000000,
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},
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{ /* 168MHz */
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.pllm = 8,
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.plln = 336,
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.pllp = 2,
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.pllq = 7,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_5WS,
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.apb1_frequency = 42000000,
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.apb2_frequency = 84000000,
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},
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const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] = {
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{ /* 48MHz */
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.pllm = 8,
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.plln = 96,
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.pllp = 2,
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.pllq = 2,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.power_save = 1,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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FLASH_ACR_LATENCY_3WS,
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.apb1_frequency = 12000000,
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.apb2_frequency = 24000000,
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},
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{ /* 120MHz */
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.pllm = 8,
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.plln = 240,
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.pllp = 2,
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.pllq = 5,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.power_save = 1,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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FLASH_ACR_LATENCY_3WS,
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.apb1_frequency = 30000000,
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.apb2_frequency = 60000000,
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},
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{ /* 168MHz */
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.pllm = 8,
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.plln = 336,
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.pllp = 2,
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.pllq = 7,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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FLASH_ACR_LATENCY_5WS,
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.apb1_frequency = 42000000,
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.apb2_frequency = 84000000,
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},
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};
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const clock_scale_t hse_12mhz_3v3[CLOCK_3V3_END] =
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{
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{ /* 48MHz */
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.pllm = 12,
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.plln = 96,
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.pllp = 2,
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.pllq = 2,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.power_save = 1,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS,
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.apb1_frequency = 12000000,
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.apb2_frequency = 24000000,
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},
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{ /* 120MHz */
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.pllm = 12,
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.plln = 240,
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.pllp = 2,
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.pllq = 5,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.power_save = 1,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS,
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.apb1_frequency = 30000000,
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.apb2_frequency = 60000000,
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},
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{ /* 168MHz */
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.pllm = 12,
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.plln = 336,
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.pllp = 2,
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.pllq = 7,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_5WS,
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.apb1_frequency = 42000000,
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.apb2_frequency = 84000000,
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},
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const clock_scale_t hse_12mhz_3v3[CLOCK_3V3_END] = {
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{ /* 48MHz */
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.pllm = 12,
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.plln = 96,
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.pllp = 2,
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.pllq = 2,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.power_save = 1,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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FLASH_ACR_LATENCY_3WS,
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.apb1_frequency = 12000000,
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.apb2_frequency = 24000000,
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},
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{ /* 120MHz */
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.pllm = 12,
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.plln = 240,
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.pllp = 2,
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.pllq = 5,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.power_save = 1,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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FLASH_ACR_LATENCY_3WS,
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.apb1_frequency = 30000000,
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.apb2_frequency = 60000000,
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},
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{ /* 168MHz */
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.pllm = 12,
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.plln = 336,
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.pllp = 2,
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.pllq = 7,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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FLASH_ACR_LATENCY_5WS,
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.apb1_frequency = 42000000,
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.apb2_frequency = 84000000,
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},
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};
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const clock_scale_t hse_16mhz_3v3[CLOCK_3V3_END] =
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{
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{ /* 48MHz */
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.pllm = 16,
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.plln = 96,
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.pllp = 2,
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.pllq = 2,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.power_save = 1,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS,
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.apb1_frequency = 12000000,
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.apb2_frequency = 24000000,
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},
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{ /* 120MHz */
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.pllm = 16,
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.plln = 240,
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.pllp = 2,
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.pllq = 5,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.power_save = 1,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS,
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.apb1_frequency = 30000000,
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.apb2_frequency = 60000000,
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},
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{ /* 168MHz */
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.pllm = 16,
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.plln = 336,
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.pllp = 2,
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.pllq = 7,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_5WS,
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.apb1_frequency = 42000000,
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.apb2_frequency = 84000000,
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},
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const clock_scale_t hse_16mhz_3v3[CLOCK_3V3_END] = {
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{ /* 48MHz */
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.pllm = 16,
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.plln = 96,
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.pllp = 2,
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.pllq = 2,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.power_save = 1,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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FLASH_ACR_LATENCY_3WS,
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.apb1_frequency = 12000000,
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.apb2_frequency = 24000000,
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},
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{ /* 120MHz */
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.pllm = 16,
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.plln = 240,
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.pllp = 2,
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.pllq = 5,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.power_save = 1,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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FLASH_ACR_LATENCY_3WS,
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.apb1_frequency = 30000000,
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.apb2_frequency = 60000000,
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},
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{ /* 168MHz */
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.pllm = 16,
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.plln = 336,
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.pllp = 2,
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.pllq = 7,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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FLASH_ACR_LATENCY_5WS,
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.apb1_frequency = 42000000,
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.apb2_frequency = 84000000,
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},
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};
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void rcc_osc_ready_int_clear(osc_t osc)
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{
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switch (osc) {
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case PLL:
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RCC_CIR |= RCC_CIR_PLLRDYC;
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break;
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case HSE:
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RCC_CIR |= RCC_CIR_HSERDYC;
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break;
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case HSI:
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RCC_CIR |= RCC_CIR_HSIRDYC;
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break;
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case LSE:
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RCC_CIR |= RCC_CIR_LSERDYC;
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break;
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case LSI:
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RCC_CIR |= RCC_CIR_LSIRDYC;
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break;
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}
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switch (osc) {
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case PLL:
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RCC_CIR |= RCC_CIR_PLLRDYC;
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break;
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case HSE:
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RCC_CIR |= RCC_CIR_HSERDYC;
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break;
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case HSI:
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RCC_CIR |= RCC_CIR_HSIRDYC;
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break;
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case LSE:
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RCC_CIR |= RCC_CIR_LSERDYC;
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break;
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case LSI:
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RCC_CIR |= RCC_CIR_LSIRDYC;
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break;
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}
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}
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void rcc_osc_ready_int_enable(osc_t osc)
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{
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switch (osc) {
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case PLL:
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RCC_CIR |= RCC_CIR_PLLRDYIE;
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break;
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case HSE:
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RCC_CIR |= RCC_CIR_HSERDYIE;
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break;
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case HSI:
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RCC_CIR |= RCC_CIR_HSIRDYIE;
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break;
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case LSE:
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RCC_CIR |= RCC_CIR_LSERDYIE;
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break;
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case LSI:
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RCC_CIR |= RCC_CIR_LSIRDYIE;
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break;
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}
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switch (osc) {
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case PLL:
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RCC_CIR |= RCC_CIR_PLLRDYIE;
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break;
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case HSE:
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RCC_CIR |= RCC_CIR_HSERDYIE;
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break;
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case HSI:
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RCC_CIR |= RCC_CIR_HSIRDYIE;
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break;
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case LSE:
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RCC_CIR |= RCC_CIR_LSERDYIE;
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break;
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case LSI:
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RCC_CIR |= RCC_CIR_LSIRDYIE;
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break;
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}
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}
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void rcc_osc_ready_int_disable(osc_t osc)
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{
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switch (osc) {
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case PLL:
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RCC_CIR &= ~RCC_CIR_PLLRDYIE;
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break;
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case HSE:
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RCC_CIR &= ~RCC_CIR_HSERDYIE;
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break;
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case HSI:
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RCC_CIR &= ~RCC_CIR_HSIRDYIE;
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break;
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case LSE:
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RCC_CIR &= ~RCC_CIR_LSERDYIE;
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break;
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case LSI:
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RCC_CIR &= ~RCC_CIR_LSIRDYIE;
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break;
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}
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switch (osc) {
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case PLL:
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RCC_CIR &= ~RCC_CIR_PLLRDYIE;
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break;
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case HSE:
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RCC_CIR &= ~RCC_CIR_HSERDYIE;
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break;
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case HSI:
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RCC_CIR &= ~RCC_CIR_HSIRDYIE;
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break;
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case LSE:
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RCC_CIR &= ~RCC_CIR_LSERDYIE;
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break;
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case LSI:
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RCC_CIR &= ~RCC_CIR_LSIRDYIE;
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break;
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}
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}
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int rcc_osc_ready_int_flag(osc_t osc)
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{
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switch (osc) {
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case PLL:
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return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0);
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break;
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case HSE:
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return ((RCC_CIR & RCC_CIR_HSERDYF) != 0);
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break;
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case HSI:
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return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0);
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break;
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case LSE:
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return ((RCC_CIR & RCC_CIR_LSERDYF) != 0);
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break;
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case LSI:
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return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0);
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break;
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}
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switch (osc) {
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case PLL:
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return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0);
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break;
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case HSE:
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return ((RCC_CIR & RCC_CIR_HSERDYF) != 0);
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break;
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case HSI:
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return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0);
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break;
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case LSE:
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return ((RCC_CIR & RCC_CIR_LSERDYF) != 0);
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break;
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case LSI:
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return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0);
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break;
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}
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cm3_assert_not_reached();
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cm3_assert_not_reached();
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}
|
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void rcc_css_int_clear(void)
|
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{
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RCC_CIR |= RCC_CIR_CSSC;
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RCC_CIR |= RCC_CIR_CSSC;
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}
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int rcc_css_int_flag(void)
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{
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return ((RCC_CIR & RCC_CIR_CSSF) != 0);
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return ((RCC_CIR & RCC_CIR_CSSF) != 0);
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}
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void rcc_wait_for_osc_ready(osc_t osc)
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{
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switch (osc) {
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case PLL:
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while ((RCC_CR & RCC_CR_PLLRDY) == 0);
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break;
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case HSE:
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while ((RCC_CR & RCC_CR_HSERDY) == 0);
|
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break;
|
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case HSI:
|
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while ((RCC_CR & RCC_CR_HSIRDY) == 0);
|
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break;
|
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case LSE:
|
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while ((RCC_BDCR & RCC_BDCR_LSERDY) == 0);
|
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break;
|
||||
case LSI:
|
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while ((RCC_CSR & RCC_CSR_LSIRDY) == 0);
|
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break;
|
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}
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switch (osc) {
|
||||
case PLL:
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while ((RCC_CR & RCC_CR_PLLRDY) == 0);
|
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break;
|
||||
case HSE:
|
||||
while ((RCC_CR & RCC_CR_HSERDY) == 0);
|
||||
break;
|
||||
case HSI:
|
||||
while ((RCC_CR & RCC_CR_HSIRDY) == 0);
|
||||
break;
|
||||
case LSE:
|
||||
while ((RCC_BDCR & RCC_BDCR_LSERDY) == 0);
|
||||
break;
|
||||
case LSI:
|
||||
while ((RCC_CSR & RCC_CSR_LSIRDY) == 0);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void rcc_wait_for_sysclk_status(osc_t osc)
|
||||
{
|
||||
switch (osc) {
|
||||
case PLL:
|
||||
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_PLL);
|
||||
break;
|
||||
case HSE:
|
||||
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSE);
|
||||
break;
|
||||
case HSI:
|
||||
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSI);
|
||||
break;
|
||||
default:
|
||||
/* Shouldn't be reached. */
|
||||
break;
|
||||
}
|
||||
switch (osc) {
|
||||
case PLL:
|
||||
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_PLL);
|
||||
break;
|
||||
case HSE:
|
||||
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSE);
|
||||
break;
|
||||
case HSI:
|
||||
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSI);
|
||||
break;
|
||||
default:
|
||||
/* Shouldn't be reached. */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void rcc_osc_on(osc_t osc)
|
||||
{
|
||||
switch (osc) {
|
||||
case PLL:
|
||||
RCC_CR |= RCC_CR_PLLON;
|
||||
break;
|
||||
case HSE:
|
||||
RCC_CR |= RCC_CR_HSEON;
|
||||
break;
|
||||
case HSI:
|
||||
RCC_CR |= RCC_CR_HSION;
|
||||
break;
|
||||
case LSE:
|
||||
RCC_BDCR |= RCC_BDCR_LSEON;
|
||||
break;
|
||||
case LSI:
|
||||
RCC_CSR |= RCC_CSR_LSION;
|
||||
break;
|
||||
}
|
||||
switch (osc) {
|
||||
case PLL:
|
||||
RCC_CR |= RCC_CR_PLLON;
|
||||
break;
|
||||
case HSE:
|
||||
RCC_CR |= RCC_CR_HSEON;
|
||||
break;
|
||||
case HSI:
|
||||
RCC_CR |= RCC_CR_HSION;
|
||||
break;
|
||||
case LSE:
|
||||
RCC_BDCR |= RCC_BDCR_LSEON;
|
||||
break;
|
||||
case LSI:
|
||||
RCC_CSR |= RCC_CSR_LSION;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void rcc_osc_off(osc_t osc)
|
||||
{
|
||||
switch (osc) {
|
||||
case PLL:
|
||||
RCC_CR &= ~RCC_CR_PLLON;
|
||||
break;
|
||||
case HSE:
|
||||
RCC_CR &= ~RCC_CR_HSEON;
|
||||
break;
|
||||
case HSI:
|
||||
RCC_CR &= ~RCC_CR_HSION;
|
||||
break;
|
||||
case LSE:
|
||||
RCC_BDCR &= ~RCC_BDCR_LSEON;
|
||||
break;
|
||||
case LSI:
|
||||
RCC_CSR &= ~RCC_CSR_LSION;
|
||||
break;
|
||||
}
|
||||
switch (osc) {
|
||||
case PLL:
|
||||
RCC_CR &= ~RCC_CR_PLLON;
|
||||
break;
|
||||
case HSE:
|
||||
RCC_CR &= ~RCC_CR_HSEON;
|
||||
break;
|
||||
case HSI:
|
||||
RCC_CR &= ~RCC_CR_HSION;
|
||||
break;
|
||||
case LSE:
|
||||
RCC_BDCR &= ~RCC_BDCR_LSEON;
|
||||
break;
|
||||
case LSI:
|
||||
RCC_CSR &= ~RCC_CSR_LSION;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void rcc_css_enable(void)
|
||||
{
|
||||
RCC_CR |= RCC_CR_CSSON;
|
||||
RCC_CR |= RCC_CR_CSSON;
|
||||
}
|
||||
|
||||
void rcc_css_disable(void)
|
||||
{
|
||||
RCC_CR &= ~RCC_CR_CSSON;
|
||||
RCC_CR &= ~RCC_CR_CSSON;
|
||||
}
|
||||
|
||||
void rcc_osc_bypass_enable(osc_t osc)
|
||||
{
|
||||
switch (osc) {
|
||||
case HSE:
|
||||
RCC_CR |= RCC_CR_HSEBYP;
|
||||
break;
|
||||
case LSE:
|
||||
RCC_BDCR |= RCC_BDCR_LSEBYP;
|
||||
break;
|
||||
case PLL:
|
||||
case HSI:
|
||||
case LSI:
|
||||
/* Do nothing, only HSE/LSE allowed here. */
|
||||
break;
|
||||
}
|
||||
switch (osc) {
|
||||
case HSE:
|
||||
RCC_CR |= RCC_CR_HSEBYP;
|
||||
break;
|
||||
case LSE:
|
||||
RCC_BDCR |= RCC_BDCR_LSEBYP;
|
||||
break;
|
||||
case PLL:
|
||||
case HSI:
|
||||
case LSI:
|
||||
/* Do nothing, only HSE/LSE allowed here. */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void rcc_osc_bypass_disable(osc_t osc)
|
||||
{
|
||||
switch (osc) {
|
||||
case HSE:
|
||||
RCC_CR &= ~RCC_CR_HSEBYP;
|
||||
break;
|
||||
case LSE:
|
||||
RCC_BDCR &= ~RCC_BDCR_LSEBYP;
|
||||
break;
|
||||
case PLL:
|
||||
case HSI:
|
||||
case LSI:
|
||||
/* Do nothing, only HSE/LSE allowed here. */
|
||||
break;
|
||||
}
|
||||
switch (osc) {
|
||||
case HSE:
|
||||
RCC_CR &= ~RCC_CR_HSEBYP;
|
||||
break;
|
||||
case LSE:
|
||||
RCC_BDCR &= ~RCC_BDCR_LSEBYP;
|
||||
break;
|
||||
case PLL:
|
||||
case HSI:
|
||||
case LSI:
|
||||
/* Do nothing, only HSE/LSE allowed here. */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en)
|
||||
{
|
||||
*reg |= en;
|
||||
*reg |= en;
|
||||
}
|
||||
|
||||
void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en)
|
||||
{
|
||||
*reg &= ~en;
|
||||
*reg &= ~en;
|
||||
}
|
||||
|
||||
void rcc_peripheral_reset(volatile u32 *reg, u32 reset)
|
||||
{
|
||||
*reg |= reset;
|
||||
*reg |= reset;
|
||||
}
|
||||
|
||||
void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset)
|
||||
{
|
||||
*reg &= ~clear_reset;
|
||||
*reg &= ~clear_reset;
|
||||
}
|
||||
|
||||
void rcc_set_sysclk_source(u32 clk)
|
||||
{
|
||||
u32 reg32;
|
||||
u32 reg32;
|
||||
|
||||
reg32 = RCC_CFGR;
|
||||
reg32 &= ~((1 << 1) | (1 << 0));
|
||||
RCC_CFGR = (reg32 | clk);
|
||||
reg32 = RCC_CFGR;
|
||||
reg32 &= ~((1 << 1) | (1 << 0));
|
||||
RCC_CFGR = (reg32 | clk);
|
||||
}
|
||||
|
||||
void rcc_set_pll_source(u32 pllsrc)
|
||||
{
|
||||
u32 reg32;
|
||||
u32 reg32;
|
||||
|
||||
reg32 = RCC_PLLCFGR;
|
||||
reg32 &= ~(1 << 22);
|
||||
RCC_PLLCFGR = (reg32 | (pllsrc << 22));
|
||||
reg32 = RCC_PLLCFGR;
|
||||
reg32 &= ~(1 << 22);
|
||||
RCC_PLLCFGR = (reg32 | (pllsrc << 22));
|
||||
}
|
||||
|
||||
void rcc_set_ppre2(u32 ppre2)
|
||||
{
|
||||
u32 reg32;
|
||||
u32 reg32;
|
||||
|
||||
reg32 = RCC_CFGR;
|
||||
reg32 &= ~((1 << 13) | (1 << 14) | (1 << 15));
|
||||
RCC_CFGR = (reg32 | (ppre2 << 13));
|
||||
reg32 = RCC_CFGR;
|
||||
reg32 &= ~((1 << 13) | (1 << 14) | (1 << 15));
|
||||
RCC_CFGR = (reg32 | (ppre2 << 13));
|
||||
}
|
||||
|
||||
void rcc_set_ppre1(u32 ppre1)
|
||||
{
|
||||
u32 reg32;
|
||||
u32 reg32;
|
||||
|
||||
reg32 = RCC_CFGR;
|
||||
reg32 &= ~((1 << 10) | (1 << 11) | (1 << 12));
|
||||
RCC_CFGR = (reg32 | (ppre1 << 10));
|
||||
reg32 = RCC_CFGR;
|
||||
reg32 &= ~((1 << 10) | (1 << 11) | (1 << 12));
|
||||
RCC_CFGR = (reg32 | (ppre1 << 10));
|
||||
}
|
||||
|
||||
void rcc_set_hpre(u32 hpre)
|
||||
{
|
||||
u32 reg32;
|
||||
u32 reg32;
|
||||
|
||||
reg32 = RCC_CFGR;
|
||||
reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7));
|
||||
RCC_CFGR = (reg32 | (hpre << 4));
|
||||
reg32 = RCC_CFGR;
|
||||
reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7));
|
||||
RCC_CFGR = (reg32 | (hpre << 4));
|
||||
}
|
||||
|
||||
void rcc_set_rtcpre(u32 rtcpre)
|
||||
{
|
||||
u32 reg32;
|
||||
u32 reg32;
|
||||
|
||||
reg32 = RCC_CFGR;
|
||||
reg32 &= ~((1 << 16) | (1 << 17) | (1 << 18) | (1 << 19) | (1 << 20));
|
||||
RCC_CFGR = (reg32 | (rtcpre << 16));
|
||||
reg32 = RCC_CFGR;
|
||||
reg32 &= ~((1 << 16) | (1 << 17) | (1 << 18) | (1 << 19) | (1 << 20));
|
||||
RCC_CFGR = (reg32 | (rtcpre << 16));
|
||||
}
|
||||
|
||||
void rcc_set_main_pll_hsi(u32 pllm, u32 plln, u32 pllp, u32 pllq)
|
||||
{
|
||||
RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
|
||||
(plln << RCC_PLLCFGR_PLLN_SHIFT) |
|
||||
(((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) |
|
||||
(pllq << RCC_PLLCFGR_PLLQ_SHIFT);
|
||||
RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
|
||||
(plln << RCC_PLLCFGR_PLLN_SHIFT) |
|
||||
(((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) |
|
||||
(pllq << RCC_PLLCFGR_PLLQ_SHIFT);
|
||||
}
|
||||
|
||||
void rcc_set_main_pll_hse(u32 pllm, u32 plln, u32 pllp, u32 pllq)
|
||||
{
|
||||
RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
|
||||
(plln << RCC_PLLCFGR_PLLN_SHIFT) |
|
||||
(((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) |
|
||||
RCC_PLLCFGR_PLLSRC |
|
||||
(pllq << RCC_PLLCFGR_PLLQ_SHIFT);
|
||||
RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
|
||||
(plln << RCC_PLLCFGR_PLLN_SHIFT) |
|
||||
(((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) |
|
||||
RCC_PLLCFGR_PLLSRC |
|
||||
(pllq << RCC_PLLCFGR_PLLQ_SHIFT);
|
||||
}
|
||||
|
||||
u32 rcc_system_clock_source(void)
|
||||
{
|
||||
/* Return the clock source which is used as system clock. */
|
||||
return ((RCC_CFGR & 0x000c) >> 2);
|
||||
/* Return the clock source which is used as system clock. */
|
||||
return (RCC_CFGR & 0x000c) >> 2;
|
||||
}
|
||||
|
||||
void rcc_clock_setup_hse_3v3(const clock_scale_t *clock)
|
||||
{
|
||||
/* Enable internal high-speed oscillator. */
|
||||
rcc_osc_on(HSI);
|
||||
rcc_wait_for_osc_ready(HSI);
|
||||
/* Enable internal high-speed oscillator. */
|
||||
rcc_osc_on(HSI);
|
||||
rcc_wait_for_osc_ready(HSI);
|
||||
|
||||
/* Select HSI as SYSCLK source. */
|
||||
rcc_set_sysclk_source(RCC_CFGR_SW_HSI);
|
||||
/* Select HSI as SYSCLK source. */
|
||||
rcc_set_sysclk_source(RCC_CFGR_SW_HSI);
|
||||
|
||||
/* Enable external high-speed oscillator 8MHz. */
|
||||
rcc_osc_on(HSE);
|
||||
rcc_wait_for_osc_ready(HSE);
|
||||
/* Enable external high-speed oscillator 8MHz. */
|
||||
rcc_osc_on(HSE);
|
||||
rcc_wait_for_osc_ready(HSE);
|
||||
|
||||
/* Enable/disable high performance mode */
|
||||
if (!clock->power_save)
|
||||
pwr_set_vos_scale(SCALE1);
|
||||
else
|
||||
pwr_set_vos_scale(SCALE2);
|
||||
/* Enable/disable high performance mode */
|
||||
if (!clock->power_save) {
|
||||
pwr_set_vos_scale(SCALE1);
|
||||
} else {
|
||||
pwr_set_vos_scale(SCALE2);
|
||||
}
|
||||
|
||||
/*
|
||||
* Set prescalers for AHB, ADC, ABP1, ABP2.
|
||||
* Do this before touching the PLL (TODO: why?).
|
||||
*/
|
||||
rcc_set_hpre(clock->hpre);
|
||||
rcc_set_ppre1(clock->ppre1);
|
||||
rcc_set_ppre2(clock->ppre2);
|
||||
/*
|
||||
* Set prescalers for AHB, ADC, ABP1, ABP2.
|
||||
* Do this before touching the PLL (TODO: why?).
|
||||
*/
|
||||
rcc_set_hpre(clock->hpre);
|
||||
rcc_set_ppre1(clock->ppre1);
|
||||
rcc_set_ppre2(clock->ppre2);
|
||||
|
||||
rcc_set_main_pll_hse(clock->pllm, clock->plln,
|
||||
clock->pllp, clock->pllq);
|
||||
rcc_set_main_pll_hse(clock->pllm, clock->plln,
|
||||
clock->pllp, clock->pllq);
|
||||
|
||||
/* Enable PLL oscillator and wait for it to stabilize. */
|
||||
rcc_osc_on(PLL);
|
||||
rcc_wait_for_osc_ready(PLL);
|
||||
/* Enable PLL oscillator and wait for it to stabilize. */
|
||||
rcc_osc_on(PLL);
|
||||
rcc_wait_for_osc_ready(PLL);
|
||||
|
||||
/* Configure flash settings. */
|
||||
flash_set_ws(clock->flash_config);
|
||||
/* Configure flash settings. */
|
||||
flash_set_ws(clock->flash_config);
|
||||
|
||||
/* Select PLL as SYSCLK source. */
|
||||
rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
|
||||
/* Select PLL as SYSCLK source. */
|
||||
rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
|
||||
|
||||
/* Wait for PLL clock to be selected. */
|
||||
rcc_wait_for_sysclk_status(PLL);
|
||||
/* Wait for PLL clock to be selected. */
|
||||
rcc_wait_for_sysclk_status(PLL);
|
||||
|
||||
/* Set the peripheral clock frequencies used. */
|
||||
rcc_ppre1_frequency = clock->apb1_frequency;
|
||||
rcc_ppre2_frequency = clock->apb2_frequency;
|
||||
/* Set the peripheral clock frequencies used. */
|
||||
rcc_ppre1_frequency = clock->apb1_frequency;
|
||||
rcc_ppre2_frequency = clock->apb2_frequency;
|
||||
|
||||
/* Disable internal high-speed oscillator. */
|
||||
rcc_osc_off(HSI);
|
||||
/* Disable internal high-speed oscillator. */
|
||||
rcc_osc_off(HSI);
|
||||
}
|
||||
|
||||
void rcc_backupdomain_reset(void)
|
||||
{
|
||||
/* Set the backup domain software reset. */
|
||||
RCC_BDCR |= RCC_BDCR_BDRST;
|
||||
/* Set the backup domain software reset. */
|
||||
RCC_BDCR |= RCC_BDCR_BDRST;
|
||||
|
||||
/* Clear the backup domain software reset. */
|
||||
RCC_BDCR &= ~RCC_BDCR_BDRST;
|
||||
/* Clear the backup domain software reset. */
|
||||
RCC_BDCR &= ~RCC_BDCR_BDRST;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user