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First coarse run to fix coding style in locm3.

Browse Source 
Added --terse and --mailback options to the make stylecheck target. It
also does continue even if it enounters a possible error.

We decided on two exceptions from the linux kernel coding standard:
- Empty wait while loops may end with ; on the same line.
- All blocks after while, if, for have to be in brackets even if they
  only contain one statement. Otherwise it is easy to introduce an
  error.

Checkpatch needs to be adapted to reflect those changes.
This commit is contained in:
Piotr Esden-Tempski
2013-06-12 17:44:07 -07:00
parent 48e0f3326b
commit 7df63fcae0
147 changed files with 3323 additions and 2565 deletions
Download Patch File Download Diff File Expand all files Collapse all files

357
lib/stm32/f4/adc.c
View File

@@ -4,44 +4,46 @@
@brief <b>libopencm3 STM32F4xx Analog to Digital Converters</b>
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
@author @htmlonly &copy; @endhtmlonly 2012
Ken Sarkies <ksarkies@internode.on.net>
@date 30 August 2012
This library supports the A/D Converter Control System in the STM32 series
of ARM Cortex Microcontrollers by ST Microelectronics.
Devices can have up to three A/D converters each with their own set of registers.
However all the A/D converters share a common clock which is prescaled from the APB2
clock by default by a minimum factor of 2 to a maximum of 8. The ADC resolution
can be set to 12, 10, 8 or 6 bits.
Devices can have up to three A/D converters each with their own set of
registers. However all the A/D converters share a common clock which is
prescaled from the APB2 clock by default by a minimum factor of 2 to a maximum
of 8. The ADC resolution can be set to 12, 10, 8 or 6 bits.
Each A/D converter has up to 19 channels:
@li On ADC1 the analog channels 16 is internally connected to the temperature
sensor, channel 17 to V<sub>REFINT</sub>, and channel 18 to V<sub>BATT</sub>.
@li On ADC2 and ADC3 the analog channels 16 - 18 are not used.
The conversions can occur as a one-off conversion whereby the process stops once
conversion is complete. The conversions can also be continuous wherein a new
conversion starts immediately the previous conversion has ended.
The conversions can occur as a one-off conversion whereby the process stops
once conversion is complete. The conversions can also be continuous wherein a
new conversion starts immediately the previous conversion has ended.
Conversion can occur as a single channel conversion or a scan of a group of
channels in either continuous or one-off mode. If more than one channel is converted
in a scan group, DMA must be used to transfer the data as there is only one
result register available. An interrupt can be set to occur at the end of
conversion, which occurs after all channels have been scanned.
channels in either continuous or one-off mode. If more than one channel is
converted in a scan group, DMA must be used to transfer the data as there is
only one result register available. An interrupt can be set to occur at the end
of conversion, which occurs after all channels have been scanned.
A discontinuous mode allows a subgroup of group of a channels to be converted in
bursts of a given length.
A discontinuous mode allows a subgroup of group of a channels to be converted
in bursts of a given length.
Injected conversions allow a second group of channels to be converted separately
from the regular group. An interrupt can be set to occur at the end of
conversion, which occurs after all channels have been scanned.
Injected conversions allow a second group of channels to be converted
separately from the regular group. An interrupt can be set to occur at the end
of conversion, which occurs after all channels have been scanned.
@section adc_f4_api_ex Basic ADC Handling API.
Example 1: Simple single channel conversion polled. Enable the peripheral clock
and ADC, reset ADC and set the prescaler divider. Set multiple mode to independent.
and ADC, reset ADC and set the prescaler divider. Set multiple mode to
independent.
@code
gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO1);
@@ -84,7 +86,7 @@ LGPL License Terms @ref lgpl_license
/**@{*/
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Off
Turn off the ADC to reduce power consumption to a few microamps.
@@ -97,12 +99,12 @@ void adc_off(u32 adc)
ADC_CR2(adc) &= ~ADC_CR2_ADON;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Analog Watchdog for Regular Conversions
The analog watchdog allows the monitoring of an analog signal between two threshold
levels. The thresholds must be preset. Comparison is done before data alignment
takes place, so the thresholds are left-aligned.
The analog watchdog allows the monitoring of an analog signal between two
threshold levels. The thresholds must be preset. Comparison is done before data
alignment takes place, so the thresholds are left-aligned.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
@@ -112,7 +114,7 @@ void adc_enable_analog_watchdog_regular(u32 adc)
ADC_CR1(adc) |= ADC_CR1_AWDEN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable Analog Watchdog for Regular Conversions
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -123,12 +125,12 @@ void adc_disable_analog_watchdog_regular(u32 adc)
ADC_CR1(adc) &= ~ADC_CR1_AWDEN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Analog Watchdog for Injected Conversions
The analog watchdog allows the monitoring of an analog signal between two threshold
levels. The thresholds must be preset. Comparison is done before data alignment
takes place, so the thresholds are left-aligned.
The analog watchdog allows the monitoring of an analog signal between two
threshold levels. The thresholds must be preset. Comparison is done before data
alignment takes place, so the thresholds are left-aligned.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
@@ -138,7 +140,7 @@ void adc_enable_analog_watchdog_injected(u32 adc)
ADC_CR1(adc) |= ADC_CR1_JAWDEN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable Analog Watchdog for Injected Conversions
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -149,7 +151,7 @@ void adc_disable_analog_watchdog_injected(u32 adc)
ADC_CR1(adc) &= ~ADC_CR1_JAWDEN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Discontinuous Mode for Regular Conversions
In this mode the ADC converts, on each trigger, a subgroup of up to 8 of the
@@ -161,17 +163,20 @@ the whole group has been converted, the next trigger will restart conversion
of the subgroup at the beginning of the whole group.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@param[in] length Unsigned int8. Number of channels in the group @ref adc_cr1_discnum
@param[in] length Unsigned int8. Number of channels in the group @ref
adc_cr1_discnum
*/
void adc_enable_discontinuous_mode_regular(u32 adc, u8 length)
{
if ( (length-1) > 7 ) return;
ADC_CR1(adc) |= ADC_CR1_DISCEN;
ADC_CR1(adc) |= ((length-1) << ADC_CR1_DISCNUM_SHIFT);
if ((length-1) > 7) {
return;
}
ADC_CR1(adc) |= ADC_CR1_DISCEN;
ADC_CR1(adc) |= ((length-1) << ADC_CR1_DISCNUM_SHIFT);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable Discontinuous Mode for Regular Conversions
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -182,7 +187,7 @@ void adc_disable_discontinuous_mode_regular(u32 adc)
ADC_CR1(adc) &= ~ADC_CR1_DISCEN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Discontinuous Mode for Injected Conversions
In this mode the ADC converts sequentially one channel of the defined group of
@@ -197,7 +202,7 @@ void adc_enable_discontinuous_mode_injected(u32 adc)
ADC_CR1(adc) |= ADC_CR1_JDISCEN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable Discontinuous Mode for Injected Conversions
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -208,7 +213,7 @@ void adc_disable_discontinuous_mode_injected(u32 adc)
ADC_CR1(adc) &= ~ADC_CR1_JDISCEN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Automatic Injected Conversions
The ADC converts a defined injected group of channels immediately after the
@@ -220,11 +225,11 @@ channels is disabled as required.
void adc_enable_automatic_injected_group_conversion(u32 adc)
{
adc_disable_external_trigger_injected(adc);
adc_disable_external_trigger_injected(adc);
ADC_CR1(adc) |= ADC_CR1_JAUTO;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable Automatic Injected Conversions
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -235,17 +240,18 @@ void adc_disable_automatic_injected_group_conversion(u32 adc)
ADC_CR1(adc) &= ~ADC_CR1_JAUTO;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Analog Watchdog for All Regular and/or Injected Channels
The analog watchdog allows the monitoring of an analog signal between two threshold
levels. The thresholds must be preset. Comparison is done before data alignment
takes place, so the thresholds are left-aligned.
The analog watchdog allows the monitoring of an analog signal between two
threshold levels. The thresholds must be preset. Comparison is done before data
alignment takes place, so the thresholds are left-aligned.
@note The analog watchdog must be enabled for either or both of the regular or
injected channels. If neither are enabled, the analog watchdog feature will be
disabled.
@ref adc_enable_analog_watchdog_injected, @ref adc_enable_analog_watchdog_regular.
@ref adc_enable_analog_watchdog_injected, @ref
adc_enable_analog_watchdog_regular.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
@@ -255,17 +261,18 @@ void adc_enable_analog_watchdog_on_all_channels(u32 adc)
ADC_CR1(adc) &= ~ADC_CR1_AWDSGL;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Analog Watchdog for a Selected Channel
The analog watchdog allows the monitoring of an analog signal between two threshold
levels. The thresholds must be preset. Comparison is done before data alignment
takes place, so the thresholds are left-aligned.
The analog watchdog allows the monitoring of an analog signal between two
threshold levels. The thresholds must be preset. Comparison is done before data
alignment takes place, so the thresholds are left-aligned.
@note The analog watchdog must be enabled for either or both of the regular or
injected channels. If neither are enabled, the analog watchdog feature will be
disabled. If both are enabled, the same channel number is monitored.
@ref adc_enable_analog_watchdog_injected, @ref adc_enable_analog_watchdog_regular.
@ref adc_enable_analog_watchdog_injected, @ref
adc_enable_analog_watchdog_regular.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@param[in] channel Unsigned int8. ADC channel number @ref adc_watchdog_channel
@@ -276,13 +283,14 @@ void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel)
u32 reg32;
reg32 = (ADC_CR1(adc) & ~ADC_CR1_AWDCH_MASK); /* Clear bits [4:0]. */
if (channel < 18)
if (channel < 18) {
reg32 |= channel;
}
ADC_CR1(adc) = reg32;
ADC_CR1(adc) |= ADC_CR1_AWDSGL;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Set Scan Mode
In this mode a conversion consists of a scan of the predefined set of channels,
@@ -297,7 +305,7 @@ void adc_enable_scan_mode(u32 adc)
ADC_CR1(adc) |= ADC_CR1_SCAN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable Scan Mode
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -308,7 +316,7 @@ void adc_disable_scan_mode(u32 adc)
ADC_CR1(adc) &= ~ADC_CR1_SCAN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Injected End-Of-Conversion Interrupt
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -319,7 +327,7 @@ void adc_enable_eoc_interrupt_injected(u32 adc)
ADC_CR1(adc) |= ADC_CR1_JEOCIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable Injected End-Of-Conversion Interrupt
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -330,7 +338,7 @@ void adc_disable_eoc_interrupt_injected(u32 adc)
ADC_CR1(adc) &= ~ADC_CR1_JEOCIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Analog Watchdog Interrupt
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -341,7 +349,7 @@ void adc_enable_awd_interrupt(u32 adc)
ADC_CR1(adc) |= ADC_CR1_AWDIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable Analog Watchdog Interrupt
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -352,7 +360,7 @@ void adc_disable_awd_interrupt(u32 adc)
ADC_CR1(adc) &= ~ADC_CR1_AWDIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Regular End-Of-Conversion Interrupt
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -363,7 +371,7 @@ void adc_enable_eoc_interrupt(u32 adc)
ADC_CR1(adc) |= ADC_CR1_EOCIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable Regular End-Of-Conversion Interrupt
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -374,7 +382,7 @@ void adc_disable_eoc_interrupt(u32 adc)
ADC_CR1(adc) &= ~ADC_CR1_EOCIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Software Triggered Conversion on Regular Channels
This starts conversion on a set of defined regular channels. It is cleared by
@@ -392,7 +400,7 @@ void adc_start_conversion_regular(u32 adc)
while (ADC_CR2(adc) & ADC_CR2_SWSTART);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Software Triggered Conversion on Injected Channels
This starts conversion on a set of defined injected channels. It is cleared by
@@ -410,7 +418,7 @@ void adc_start_conversion_injected(u32 adc)
while (ADC_CR2(adc) & ADC_CR2_JSWSTART);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Set the Data as Left Aligned
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -421,7 +429,7 @@ void adc_set_left_aligned(u32 adc)
ADC_CR2(adc) |= ADC_CR2_ALIGN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Set the Data as Right Aligned
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -432,7 +440,7 @@ void adc_set_right_aligned(u32 adc)
ADC_CR2(adc) &= ~ADC_CR2_ALIGN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable DMA Transfers
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -440,10 +448,10 @@ void adc_set_right_aligned(u32 adc)
void adc_enable_dma(u32 adc)
{
ADC_CR2(adc) |= ADC_CR2_DMA;
ADC_CR2(adc) |= ADC_CR2_DMA;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable DMA Transfers
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -451,10 +459,10 @@ void adc_enable_dma(u32 adc)
void adc_disable_dma(u32 adc)
{
ADC_CR2(adc) &= ~ADC_CR2_DMA;
ADC_CR2(adc) &= ~ADC_CR2_DMA;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Continuous Conversion Mode
In this mode the ADC starts a new conversion of a single channel or a channel
@@ -468,7 +476,7 @@ void adc_set_continuous_conversion_mode(u32 adc)
ADC_CR2(adc) |= ADC_CR2_CONT;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Single Conversion Mode
In this mode the ADC performs a conversion of one channel or a channel group
@@ -482,13 +490,14 @@ void adc_set_single_conversion_mode(u32 adc)
ADC_CR2(adc) &= ~ADC_CR2_CONT;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Set the Sample Time for a Single Channel
The sampling time can be selected in ADC clock cycles from 1.5 to 239.5.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@param[in] channel Unsigned int8. ADC Channel integer 0..18 or from @ref adc_channel
@param[in] channel Unsigned int8. ADC Channel integer 0..18 or from @ref
adc_channel
@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg
*/
@@ -509,11 +518,11 @@ void adc_set_sample_time(u32 adc, u8 channel, u8 time)
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Set the Sample Time for All Channels
The sampling time can be selected in ADC clock cycles from 1.5 to 239.5, same for
all channels.
The sampling time can be selected in ADC clock cycles from 1.5 to 239.5, same
for all channels.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg
@@ -524,16 +533,18 @@ void adc_set_sample_time_on_all_channels(u32 adc, u8 time)
u8 i;
u32 reg32 = 0;
for (i = 0; i <= 9; i++)
for (i = 0; i <= 9; i++) {
reg32 |= (time << (i * 3));
}
ADC_SMPR2(adc) = reg32;
for (i = 10; i <= 17; i++)
for (i = 10; i <= 17; i++) {
reg32 |= (time << ((i - 10) * 3));
}
ADC_SMPR1(adc) = reg32;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Set Analog Watchdog Upper Threshold
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -549,7 +560,7 @@ void adc_set_watchdog_high_threshold(u32 adc, u16 threshold)
ADC_HTR(adc) = reg32;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Set Analog Watchdog Lower Threshold
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -565,12 +576,12 @@ void adc_set_watchdog_low_threshold(u32 adc, u16 threshold)
ADC_LTR(adc) = reg32;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Set a Regular Channel Conversion Sequence
Define a sequence of channels to be converted as a regular group with a length
from 1 to 16 channels. If this is called during conversion, the current conversion
is reset and conversion begins again with the newly defined group.
from 1 to 16 channels. If this is called during conversion, the current
conversion is reset and conversion begins again with the newly defined group.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@param[in] length Unsigned int8. Number of channels in the group.
@@ -583,30 +594,34 @@ void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[])
u8 i = 0;
/* Maximum sequence length is 16 channels. */
if (length > 16)
if (length > 16) {
return;
}
for (i = 1; i <= length; i++) {
if (i <= 6)
if (i <= 6) {
reg32_3 |= (channel[i - 1] << ((i - 1) * 5));
if ((i > 6) & (i <= 12))
}
if ((i > 6) & (i <= 12)) {
reg32_2 |= (channel[i - 1] << ((i - 6 - 1) * 5));
if ((i > 12) & (i <= 16))
}
if ((i > 12) & (i <= 16)) {
reg32_1 |= (channel[i - 1] << ((i - 12 - 1) * 5));
}
}
reg32_1 |= ((length -1) << ADC_SQR1_L_LSB);
reg32_1 |= ((length - 1) << ADC_SQR1_L_LSB);
ADC_SQR1(adc) = reg32_1;
ADC_SQR2(adc) = reg32_2;
ADC_SQR3(adc) = reg32_3;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Set an Injected Channel Conversion Sequence
Defines a sequence of channels to be converted as an injected group with a length
from 1 to 4 channels. If this is called during conversion, the current conversion
is reset and conversion begins again with the newly defined group.
Defines a sequence of channels to be converted as an injected group with a
length from 1 to 4 channels. If this is called during conversion, the current
conversion is reset and conversion begins again with the newly defined group.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@param[in] length Unsigned int8. Number of channels in the group.
@@ -619,18 +634,20 @@ void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[])
u8 i = 0;
/* Maximum sequence length is 4 channels. */
if ((length-1) > 3)
if ((length-1) > 3) {
return;
}
for (i = 1; i <= length; i++)
for (i = 1; i <= length; i++) {
reg32 |= (channel[4 - i] << ((4 - i) * 5));
}
reg32 |= ((length - 1) << ADC_JSQR_JL_LSB);
ADC_JSQR(adc) = reg32;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Read the End-of-Conversion Flag
This flag is set after all channels of a regular or injected group have been
@@ -642,10 +659,10 @@ converted.
bool adc_eoc(u32 adc)
{
return ((ADC_SR(adc) & ADC_SR_EOC) != 0);
return (ADC_SR(adc) & ADC_SR_EOC) != 0;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Read the End-of-Conversion Flag for Injected Conversion
This flag is set after all channels of an injected group have been converted.
@@ -656,10 +673,10 @@ This flag is set after all channels of an injected group have been converted.
bool adc_eoc_injected(u32 adc)
{
return ((ADC_SR(adc) & ADC_SR_JEOC) != 0);
return (ADC_SR(adc) & ADC_SR_JEOC) != 0;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Read from the Regular Conversion Result Register
The result read back is 12 bits, right or left aligned within the first 16 bits.
@@ -672,15 +689,16 @@ an appropriate dual mode has been set @see adc_set_dual_mode.
u32 adc_read_regular(u32 adc)
{
return ADC_DR(adc);
return ADC_DR(adc);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Read from an Injected Conversion Result Register
The result read back from the selected injected result register (one of four) is
12 bits, right or left aligned within the first 16 bits. The result can have a
negative value if the injected channel offset has been set @see adc_set_injected_offset.
The result read back from the selected injected result register (one of four)
is 12 bits, right or left aligned within the first 16 bits. The result can have
a negative value if the injected channel offset has been set @see
adc_set_injected_offset.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@param[in] reg Unsigned int8. Register number (1 ... 4).
@@ -689,24 +707,24 @@ negative value if the injected channel offset has been set @see adc_set_injected
u32 adc_read_injected(u32 adc, u8 reg)
{
switch (reg) {
case 1:
return ADC_JDR1(adc);
case 2:
return ADC_JDR2(adc);
case 3:
return ADC_JDR3(adc);
case 4:
return ADC_JDR4(adc);
}
switch (reg) {
case 1:
return ADC_JDR1(adc);
case 2:
return ADC_JDR2(adc);
case 3:
return ADC_JDR3(adc);
case 4:
return ADC_JDR4(adc);
}
return 0;
}
/*-----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------*/
/** @brief ADC Set the Injected Channel Data Offset
This value is subtracted from the injected channel results after conversion
is complete, and can result in negative results. A separate value can be specified
This value is subtracted from the injected channel results after conversion is
complete, and can result in negative results. A separate value can be specified
for each injected data register.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -716,23 +734,23 @@ for each injected data register.
void adc_set_injected_offset(u32 adc, u8 reg, u32 offset)
{
switch (reg) {
case 1:
ADC_JOFR1(adc) = offset;
break;
case 2:
ADC_JOFR2(adc) = offset;
break;
case 3:
ADC_JOFR3(adc) = offset;
break;
case 4:
ADC_JOFR4(adc) = offset;
break;
}
switch (reg) {
case 1:
ADC_JOFR1(adc) = offset;
break;
case 2:
ADC_JOFR2(adc) = offset;
break;
case 3:
ADC_JOFR3(adc) = offset;
break;
case 4:
ADC_JOFR4(adc) = offset;
break;
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Power On
If the ADC is in power-down mode then it is powered up. The application needs
@@ -747,12 +765,13 @@ void adc_power_on(u32 adc)
ADC_CR2(adc) |= ADC_CR2_ADON;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Set Clock Prescale
The ADC clock taken from the APB2 clock can be scaled down by 2, 4, 6 or 8.
@param[in] prescale Unsigned int32. Prescale value for ADC Clock @ref adc_ccr_adcpre
@param[in] prescale Unsigned int32. Prescale value for ADC Clock @ref
adc_ccr_adcpre
*/
void adc_set_clk_prescale(u32 prescale)
@@ -761,7 +780,7 @@ void adc_set_clk_prescale(u32 prescale)
ADC_CCR = reg32;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Set Dual/Triple Mode
The multiple mode uses ADC1 as master, ADC2 and optionally ADC3 in a slave
@@ -777,16 +796,17 @@ void adc_set_multi_mode(u32 mode)
ADC_CCR |= mode;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable an External Trigger for Regular Channels
This enables an external trigger for set of defined regular channels, and sets the
polarity of the trigger event: rising or falling edge or both. Note that if the
trigger polarity is zero, triggering is disabled.
This enables an external trigger for set of defined regular channels, and sets
the polarity of the trigger event: rising or falling edge or both. Note that if
the trigger polarity is zero, triggering is disabled.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@param[in] trigger Unsigned int32. Trigger identifier @ref adc_trigger_regular
@param[in] polarity Unsigned int32. Trigger polarity @ref adc_trigger_polarity_regular
@param[in] polarity Unsigned int32. Trigger polarity @ref
adc_trigger_polarity_regular
*/
void adc_enable_external_trigger_regular(u32 adc, u32 trigger, u32 polarity)
@@ -798,7 +818,7 @@ void adc_enable_external_trigger_regular(u32 adc, u32 trigger, u32 polarity)
ADC_CR2(adc) = reg32;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable an External Trigger for Regular Channels
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -809,15 +829,16 @@ void adc_disable_external_trigger_regular(u32 adc)
ADC_CR2(adc) &= ~ADC_CR2_EXTEN_MASK;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable an External Trigger for Injected Channels
This enables an external trigger for set of defined injected channels, and sets the
polarity of the trigger event: rising or falling edge or both.
This enables an external trigger for set of defined injected channels, and sets
the polarity of the trigger event: rising or falling edge or both.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@param[in] trigger Unsigned int8. Trigger identifier @ref adc_trigger_injected
@param[in] polarity Unsigned int32. Trigger polarity @ref adc_trigger_polarity_injected
@param[in] polarity Unsigned int32. Trigger polarity @ref
adc_trigger_polarity_injected
*/
void adc_enable_external_trigger_injected(u32 adc, u32 trigger, u32 polarity)
@@ -829,7 +850,7 @@ void adc_enable_external_trigger_injected(u32 adc, u32 trigger, u32 polarity)
ADC_CR2(adc) = reg32;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable an External Trigger for Injected Channels
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -840,11 +861,11 @@ void adc_disable_external_trigger_injected(u32 adc)
ADC_CR2(adc) &= ~ADC_CR2_JEXTEN_MASK;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Set Resolution
ADC Resolution can be reduced from 12 bits to 10, 8 or 6 bits for a corresponding
reduction in conversion time (resolution + 3 ADC clock cycles).
ADC Resolution can be reduced from 12 bits to 10, 8 or 6 bits for a
corresponding reduction in conversion time (resolution + 3 ADC clock cycles).
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@param[in] resolution Unsigned int8. Resolution value @ref adc_cr1_res
@@ -859,7 +880,7 @@ void adc_set_resolution(u32 adc, u16 resolution)
ADC_CR1(adc) = reg32;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable the Overrun Interrupt
The overrun interrupt is generated when data is not read from a result register
@@ -874,7 +895,7 @@ void adc_enable_overrun_interrupt(u32 adc)
ADC_CR1(adc) |= ADC_CR1_OVRIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable the Overrun Interrupt
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -885,12 +906,12 @@ void adc_disable_overrun_interrupt(u32 adc)
ADC_CR1(adc) &= ~ADC_CR1_OVRIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Read the Overrun Flag
The overrun flag is set when data is not read from a result register before the next
conversion is written. If DMA is enabled, all transfers are terminated and any
conversion sequence is aborted.
The overrun flag is set when data is not read from a result register before the
next conversion is written. If DMA is enabled, all transfers are terminated and
any conversion sequence is aborted.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@returns Unsigned int32 conversion result.
@@ -898,10 +919,10 @@ conversion sequence is aborted.
bool adc_get_overrun_flag(u32 adc)
{
return (ADC_SR(adc) & ADC_SR_OVR);
return ADC_SR(adc) & ADC_SR_OVR;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Clear Overrun Flags
The overrun flag is cleared. Note that if an overrun occurs, DMA is terminated.
@@ -918,7 +939,7 @@ void adc_clear_overrun_flag(u32 adc)
ADC_SR(adc) &= ~ADC_SR_OVR;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable an EOC for Each Conversion
The EOC is set after each conversion in a sequence rather than at the end of the
@@ -932,11 +953,11 @@ void adc_eoc_after_each(u32 adc)
ADC_CR2(adc) |= ADC_CR2_EOCS;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable the EOC for Each Conversion
The EOC is set at the end of each sequence rather than after each conversion in the
sequence. Overrun detection is enabled always.
The EOC is set at the end of each sequence rather than after each conversion in
the sequence. Overrun detection is enabled always.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
@@ -946,11 +967,11 @@ void adc_eoc_after_group(u32 adc)
ADC_CR2(adc) &= ~ADC_CR2_EOCS;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Set DMA to Continue
This must be set to allow DMA to continue to operate after the last conversion in
the DMA sequence. This allows DMA to be used in continuous circular mode.
This must be set to allow DMA to continue to operate after the last conversion
in the DMA sequence. This allows DMA to be used in continuous circular mode.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
@@ -960,7 +981,7 @@ void adc_set_dma_continue(u32 adc)
ADC_CR2(adc) |= ADC_CR2_DDS;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Set DMA to Terminate
This must be set to allow DMA to terminate after the last conversion in the DMA
@@ -973,7 +994,7 @@ void adc_set_dma_terminate(u32 adc)
{
ADC_CR2(adc) &= ~ADC_CR2_DDS;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Read the Analog Watchdog Flag
This flag is set when the converted voltage crosses the high or low thresholds.
@@ -984,10 +1005,10 @@ This flag is set when the converted voltage crosses the high or low thresholds.
bool adc_awd(u32 adc)
{
return (ADC_SR(adc) & ADC_SR_AWD);
return ADC_SR(adc) & ADC_SR_AWD;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable The Temperature Sensor
This enables both the sensor and the reference voltage measurements on channels
@@ -1001,7 +1022,7 @@ void adc_enable_temperature_sensor()
ADC_CCR |= ADC_CCR_TSVREFE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable The Temperature Sensor
Disabling this will reduce power consumption from the sensor and the reference
@@ -1015,7 +1036,7 @@ void adc_disable_temperature_sensor()
ADC_CCR &= ~ADC_CCR_TSVREFE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/**@}*/

5
lib/stm32/f4/pwr.c
View File

@@ -38,8 +38,9 @@ LGPL License Terms @ref lgpl_license
void pwr_set_vos_scale(vos_scale_t scale)
{
if (scale == SCALE1)
if (scale == SCALE1) {
PWR_CR |= PWR_CR_VOS;
else if (scale == SCALE2)
} else if (scale == SCALE2) {
PWR_CR &= PWR_CR_VOS;
}
}

733
lib/stm32/f4/rcc.c
View File

@@ -28,506 +28,513 @@
u32 rcc_ppre1_frequency = 16000000;
u32 rcc_ppre2_frequency = 16000000;
const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] =
{
{ /* 48MHz */
.pllm = 8,
.plln = 96,
.pllp = 2,
.pllq = 2,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.power_save = 1,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS,
.apb1_frequency = 12000000,
.apb2_frequency = 24000000,
},
{ /* 120MHz */
.pllm = 8,
.plln = 240,
.pllp = 2,
.pllq = 5,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.power_save = 1,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS,
.apb1_frequency = 30000000,
.apb2_frequency = 60000000,
},
{ /* 168MHz */
.pllm = 8,
.plln = 336,
.pllp = 2,
.pllq = 7,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_5WS,
.apb1_frequency = 42000000,
.apb2_frequency = 84000000,
},
const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] = {
{ /* 48MHz */
.pllm = 8,
.plln = 96,
.pllp = 2,
.pllq = 2,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.power_save = 1,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
FLASH_ACR_LATENCY_3WS,
.apb1_frequency = 12000000,
.apb2_frequency = 24000000,
},
{ /* 120MHz */
.pllm = 8,
.plln = 240,
.pllp = 2,
.pllq = 5,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.power_save = 1,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
FLASH_ACR_LATENCY_3WS,
.apb1_frequency = 30000000,
.apb2_frequency = 60000000,
},
{ /* 168MHz */
.pllm = 8,
.plln = 336,
.pllp = 2,
.pllq = 7,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
FLASH_ACR_LATENCY_5WS,
.apb1_frequency = 42000000,
.apb2_frequency = 84000000,
},
};
const clock_scale_t hse_12mhz_3v3[CLOCK_3V3_END] =
{
{ /* 48MHz */
.pllm = 12,
.plln = 96,
.pllp = 2,
.pllq = 2,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.power_save = 1,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS,
.apb1_frequency = 12000000,
.apb2_frequency = 24000000,
},
{ /* 120MHz */
.pllm = 12,
.plln = 240,
.pllp = 2,
.pllq = 5,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.power_save = 1,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS,
.apb1_frequency = 30000000,
.apb2_frequency = 60000000,
},
{ /* 168MHz */
.pllm = 12,
.plln = 336,
.pllp = 2,
.pllq = 7,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_5WS,
.apb1_frequency = 42000000,
.apb2_frequency = 84000000,
},
const clock_scale_t hse_12mhz_3v3[CLOCK_3V3_END] = {
{ /* 48MHz */
.pllm = 12,
.plln = 96,
.pllp = 2,
.pllq = 2,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.power_save = 1,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
FLASH_ACR_LATENCY_3WS,
.apb1_frequency = 12000000,
.apb2_frequency = 24000000,
},
{ /* 120MHz */
.pllm = 12,
.plln = 240,
.pllp = 2,
.pllq = 5,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.power_save = 1,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
FLASH_ACR_LATENCY_3WS,
.apb1_frequency = 30000000,
.apb2_frequency = 60000000,
},
{ /* 168MHz */
.pllm = 12,
.plln = 336,
.pllp = 2,
.pllq = 7,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
FLASH_ACR_LATENCY_5WS,
.apb1_frequency = 42000000,
.apb2_frequency = 84000000,
},
};
const clock_scale_t hse_16mhz_3v3[CLOCK_3V3_END] =
{
{ /* 48MHz */
.pllm = 16,
.plln = 96,
.pllp = 2,
.pllq = 2,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.power_save = 1,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS,
.apb1_frequency = 12000000,
.apb2_frequency = 24000000,
},
{ /* 120MHz */
.pllm = 16,
.plln = 240,
.pllp = 2,
.pllq = 5,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.power_save = 1,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS,
.apb1_frequency = 30000000,
.apb2_frequency = 60000000,
},
{ /* 168MHz */
.pllm = 16,
.plln = 336,
.pllp = 2,
.pllq = 7,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_5WS,
.apb1_frequency = 42000000,
.apb2_frequency = 84000000,
},
const clock_scale_t hse_16mhz_3v3[CLOCK_3V3_END] = {
{ /* 48MHz */
.pllm = 16,
.plln = 96,
.pllp = 2,
.pllq = 2,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.power_save = 1,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
FLASH_ACR_LATENCY_3WS,
.apb1_frequency = 12000000,
.apb2_frequency = 24000000,
},
{ /* 120MHz */
.pllm = 16,
.plln = 240,
.pllp = 2,
.pllq = 5,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.power_save = 1,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
FLASH_ACR_LATENCY_3WS,
.apb1_frequency = 30000000,
.apb2_frequency = 60000000,
},
{ /* 168MHz */
.pllm = 16,
.plln = 336,
.pllp = 2,
.pllq = 7,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
FLASH_ACR_LATENCY_5WS,
.apb1_frequency = 42000000,
.apb2_frequency = 84000000,
},
};
void rcc_osc_ready_int_clear(osc_t osc)
{
switch (osc) {
case PLL:
RCC_CIR |= RCC_CIR_PLLRDYC;
break;
case HSE:
RCC_CIR |= RCC_CIR_HSERDYC;
break;
case HSI:
RCC_CIR |= RCC_CIR_HSIRDYC;
break;
case LSE:
RCC_CIR |= RCC_CIR_LSERDYC;
break;
case LSI:
RCC_CIR |= RCC_CIR_LSIRDYC;
break;
}
switch (osc) {
case PLL:
RCC_CIR |= RCC_CIR_PLLRDYC;
break;
case HSE:
RCC_CIR |= RCC_CIR_HSERDYC;
break;
case HSI:
RCC_CIR |= RCC_CIR_HSIRDYC;
break;
case LSE:
RCC_CIR |= RCC_CIR_LSERDYC;
break;
case LSI:
RCC_CIR |= RCC_CIR_LSIRDYC;
break;
}
}
void rcc_osc_ready_int_enable(osc_t osc)
{
switch (osc) {
case PLL:
RCC_CIR |= RCC_CIR_PLLRDYIE;
break;
case HSE:
RCC_CIR |= RCC_CIR_HSERDYIE;
break;
case HSI:
RCC_CIR |= RCC_CIR_HSIRDYIE;
break;
case LSE:
RCC_CIR |= RCC_CIR_LSERDYIE;
break;
case LSI:
RCC_CIR |= RCC_CIR_LSIRDYIE;
break;
}
switch (osc) {
case PLL:
RCC_CIR |= RCC_CIR_PLLRDYIE;
break;
case HSE:
RCC_CIR |= RCC_CIR_HSERDYIE;
break;
case HSI:
RCC_CIR |= RCC_CIR_HSIRDYIE;
break;
case LSE:
RCC_CIR |= RCC_CIR_LSERDYIE;
break;
case LSI:
RCC_CIR |= RCC_CIR_LSIRDYIE;
break;
}
}
void rcc_osc_ready_int_disable(osc_t osc)
{
switch (osc) {
case PLL:
RCC_CIR &= ~RCC_CIR_PLLRDYIE;
break;
case HSE:
RCC_CIR &= ~RCC_CIR_HSERDYIE;
break;
case HSI:
RCC_CIR &= ~RCC_CIR_HSIRDYIE;
break;
case LSE:
RCC_CIR &= ~RCC_CIR_LSERDYIE;
break;
case LSI:
RCC_CIR &= ~RCC_CIR_LSIRDYIE;
break;
}
switch (osc) {
case PLL:
RCC_CIR &= ~RCC_CIR_PLLRDYIE;
break;
case HSE:
RCC_CIR &= ~RCC_CIR_HSERDYIE;
break;
case HSI:
RCC_CIR &= ~RCC_CIR_HSIRDYIE;
break;
case LSE:
RCC_CIR &= ~RCC_CIR_LSERDYIE;
break;
case LSI:
RCC_CIR &= ~RCC_CIR_LSIRDYIE;
break;
}
}
int rcc_osc_ready_int_flag(osc_t osc)
{
switch (osc) {
case PLL:
return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0);
break;
case HSE:
return ((RCC_CIR & RCC_CIR_HSERDYF) != 0);
break;
case HSI:
return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0);
break;
case LSE:
return ((RCC_CIR & RCC_CIR_LSERDYF) != 0);
break;
case LSI:
return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0);
break;
}
switch (osc) {
case PLL:
return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0);
break;
case HSE:
return ((RCC_CIR & RCC_CIR_HSERDYF) != 0);
break;
case HSI:
return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0);
break;
case LSE:
return ((RCC_CIR & RCC_CIR_LSERDYF) != 0);
break;
case LSI:
return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0);
break;
}
cm3_assert_not_reached();
cm3_assert_not_reached();
}
void rcc_css_int_clear(void)
{
RCC_CIR |= RCC_CIR_CSSC;
RCC_CIR |= RCC_CIR_CSSC;
}
int rcc_css_int_flag(void)
{
return ((RCC_CIR & RCC_CIR_CSSF) != 0);
return ((RCC_CIR & RCC_CIR_CSSF) != 0);
}
void rcc_wait_for_osc_ready(osc_t osc)
{
switch (osc) {
case PLL:
while ((RCC_CR & RCC_CR_PLLRDY) == 0);
break;
case HSE:
while ((RCC_CR & RCC_CR_HSERDY) == 0);
break;
case HSI:
while ((RCC_CR & RCC_CR_HSIRDY) == 0);
break;
case LSE:
while ((RCC_BDCR & RCC_BDCR_LSERDY) == 0);
break;
case LSI:
while ((RCC_CSR & RCC_CSR_LSIRDY) == 0);
break;
}
switch (osc) {
case PLL:
while ((RCC_CR & RCC_CR_PLLRDY) == 0);
break;
case HSE:
while ((RCC_CR & RCC_CR_HSERDY) == 0);
break;
case HSI:
while ((RCC_CR & RCC_CR_HSIRDY) == 0);
break;
case LSE:
while ((RCC_BDCR & RCC_BDCR_LSERDY) == 0);
break;
case LSI:
while ((RCC_CSR & RCC_CSR_LSIRDY) == 0);
break;
}
}
void rcc_wait_for_sysclk_status(osc_t osc)
{
switch (osc) {
case PLL:
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_PLL);
break;
case HSE:
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSE);
break;
case HSI:
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSI);
break;
default:
/* Shouldn't be reached. */
break;
}
switch (osc) {
case PLL:
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_PLL);
break;
case HSE:
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSE);
break;
case HSI:
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSI);
break;
default:
/* Shouldn't be reached. */
break;
}
}
void rcc_osc_on(osc_t osc)
{
switch (osc) {
case PLL:
RCC_CR |= RCC_CR_PLLON;
break;
case HSE:
RCC_CR |= RCC_CR_HSEON;
break;
case HSI:
RCC_CR |= RCC_CR_HSION;
break;
case LSE:
RCC_BDCR |= RCC_BDCR_LSEON;
break;
case LSI:
RCC_CSR |= RCC_CSR_LSION;
break;
}
switch (osc) {
case PLL:
RCC_CR |= RCC_CR_PLLON;
break;
case HSE:
RCC_CR |= RCC_CR_HSEON;
break;
case HSI:
RCC_CR |= RCC_CR_HSION;
break;
case LSE:
RCC_BDCR |= RCC_BDCR_LSEON;
break;
case LSI:
RCC_CSR |= RCC_CSR_LSION;
break;
}
}
void rcc_osc_off(osc_t osc)
{
switch (osc) {
case PLL:
RCC_CR &= ~RCC_CR_PLLON;
break;
case HSE:
RCC_CR &= ~RCC_CR_HSEON;
break;
case HSI:
RCC_CR &= ~RCC_CR_HSION;
break;
case LSE:
RCC_BDCR &= ~RCC_BDCR_LSEON;
break;
case LSI:
RCC_CSR &= ~RCC_CSR_LSION;
break;
}
switch (osc) {
case PLL:
RCC_CR &= ~RCC_CR_PLLON;
break;
case HSE:
RCC_CR &= ~RCC_CR_HSEON;
break;
case HSI:
RCC_CR &= ~RCC_CR_HSION;
break;
case LSE:
RCC_BDCR &= ~RCC_BDCR_LSEON;
break;
case LSI:
RCC_CSR &= ~RCC_CSR_LSION;
break;
}
}
void rcc_css_enable(void)
{
RCC_CR |= RCC_CR_CSSON;
RCC_CR |= RCC_CR_CSSON;
}
void rcc_css_disable(void)
{
RCC_CR &= ~RCC_CR_CSSON;
RCC_CR &= ~RCC_CR_CSSON;
}
void rcc_osc_bypass_enable(osc_t osc)
{
switch (osc) {
case HSE:
RCC_CR |= RCC_CR_HSEBYP;
break;
case LSE:
RCC_BDCR |= RCC_BDCR_LSEBYP;
break;
case PLL:
case HSI:
case LSI:
/* Do nothing, only HSE/LSE allowed here. */
break;
}
switch (osc) {
case HSE:
RCC_CR |= RCC_CR_HSEBYP;
break;
case LSE:
RCC_BDCR |= RCC_BDCR_LSEBYP;
break;
case PLL:
case HSI:
case LSI:
/* Do nothing, only HSE/LSE allowed here. */
break;
}
}
void rcc_osc_bypass_disable(osc_t osc)
{
switch (osc) {
case HSE:
RCC_CR &= ~RCC_CR_HSEBYP;
break;
case LSE:
RCC_BDCR &= ~RCC_BDCR_LSEBYP;
break;
case PLL:
case HSI:
case LSI:
/* Do nothing, only HSE/LSE allowed here. */
break;
}
switch (osc) {
case HSE:
RCC_CR &= ~RCC_CR_HSEBYP;
break;
case LSE:
RCC_BDCR &= ~RCC_BDCR_LSEBYP;
break;
case PLL:
case HSI:
case LSI:
/* Do nothing, only HSE/LSE allowed here. */
break;
}
}
void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en)
{
*reg |= en;
*reg |= en;
}
void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en)
{
*reg &= ~en;
*reg &= ~en;
}
void rcc_peripheral_reset(volatile u32 *reg, u32 reset)
{
*reg |= reset;
*reg |= reset;
}
void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset)
{
*reg &= ~clear_reset;
*reg &= ~clear_reset;
}
void rcc_set_sysclk_source(u32 clk)
{
u32 reg32;
u32 reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 1) | (1 << 0));
RCC_CFGR = (reg32 | clk);
reg32 = RCC_CFGR;
reg32 &= ~((1 << 1) | (1 << 0));
RCC_CFGR = (reg32 | clk);
}
void rcc_set_pll_source(u32 pllsrc)
{
u32 reg32;
u32 reg32;
reg32 = RCC_PLLCFGR;
reg32 &= ~(1 << 22);
RCC_PLLCFGR = (reg32 | (pllsrc << 22));
reg32 = RCC_PLLCFGR;
reg32 &= ~(1 << 22);
RCC_PLLCFGR = (reg32 | (pllsrc << 22));
}
void rcc_set_ppre2(u32 ppre2)
{
u32 reg32;
u32 reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 13) | (1 << 14) | (1 << 15));
RCC_CFGR = (reg32 | (ppre2 << 13));
reg32 = RCC_CFGR;
reg32 &= ~((1 << 13) | (1 << 14) | (1 << 15));
RCC_CFGR = (reg32 | (ppre2 << 13));
}
void rcc_set_ppre1(u32 ppre1)
{
u32 reg32;
u32 reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 10) | (1 << 11) | (1 << 12));
RCC_CFGR = (reg32 | (ppre1 << 10));
reg32 = RCC_CFGR;
reg32 &= ~((1 << 10) | (1 << 11) | (1 << 12));
RCC_CFGR = (reg32 | (ppre1 << 10));
}
void rcc_set_hpre(u32 hpre)
{
u32 reg32;
u32 reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7));
RCC_CFGR = (reg32 | (hpre << 4));
reg32 = RCC_CFGR;
reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7));
RCC_CFGR = (reg32 | (hpre << 4));
}
void rcc_set_rtcpre(u32 rtcpre)
{
u32 reg32;
u32 reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 16) | (1 << 17) | (1 << 18) | (1 << 19) | (1 << 20));
RCC_CFGR = (reg32 | (rtcpre << 16));
reg32 = RCC_CFGR;
reg32 &= ~((1 << 16) | (1 << 17) | (1 << 18) | (1 << 19) | (1 << 20));
RCC_CFGR = (reg32 | (rtcpre << 16));
}
void rcc_set_main_pll_hsi(u32 pllm, u32 plln, u32 pllp, u32 pllq)
{
RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
(plln << RCC_PLLCFGR_PLLN_SHIFT) |
(((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) |
(pllq << RCC_PLLCFGR_PLLQ_SHIFT);
RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
(plln << RCC_PLLCFGR_PLLN_SHIFT) |
(((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) |
(pllq << RCC_PLLCFGR_PLLQ_SHIFT);
}
void rcc_set_main_pll_hse(u32 pllm, u32 plln, u32 pllp, u32 pllq)
{
RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
(plln << RCC_PLLCFGR_PLLN_SHIFT) |
(((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) |
RCC_PLLCFGR_PLLSRC |
(pllq << RCC_PLLCFGR_PLLQ_SHIFT);
RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
(plln << RCC_PLLCFGR_PLLN_SHIFT) |
(((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) |
RCC_PLLCFGR_PLLSRC |
(pllq << RCC_PLLCFGR_PLLQ_SHIFT);
}
u32 rcc_system_clock_source(void)
{
/* Return the clock source which is used as system clock. */
return ((RCC_CFGR & 0x000c) >> 2);
/* Return the clock source which is used as system clock. */
return (RCC_CFGR & 0x000c) >> 2;
}
void rcc_clock_setup_hse_3v3(const clock_scale_t *clock)
{
/* Enable internal high-speed oscillator. */
rcc_osc_on(HSI);
rcc_wait_for_osc_ready(HSI);
/* Enable internal high-speed oscillator. */
rcc_osc_on(HSI);
rcc_wait_for_osc_ready(HSI);
/* Select HSI as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_HSI);
/* Select HSI as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_HSI);
/* Enable external high-speed oscillator 8MHz. */
rcc_osc_on(HSE);
rcc_wait_for_osc_ready(HSE);
/* Enable external high-speed oscillator 8MHz. */
rcc_osc_on(HSE);
rcc_wait_for_osc_ready(HSE);
/* Enable/disable high performance mode */
if (!clock->power_save)
pwr_set_vos_scale(SCALE1);
else
pwr_set_vos_scale(SCALE2);
/* Enable/disable high performance mode */
if (!clock->power_save) {
pwr_set_vos_scale(SCALE1);
} else {
pwr_set_vos_scale(SCALE2);
}
/*
* Set prescalers for AHB, ADC, ABP1, ABP2.
* Do this before touching the PLL (TODO: why?).
*/
rcc_set_hpre(clock->hpre);
rcc_set_ppre1(clock->ppre1);
rcc_set_ppre2(clock->ppre2);
/*
* Set prescalers for AHB, ADC, ABP1, ABP2.
* Do this before touching the PLL (TODO: why?).
*/
rcc_set_hpre(clock->hpre);
rcc_set_ppre1(clock->ppre1);
rcc_set_ppre2(clock->ppre2);
rcc_set_main_pll_hse(clock->pllm, clock->plln,
clock->pllp, clock->pllq);
rcc_set_main_pll_hse(clock->pllm, clock->plln,
clock->pllp, clock->pllq);
/* Enable PLL oscillator and wait for it to stabilize. */
rcc_osc_on(PLL);
rcc_wait_for_osc_ready(PLL);
/* Enable PLL oscillator and wait for it to stabilize. */
rcc_osc_on(PLL);
rcc_wait_for_osc_ready(PLL);
/* Configure flash settings. */
flash_set_ws(clock->flash_config);
/* Configure flash settings. */
flash_set_ws(clock->flash_config);
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
/* Wait for PLL clock to be selected. */
rcc_wait_for_sysclk_status(PLL);
/* Wait for PLL clock to be selected. */
rcc_wait_for_sysclk_status(PLL);
/* Set the peripheral clock frequencies used. */
rcc_ppre1_frequency = clock->apb1_frequency;
rcc_ppre2_frequency = clock->apb2_frequency;
/* Set the peripheral clock frequencies used. */
rcc_ppre1_frequency = clock->apb1_frequency;
rcc_ppre2_frequency = clock->apb2_frequency;
/* Disable internal high-speed oscillator. */
rcc_osc_off(HSI);
/* Disable internal high-speed oscillator. */
rcc_osc_off(HSI);
}
void rcc_backupdomain_reset(void)
{
/* Set the backup domain software reset. */
RCC_BDCR |= RCC_BDCR_BDRST;
/* Set the backup domain software reset. */
RCC_BDCR |= RCC_BDCR_BDRST;
/* Clear the backup domain software reset. */
RCC_BDCR &= ~RCC_BDCR_BDRST;
/* Clear the backup domain software reset. */
RCC_BDCR &= ~RCC_BDCR_BDRST;
}

56
lib/stm32/f4/rtc.c
View File

@@ -39,9 +39,10 @@ LGPL License Terms @ref lgpl_license
@warning You must unlock the registers before using this function
*/
void rtc_enable_wakeup_timer(void) {
RTC_CR |= RTC_CR_WUTE | (RTC_CR_OSEL_WAKEUP << RTC_CR_OSEL_SHIFT);
rtc_enable_wakeup_timer_interrupt();
void rtc_enable_wakeup_timer(void)
{
RTC_CR |= RTC_CR_WUTE | (RTC_CR_OSEL_WAKEUP << RTC_CR_OSEL_SHIFT);
rtc_enable_wakeup_timer_interrupt();
}
/*---------------------------------------------------------------------------*/
@@ -49,9 +50,10 @@ void rtc_enable_wakeup_timer(void) {
@warning You must unlock the registers before using this function
*/
void rtc_disable_wakeup_timer(void) {
RTC_CR &= ~RTC_CR_WUTE;
rtc_disable_wakeup_timer_interrupt();
void rtc_disable_wakeup_timer(void)
{
RTC_CR &= ~RTC_CR_WUTE;
rtc_disable_wakeup_timer_interrupt();
}
/*---------------------------------------------------------------------------*/
@@ -59,20 +61,23 @@ void rtc_disable_wakeup_timer(void) {
@warning You must unlock the registers before using this function
*/
void rtc_enable_wakeup_timer_interrupt(void) {
// FTFM:
// To enable the RTC Wakeup interrupt, the following sequence is required:
// 1. Configure and enable the EXTI Line 22 in interrupt mode and select the
// rising edge sensitivity.
exti_enable_request(EXTI22);
exti_set_trigger(EXTI22, EXTI_TRIGGER_RISING);
void rtc_enable_wakeup_timer_interrupt(void)
{
/* FTFM:
* To enable the RTC Wakeup interrupt, the following sequence is
* required:
* 1. Configure and enable the EXTI Line 22 in interrupt mode and
* select the rising edge sensitivity.
*/
exti_enable_request(EXTI22);
exti_set_trigger(EXTI22, EXTI_TRIGGER_RISING);
// 2. Configure and enable the RTC_WKUP IRQ channel in the NVIC.
nvic_enable_irq(NVIC_RTC_WKUP_IRQ);
nvic_set_priority(NVIC_RTC_WKUP_IRQ, 1);
/* 2. Configure and enable the RTC_WKUP IRQ channel in the NVIC. */
nvic_enable_irq(NVIC_RTC_WKUP_IRQ);
nvic_set_priority(NVIC_RTC_WKUP_IRQ, 1);
// 3. Configure the RTC to generate the RTC wakeup timer event.
RTC_CR |= RTC_CR_WUTIE; // Enable the interrupt
/* 3. Configure the RTC to generate the RTC wakeup timer event. */
RTC_CR |= RTC_CR_WUTIE; /* Enable the interrupt */
}
/*---------------------------------------------------------------------------*/
@@ -80,13 +85,14 @@ void rtc_enable_wakeup_timer_interrupt(void) {
@warning You must unlock the registers before using this function
*/
void rtc_disable_wakeup_timer_interrupt(void) {
// 1. Disable EXTI Line 22
exti_disable_request(EXTI22);
void rtc_disable_wakeup_timer_interrupt(void)
{
/* 1. Disable EXTI Line 22 */
exti_disable_request(EXTI22);
// 2. Disable RTC_WKUP IRQ channel in the NVIC.
nvic_disable_irq(NVIC_RTC_WKUP_IRQ);
/* 2. Disable RTC_WKUP IRQ channel in the NVIC. */
nvic_disable_irq(NVIC_RTC_WKUP_IRQ);
// 3. Disable RTC wakeup timer event.
RTC_CR &= ~RTC_CR_WUTIE;
/* 3. Disable RTC wakeup timer event. */
RTC_CR &= ~RTC_CR_WUTIE;
}