First coarse run to fix coding style in locm3.
Added --terse and --mailback options to the make stylecheck target. It also does continue even if it enounters a possible error. We decided on two exceptions from the linux kernel coding standard: - Empty wait while loops may end with ; on the same line. - All blocks after while, if, for have to be in brackets even if they only contain one statement. Otherwise it is easy to introduce an error. Checkpatch needs to be adapted to reflect those changes.
This commit is contained in:
Piotr Esden-Tempski
@@ -6,7 +6,8 @@
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2009 Federico Ruiz-Ugalde \<memeruiz at gmail dot com\>
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@author @htmlonly © @endhtmlonly 2009
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Federico Ruiz-Ugalde \<memeruiz at gmail dot com\>
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@author @htmlonly © @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
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@author @htmlonly © @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
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@@ -17,8 +18,8 @@ series of ARM Cortex Microcontrollers by ST Microelectronics.
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@note Full support for connection line devices is not yet provided.
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Clock settings and resets for many peripherals are given here rather than in the
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corresponding peripheral library.
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Clock settings and resets for many peripherals are given here rather than in
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the corresponding peripheral library.
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The library also provides a number of common configurations for the processor
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system clock. Not all possible configurations are included.
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@@ -57,10 +58,11 @@ u32 rcc_ppre1_frequency = 8000000;
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/** Default ppre2 peripheral clock frequency after reset. */
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u32 rcc_ppre2_frequency = 8000000;
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Clear the Oscillator Ready Interrupt Flag
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Clear the interrupt flag that was set when a clock oscillator became ready to use.
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Clear the interrupt flag that was set when a clock oscillator became ready to
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use.
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@param[in] osc enum ::osc_t. Oscillator ID
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*/
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@@ -92,7 +94,7 @@ void rcc_osc_ready_int_clear(osc_t osc)
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}
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Enable the Oscillator Ready Interrupt
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@param[in] osc enum ::osc_t. Oscillator ID
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@@ -125,7 +127,7 @@ void rcc_osc_ready_int_enable(osc_t osc)
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}
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Disable the Oscillator Ready Interrupt
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@param[in] osc enum ::osc_t. Oscillator ID
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@@ -158,7 +160,7 @@ void rcc_osc_ready_int_disable(osc_t osc)
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}
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Read the Oscillator Ready Interrupt Flag
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@param[in] osc enum ::osc_t. Oscillator ID
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@@ -194,7 +196,7 @@ int rcc_osc_ready_int_flag(osc_t osc)
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cm3_assert_not_reached();
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Clear the Clock Security System Interrupt Flag
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*/
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@@ -204,7 +206,7 @@ void rcc_css_int_clear(void)
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RCC_CIR |= RCC_CIR_CSSC;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Read the Clock Security System Interrupt Flag
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@returns int. Boolean value for flag set.
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@@ -215,7 +217,7 @@ int rcc_css_int_flag(void)
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return ((RCC_CIR & RCC_CIR_CSSF) != 0);
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Wait for Oscillator Ready.
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@param[in] osc enum ::osc_t. Oscillator ID
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@@ -248,16 +250,17 @@ void rcc_wait_for_osc_ready(osc_t osc)
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}
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Turn on an Oscillator.
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Enable an oscillator and power on. Each oscillator requires an amount of time to
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settle to a usable state. Refer to datasheets for time delay information. A status
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flag is available to indicate when the oscillator becomes ready (see
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Enable an oscillator and power on. Each oscillator requires an amount of time
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to settle to a usable state. Refer to datasheets for time delay information. A
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status flag is available to indicate when the oscillator becomes ready (see
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@ref rcc_osc_ready_int_flag and @ref rcc_wait_for_osc_ready).
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@note The LSE clock is in the backup domain and cannot be enabled until the
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backup domain write protection has been removed (see @ref pwr_disable_backup_domain_write_protect).
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backup domain write protection has been removed (see @ref
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pwr_disable_backup_domain_write_protect).
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@param[in] osc enum ::osc_t. Oscillator ID
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*/
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@@ -289,7 +292,7 @@ void rcc_osc_on(osc_t osc)
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}
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Turn off an Oscillator.
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Disable an oscillator and power off.
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@@ -330,7 +333,7 @@ void rcc_osc_off(osc_t osc)
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}
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Enable the Clock Security System.
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*/
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@@ -340,7 +343,7 @@ void rcc_css_enable(void)
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RCC_CR |= RCC_CR_CSSON;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Disable the Clock Security System.
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*/
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@@ -350,15 +353,16 @@ void rcc_css_disable(void)
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RCC_CR &= ~RCC_CR_CSSON;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Enable Bypass.
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Enable an external clock to bypass the internal clock (high speed and low speed
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clocks only). The external clock must be enabled (see @ref rcc_osc_on)
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and the internal clock must be disabled (see @ref rcc_osc_off) for this to have effect.
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clocks only). The external clock must be enabled (see @ref rcc_osc_on) and the
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internal clock must be disabled (see @ref rcc_osc_off) for this to have effect.
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@note The LSE clock is in the backup domain and cannot be bypassed until the
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backup domain write protection has been removed (see @ref pwr_disable_backup_domain_write_protect).
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backup domain write protection has been removed (see @ref
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pwr_disable_backup_domain_write_protect).
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@param[in] osc enum ::osc_t. Oscillator ID. Only HSE and LSE have effect.
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*/
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@@ -382,15 +386,16 @@ void rcc_osc_bypass_enable(osc_t osc)
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}
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Disable Bypass.
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Re-enable the internal clock (high speed and low speed clocks only). The internal
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clock must be disabled (see @ref rcc_osc_off) for this to have effect.
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Re-enable the internal clock (high speed and low speed clocks only). The
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internal clock must be disabled (see @ref rcc_osc_off) for this to have effect.
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@note The LSE clock is in the backup domain and cannot have bypass removed until the
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backup domain write protection has been removed (see @ref pwr_disable_backup_domain_write_protect)
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or the backup domain has been reset (see @ref rcc_backupdomain_reset).
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@note The LSE clock is in the backup domain and cannot have bypass removed
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until the backup domain write protection has been removed (see @ref
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pwr_disable_backup_domain_write_protect) or the backup domain has been reset
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(see @ref rcc_backupdomain_reset).
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@param[in] osc enum ::osc_t. Oscillator ID. Only HSE and LSE have effect.
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*/
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@@ -414,13 +419,13 @@ void rcc_osc_bypass_disable(osc_t osc)
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}
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Enable Peripheral Clocks.
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Enable the clock on particular peripherals. There are three registers
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involved, each one controlling the enabling of clocks associated with the AHB,
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APB1 and APB2 respectively. Several peripherals could be
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enabled simultaneously <em>only if they are controlled by the same register</em>.
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Enable the clock on particular peripherals. There are three registers involved,
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each one controlling the enabling of clocks associated with the AHB, APB1 and
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APB2 respectively. Several peripherals could be enabled simultaneously <em>only
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if they are controlled by the same register</em>.
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@param[in] *reg Unsigned int32. Pointer to a Clock Enable Register
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(either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
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@@ -435,17 +440,18 @@ void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en)
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*reg |= en;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Disable Peripheral Clocks.
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Enable the clock on particular peripherals. There are three registers
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involved, each one controlling the enabling of clocks associated with the AHB,
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APB1 and APB2 respectively. Several peripherals could be
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disabled simultaneously <em>only if they are controlled by the same register</em>.
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Enable the clock on particular peripherals. There are three registers involved,
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each one controlling the enabling of clocks associated with the AHB, APB1 and
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APB2 respectively. Several peripherals could be disabled simultaneously
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<em>only if they are controlled by the same register</em>.
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@param[in] *reg Unsigned int32. Pointer to a Clock Enable Register
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(either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
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@param[in] en Unsigned int32. Logical OR of all enables to be used for disabling.
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@param[in] en Unsigned int32. Logical OR of all enables to be used for
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disabling.
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@li If register is RCC_AHBER, from @ref rcc_ahbenr_en
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@li If register is RCC_APB1ENR, from @ref rcc_apb1enr_en
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@li If register is RCC_APB2ENR, from @ref rcc_apb2enr_en
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@@ -456,13 +462,13 @@ void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en)
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*reg &= ~en;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Reset Peripherals.
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Reset particular peripherals. There are three registers
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involved, each one controlling reset of peripherals associated with the AHB,
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APB1 and APB2 respectively. Several peripherals could be reset simultaneously
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<em>only if they are controlled by the same register</em>.
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Reset particular peripherals. There are three registers involved, each one
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controlling reset of peripherals associated with the AHB, APB1 and APB2
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respectively. Several peripherals could be reset simultaneously <em>only if
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they are controlled by the same register</em>.
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@param[in] *reg Unsigned int32. Pointer to a Reset Register
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(either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
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@@ -477,7 +483,7 @@ void rcc_peripheral_reset(volatile u32 *reg, u32 reset)
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*reg |= reset;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Remove Reset on Peripherals.
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Remove the reset on particular peripherals. There are three registers
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@@ -498,7 +504,7 @@ void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset)
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*reg &= ~clear_reset;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set the Source for the System Clock.
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@param[in] clk Unsigned int32. System Clock Selection @ref rcc_cfgr_scs
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@@ -513,7 +519,7 @@ void rcc_set_sysclk_source(u32 clk)
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RCC_CFGR = (reg32 | clk);
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set the PLL Multiplication Factor.
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@note This only has effect when the PLL is disabled.
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@@ -530,7 +536,7 @@ void rcc_set_pll_multiplication_factor(u32 mul)
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RCC_CFGR = (reg32 | (mul << 18));
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set the PLL2 Multiplication Factor.
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@note This only has effect when the PLL is disabled.
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@@ -547,7 +553,7 @@ void rcc_set_pll2_multiplication_factor(u32 mul)
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RCC_CFGR2 = (reg32 | (mul << 8));
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set the PLL3 Multiplication Factor.
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@note This only has effect when the PLL is disabled.
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@@ -564,7 +570,7 @@ void rcc_set_pll3_multiplication_factor(u32 mul)
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RCC_CFGR2 = (reg32 | (mul << 12));
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set the PLL Clock Source.
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@note This only has effect when the PLL is disabled.
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@@ -581,7 +587,7 @@ void rcc_set_pll_source(u32 pllsrc)
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RCC_CFGR = (reg32 | (pllsrc << 16));
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set the HSE Frequency Divider used as PLL Clock Source.
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@note This only has effect when the PLL is disabled.
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@@ -598,7 +604,7 @@ void rcc_set_pllxtpre(u32 pllxtpre)
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RCC_CFGR = (reg32 | (pllxtpre << 17));
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Setup the A/D Clock
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The ADC's have a common clock prescale setting.
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@@ -615,7 +621,7 @@ void rcc_set_adcpre(u32 adcpre)
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RCC_CFGR = (reg32 | (adcpre << 14));
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set the APB2 Prescale Factor.
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@param[in] ppre2 Unsigned int32. APB2 prescale factor @ref rcc_cfgr_apb2pre
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@@ -630,7 +636,7 @@ void rcc_set_ppre2(u32 ppre2)
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RCC_CFGR = (reg32 | (ppre2 << 11));
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set the APB1 Prescale Factor.
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@note The APB1 clock frequency must not exceed 36MHz.
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@@ -647,7 +653,7 @@ void rcc_set_ppre1(u32 ppre1)
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RCC_CFGR = (reg32 | (ppre1 << 8));
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set the AHB Prescale Factor.
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@param[in] hpre Unsigned int32. AHB prescale factor @ref rcc_cfgr_ahbpre
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@@ -662,7 +668,7 @@ void rcc_set_hpre(u32 hpre)
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RCC_CFGR = (reg32 | (hpre << 4));
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set the USB Prescale Factor.
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The prescale factor can be set to 1 (no prescale) for use when the PLL clock is
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@@ -712,7 +718,7 @@ void rcc_set_mco(u32 mcosrc)
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RCC_CFGR |= (reg32 | (mcosrc << 24));
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Get the System Clock Source.
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@returns Unsigned int32. System clock source:
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@@ -724,15 +730,15 @@ void rcc_set_mco(u32 mcosrc)
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u32 rcc_system_clock_source(void)
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{
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/* Return the clock source which is used as system clock. */
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return ((RCC_CFGR & 0x000c) >> 2);
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return (RCC_CFGR & 0x000c) >> 2;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/*
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* These functions are setting up the whole clock system for the most common
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* input clock and output clock configurations.
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*/
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Set System Clock PLL at 64MHz from HSI
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*/
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@@ -750,10 +756,10 @@ void rcc_clock_setup_in_hsi_out_64mhz(void)
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* Set prescalers for AHB, ADC, ABP1, ABP2.
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* Do this before touching the PLL (TODO: why?).
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*/
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rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 64MHz Max. 72MHz */
|
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rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 8MHz Max. 14MHz */
|
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rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 32MHz Max. 36MHz */
|
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rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 64MHz Max. 72MHz */
|
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rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 64MHz Max. 72MHz */
|
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rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 8MHz Max. 14MHz */
|
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rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 32MHz Max. 36MHz */
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rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 64MHz Max. 72MHz */
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/*
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* Sysclk is running with 64MHz -> 2 waitstates.
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@@ -784,7 +790,7 @@ void rcc_clock_setup_in_hsi_out_64mhz(void)
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rcc_ppre2_frequency = 64000000;
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}
|
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|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief RCC Set System Clock PLL at 48MHz from HSI
|
||||
|
||||
*/
|
||||
@@ -802,11 +808,11 @@ void rcc_clock_setup_in_hsi_out_48mhz(void)
|
||||
* Set prescalers for AHB, ADC, ABP1, ABP2.
|
||||
* Do this before touching the PLL (TODO: why?).
|
||||
*/
|
||||
rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 48MHz Max. 72MHz */
|
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rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 6MHz Max. 14MHz */
|
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rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 24MHz Max. 36MHz */
|
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rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 48MHz Max. 72MHz */
|
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rcc_set_usbpre(RCC_CFGR_USBPRE_PLL_CLK_NODIV); /* Set. 48MHz Max. 48MHz */
|
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rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /*Set.48MHz Max.72MHz */
|
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rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /*Set. 6MHz Max.14MHz */
|
||||
rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /*Set.24MHz Max.36MHz */
|
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rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /*Set.48MHz Max.72MHz */
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||||
rcc_set_usbpre(RCC_CFGR_USBPRE_PLL_CLK_NODIV); /*Set.48MHz Max.48MHz */
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||||
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||||
/*
|
||||
* Sysclk runs with 48MHz -> 1 waitstates.
|
||||
@@ -837,12 +843,13 @@ void rcc_clock_setup_in_hsi_out_48mhz(void)
|
||||
rcc_ppre2_frequency = 48000000;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief RCC Set System Clock PLL at 24MHz from HSI
|
||||
|
||||
*/
|
||||
|
||||
void rcc_clock_setup_in_hsi_out_24mhz(void) {
|
||||
void rcc_clock_setup_in_hsi_out_24mhz(void)
|
||||
{
|
||||
/* Enable internal high-speed oscillator. */
|
||||
rcc_osc_on(HSI);
|
||||
rcc_wait_for_osc_ready(HSI);
|
||||
@@ -888,7 +895,7 @@ void rcc_clock_setup_in_hsi_out_24mhz(void) {
|
||||
rcc_ppre2_frequency = 24000000;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief RCC Set System Clock PLL at 24MHz from HSE at 8MHz
|
||||
|
||||
*/
|
||||
@@ -911,10 +918,10 @@ void rcc_clock_setup_in_hse_8mhz_out_24mhz(void)
|
||||
* Set prescalers for AHB, ADC, ABP1, ABP2.
|
||||
* Do this before touching the PLL (TODO: why?).
|
||||
*/
|
||||
rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 24MHz Max. 72MHz */
|
||||
rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV2); /* Set. 12MHz Max. 14MHz */
|
||||
rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_NODIV); /* Set. 24MHz Max. 36MHz */
|
||||
rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 24MHz Max. 72MHz */
|
||||
rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 24MHz Max. 72MHz */
|
||||
rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV2); /* Set. 12MHz Max. 14MHz */
|
||||
rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_NODIV); /* Set. 24MHz Max. 36MHz */
|
||||
rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 24MHz Max. 72MHz */
|
||||
|
||||
/*
|
||||
* Sysclk runs with 24MHz -> 0 waitstates.
|
||||
@@ -951,7 +958,7 @@ void rcc_clock_setup_in_hse_8mhz_out_24mhz(void)
|
||||
rcc_ppre2_frequency = 24000000;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief RCC Set System Clock PLL at 72MHz from HSE at 8MHz
|
||||
|
||||
*/
|
||||
@@ -974,10 +981,10 @@ void rcc_clock_setup_in_hse_8mhz_out_72mhz(void)
|
||||
* Set prescalers for AHB, ADC, ABP1, ABP2.
|
||||
* Do this before touching the PLL (TODO: why?).
|
||||
*/
|
||||
rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */
|
||||
rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 9MHz Max. 14MHz */
|
||||
rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */
|
||||
rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */
|
||||
rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */
|
||||
rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 9MHz Max. 14MHz */
|
||||
rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */
|
||||
rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */
|
||||
|
||||
/*
|
||||
* Sysclk runs with 72MHz -> 2 waitstates.
|
||||
@@ -1014,7 +1021,7 @@ void rcc_clock_setup_in_hse_8mhz_out_72mhz(void)
|
||||
rcc_ppre2_frequency = 72000000;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief RCC Set System Clock PLL at 24MHz from HSE at 12MHz
|
||||
|
||||
*/
|
||||
@@ -1037,10 +1044,10 @@ void rcc_clock_setup_in_hse_12mhz_out_72mhz(void)
|
||||
* Set prescalers for AHB, ADC, ABP1, ABP2.
|
||||
* Do this before touching the PLL (TODO: why?).
|
||||
*/
|
||||
rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */
|
||||
rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */
|
||||
rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */
|
||||
rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */
|
||||
rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */
|
||||
rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */
|
||||
rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */
|
||||
rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */
|
||||
|
||||
/*
|
||||
* Sysclk runs with 72MHz -> 2 waitstates.
|
||||
@@ -1077,7 +1084,7 @@ void rcc_clock_setup_in_hse_12mhz_out_72mhz(void)
|
||||
rcc_ppre2_frequency = 72000000;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief RCC Set System Clock PLL at 24MHz from HSE at 16MHz
|
||||
|
||||
*/
|
||||
@@ -1100,10 +1107,10 @@ void rcc_clock_setup_in_hse_16mhz_out_72mhz(void)
|
||||
* Set prescalers for AHB, ADC, ABP1, ABP2.
|
||||
* Do this before touching the PLL (TODO: why?).
|
||||
*/
|
||||
rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */
|
||||
rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */
|
||||
rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */
|
||||
rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */
|
||||
rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */
|
||||
rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */
|
||||
rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */
|
||||
rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */
|
||||
|
||||
/*
|
||||
* Sysclk runs with 72MHz -> 2 waitstates.
|
||||
@@ -1140,7 +1147,7 @@ void rcc_clock_setup_in_hse_16mhz_out_72mhz(void)
|
||||
rcc_ppre2_frequency = 72000000;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief RCC Set System Clock PLL at 72MHz from HSE at 25MHz
|
||||
|
||||
*/
|
||||
@@ -1164,10 +1171,10 @@ void rcc_clock_setup_in_hse_25mhz_out_72mhz(void)
|
||||
* Set prescalers for AHB, ADC, ABP1, ABP2.
|
||||
* Do this before touching the PLL (TODO: why?).
|
||||
*/
|
||||
rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */
|
||||
rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */
|
||||
rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */
|
||||
rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */
|
||||
rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */
|
||||
rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */
|
||||
rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */
|
||||
rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */
|
||||
|
||||
/* Set pll2 prediv and multiplier */
|
||||
rcc_set_prediv2(RCC_CFGR2_PREDIV2_DIV5);
|
||||
@@ -1197,7 +1204,7 @@ void rcc_clock_setup_in_hse_25mhz_out_72mhz(void)
|
||||
rcc_ppre2_frequency = 72000000;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief RCC Reset the backup domain
|
||||
|
||||
The backup domain register is reset to disable all controls.
|
||||
|
||||
Reference in New Issue
Block a user