First coarse run to fix coding style in locm3.
Added --terse and --mailback options to the make stylecheck target. It also does continue even if it enounters a possible error. We decided on two exceptions from the linux kernel coding standard: - Empty wait while loops may end with ; on the same line. - All blocks after while, if, for have to be in brackets even if they only contain one statement. Otherwise it is easy to introduce an error. Checkpatch needs to be adapted to reflect those changes.
This commit is contained in:
Piotr Esden-Tempski
@@ -1,7 +1,9 @@
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/** @addtogroup spi_file
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@author @htmlonly © @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
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@author @htmlonly © @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
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@author @htmlonly © @endhtmlonly 2009
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Uwe Hermann <uwe@hermann-uwe.de>
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@author @htmlonly © @endhtmlonly 2012
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Ken Sarkies <ksarkies@internode.on.net>
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Devices can have up to three SPI peripherals. The common 4-wire full-duplex
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mode of operation is supported, along with 3-wire variants using unidirectional
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@@ -18,8 +20,8 @@ Example: 1Mbps, positive clock polarity, leading edge trigger, 8-bit words,
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LSB first.
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@code
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spi_init_master(SPI1, 1000000, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE,
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SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT,
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SPI_CR1_LSBFIRST);
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SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT,
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SPI_CR1_LSBFIRST);
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spi_write(SPI1, 0x55); // 8-bit write
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spi_write(SPI1, 0xaa88); // 16-bit write
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reg8 = spi_read(SPI1); // 8-bit read
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@@ -67,13 +69,14 @@ LSB first.
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/**@{*/
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Reset.
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The SPI peripheral and all its associated configuration registers are placed in the
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reset condition. The reset is effected via the RCC peripheral reset system.
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The SPI peripheral and all its associated configuration registers are placed in
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the reset condition. The reset is effected via the RCC peripheral reset system.
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@param[in] spi_peripheral Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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@param[in] spi_peripheral Unsigned int32. SPI peripheral identifier @ref
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spi_reg_base.
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*/
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void spi_reset(u32 spi_peripheral)
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@@ -96,7 +99,7 @@ void spi_reset(u32 spi_peripheral)
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}
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief Configure the SPI as Master.
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The SPI peripheral is configured as a master with communication parameters
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@@ -111,7 +114,8 @@ These must be controlled separately.
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@param[in] cpol Unsigned int32. Clock polarity @ref spi_cpol.
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@param[in] cpha Unsigned int32. Clock Phase @ref spi_cpha.
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@param[in] dff Unsigned int32. Data frame format 8/16 bits @ref spi_dff.
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@param[in] lsbfirst Unsigned int32. Frame format lsb/msb first @ref spi_lsbfirst.
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@param[in] lsbfirst Unsigned int32. Frame format lsb/msb first @ref
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spi_lsbfirst.
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@returns int. Error code.
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*/
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@@ -138,7 +142,7 @@ int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst)
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}
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/* TODO: Error handling? */
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Enable.
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The SPI peripheral is enabled.
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@@ -154,7 +158,7 @@ void spi_enable(u32 spi)
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}
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/* TODO: Error handling? */
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Disable.
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The SPI peripheral is disabled.
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@@ -171,7 +175,7 @@ void spi_disable(u32 spi)
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SPI_CR1(spi) = reg32;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Clean Disable.
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Disable the SPI peripheral according to the procedure in section 23.3.8 of the
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@@ -185,25 +189,22 @@ prevents the BSY flag from becoming unreliable.
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u16 spi_clean_disable(u32 spi)
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{
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/* Wait to receive last data */
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while (!(SPI_SR(spi) & SPI_SR_RXNE))
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;
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while (!(SPI_SR(spi) & SPI_SR_RXNE));
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u16 data = SPI_DR(spi);
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/* Wait to transmit last data */
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while (!(SPI_SR(spi) & SPI_SR_TXE))
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;
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while (!(SPI_SR(spi) & SPI_SR_TXE));
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/* Wait until not busy */
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while (SPI_SR(spi) & SPI_SR_BSY)
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;
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while (SPI_SR(spi) & SPI_SR_BSY);
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SPI_CR1(spi) &= ~SPI_CR1_SPE;
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return data;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Data Write.
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Data is written to the SPI interface.
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@@ -218,10 +219,11 @@ void spi_write(u32 spi, u16 data)
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SPI_DR(spi) = data;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Data Write with Blocking.
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Data is written to the SPI interface after the previous write transfer has finished.
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Data is written to the SPI interface after the previous write transfer has
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finished.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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@param[in] data Unsigned int16. 8 or 16 bit data to be written.
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@@ -230,14 +232,13 @@ Data is written to the SPI interface after the previous write transfer has finis
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void spi_send(u32 spi, u16 data)
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{
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/* Wait for transfer finished. */
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while (!(SPI_SR(spi) & SPI_SR_TXE))
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;
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while (!(SPI_SR(spi) & SPI_SR_TXE));
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/* Write data (8 or 16 bits, depending on DFF) into DR. */
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SPI_DR(spi) = data;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Data Read.
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Data is read from the SPI interface after the incoming transfer has finished.
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@@ -249,18 +250,17 @@ Data is read from the SPI interface after the incoming transfer has finished.
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u16 spi_read(u32 spi)
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{
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/* Wait for transfer finished. */
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while (!(SPI_SR(spi) & SPI_SR_RXNE))
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;
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while (!(SPI_SR(spi) & SPI_SR_RXNE));
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/* Read the data (8 or 16 bits, depending on DFF bit) from DR. */
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return SPI_DR(spi);
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Data Write and Read Exchange.
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Data is written to the SPI interface, then a read is done after the incoming transfer
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has finished.
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Data is written to the SPI interface, then a read is done after the incoming
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transfer has finished.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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@param[in] data Unsigned int16. 8 or 16 bit data to be written.
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@@ -272,14 +272,13 @@ u16 spi_xfer(u32 spi, u16 data)
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spi_write(spi, data);
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/* Wait for transfer finished. */
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while (!(SPI_SR(spi) & SPI_SR_RXNE))
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;
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while (!(SPI_SR(spi) & SPI_SR_RXNE));
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/* Read the data (8 or 16 bits, depending on DFF bit) from DR. */
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return SPI_DR(spi);
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Set Bidirectional Simplex Mode.
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The SPI peripheral is set for bidirectional transfers in two-wire simplex mode
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@@ -293,12 +292,12 @@ void spi_set_bidirectional_mode(u32 spi)
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SPI_CR1(spi) |= SPI_CR1_BIDIMODE;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Set Unidirectional Mode.
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The SPI peripheral is set for unidirectional transfers. This is used in full duplex
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mode or when the SPI is placed in two-wire simplex mode that uses a clock wire and a
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unidirectional data wire.
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The SPI peripheral is set for unidirectional transfers. This is used in full
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duplex mode or when the SPI is placed in two-wire simplex mode that uses a
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clock wire and a unidirectional data wire.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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@@ -308,11 +307,12 @@ void spi_set_unidirectional_mode(u32 spi)
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SPI_CR1(spi) &= ~SPI_CR1_BIDIMODE;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Set Bidirectional Simplex Receive Only Mode.
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The SPI peripheral is set for bidirectional transfers in two-wire simplex mode
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(using a clock wire and a bidirectional data wire), and is placed in a receive state.
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(using a clock wire and a bidirectional data wire), and is placed in a receive
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state.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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@@ -323,11 +323,12 @@ void spi_set_bidirectional_receive_only_mode(u32 spi)
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SPI_CR1(spi) &= ~SPI_CR1_BIDIOE;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Set Bidirectional Simplex Receive Only Mode.
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The SPI peripheral is set for bidirectional transfers in two-wire simplex mode
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(using a clock wire and a bidirectional data wire), and is placed in a transmit state.
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(using a clock wire and a bidirectional data wire), and is placed in a transmit
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state.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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@@ -338,7 +339,7 @@ void spi_set_bidirectional_transmit_only_mode(u32 spi)
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SPI_CR1(spi) |= SPI_CR1_BIDIOE;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Enable the CRC.
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The SPI peripheral is set to use a CRC field for transmit and receive.
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@@ -351,7 +352,7 @@ void spi_enable_crc(u32 spi)
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SPI_CR1(spi) |= SPI_CR1_CRCEN;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Disable the CRC.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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@@ -362,7 +363,7 @@ void spi_disable_crc(u32 spi)
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SPI_CR1(spi) &= ~SPI_CR1_CRCEN;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Next Transmit is a Data Word
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The next transmission to take place is a data word from the transmit buffer.
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@@ -377,7 +378,7 @@ void spi_set_next_tx_from_buffer(u32 spi)
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SPI_CR1(spi) &= ~SPI_CR1_CRCNEXT;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Next Transmit is a CRC Word
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The next transmission to take place is a crc word from the hardware crc unit.
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@@ -392,7 +393,7 @@ void spi_set_next_tx_from_crc(u32 spi)
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SPI_CR1(spi) |= SPI_CR1_CRCNEXT;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Set Data Frame Format to 8 bits
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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@@ -403,7 +404,7 @@ void spi_set_dff_8bit(u32 spi)
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SPI_CR1(spi) &= ~SPI_CR1_DFF;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Set Data Frame Format to 16 bits
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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@@ -414,7 +415,7 @@ void spi_set_dff_16bit(u32 spi)
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SPI_CR1(spi) |= SPI_CR1_DFF;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Set Full Duplex (3-wire) Mode
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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@@ -425,8 +426,9 @@ void spi_set_full_duplex_mode(u32 spi)
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SPI_CR1(spi) &= ~SPI_CR1_RXONLY;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief SPI Set Receive Only Mode for Simplex (2-wire) Unidirectional Transfers
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Set Receive Only Mode for Simplex (2-wire) Unidirectional
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Transfers
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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@@ -436,7 +438,7 @@ void spi_set_receive_only_mode(u32 spi)
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SPI_CR1(spi) |= SPI_CR1_RXONLY;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Enable Slave Management by Hardware
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In slave mode the NSS hardware input is used as a select enable for the slave.
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@@ -449,7 +451,7 @@ void spi_disable_software_slave_management(u32 spi)
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SPI_CR1(spi) &= ~SPI_CR1_SSM;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Enable Slave Management by Software
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In slave mode the NSS hardware input is replaced by an internal software
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@@ -463,13 +465,14 @@ void spi_enable_software_slave_management(u32 spi)
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SPI_CR1(spi) |= SPI_CR1_SSM;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Set the Software NSS Signal High
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In slave mode, and only when software slave management is used, this replaces
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the NSS signal with a slave select enable signal.
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@todo these should perhaps be combined with an SSM enable as it is meaningless otherwise
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@todo these should perhaps be combined with an SSM enable as it is meaningless
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otherwise
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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@@ -479,7 +482,7 @@ void spi_set_nss_high(u32 spi)
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SPI_CR1(spi) |= SPI_CR1_SSI;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Set the Software NSS Signal Low
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In slave mode, and only when software slave management is used, this replaces
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@@ -493,7 +496,7 @@ void spi_set_nss_low(u32 spi)
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SPI_CR1(spi) &= ~SPI_CR1_SSI;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Set to Send LSB First
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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@@ -504,7 +507,7 @@ void spi_send_lsb_first(u32 spi)
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SPI_CR1(spi) |= SPI_CR1_LSBFIRST;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Set to Send MSB First
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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@@ -515,10 +518,11 @@ void spi_send_msb_first(u32 spi)
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SPI_CR1(spi) &= ~SPI_CR1_LSBFIRST;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Set the Baudrate Prescaler
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@todo Why is this specification different to the spi_init_master baudrate values?
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@todo Why is this specification different to the spi_init_master baudrate
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values?
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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@param[in] baudrate Unsigned int8. Baudrate prescale value @ref spi_br_pre.
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@@ -528,15 +532,16 @@ void spi_set_baudrate_prescaler(u32 spi, u8 baudrate)
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{
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u32 reg32;
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if (baudrate > 7)
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if (baudrate > 7) {
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return;
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}
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reg32 = (SPI_CR1(spi) & 0xffc7); /* Clear bits [5:3]. */
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reg32 |= (baudrate << 3);
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SPI_CR1(spi) = reg32;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Set to Master Mode
|
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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@@ -547,7 +552,7 @@ void spi_set_master_mode(u32 spi)
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SPI_CR1(spi) |= SPI_CR1_MSTR;
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}
|
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/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
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/** @brief SPI Set to Slave Mode
|
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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@@ -558,7 +563,7 @@ void spi_set_slave_mode(u32 spi)
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SPI_CR1(spi) &= ~SPI_CR1_MSTR;
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||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief SPI Set the Clock Polarity to High when Idle
|
||||
|
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
||||
@@ -569,7 +574,7 @@ void spi_set_clock_polarity_1(u32 spi)
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SPI_CR1(spi) |= SPI_CR1_CPOL;
|
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}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief SPI Set the Clock Polarity to Low when Idle
|
||||
|
||||
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
||||
@@ -580,7 +585,7 @@ void spi_set_clock_polarity_0(u32 spi)
|
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SPI_CR1(spi) &= ~SPI_CR1_CPOL;
|
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}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief SPI Set the Clock Phase to Capture on Trailing Edge
|
||||
|
||||
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
||||
@@ -591,7 +596,7 @@ void spi_set_clock_phase_1(u32 spi)
|
||||
SPI_CR1(spi) |= SPI_CR1_CPHA;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief SPI Set the Clock Phase to Capture on Leading Edge
|
||||
|
||||
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
||||
@@ -602,7 +607,7 @@ void spi_set_clock_phase_0(u32 spi)
|
||||
SPI_CR1(spi) &= ~SPI_CR1_CPHA;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief SPI Enable the Transmit Buffer Empty Interrupt
|
||||
|
||||
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
||||
@@ -613,7 +618,7 @@ void spi_enable_tx_buffer_empty_interrupt(u32 spi)
|
||||
SPI_CR2(spi) |= SPI_CR2_TXEIE;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief SPI Disable the Transmit Buffer Empty Interrupt
|
||||
|
||||
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
||||
@@ -624,7 +629,7 @@ void spi_disable_tx_buffer_empty_interrupt(u32 spi)
|
||||
SPI_CR2(spi) &= ~SPI_CR2_TXEIE;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief SPI Enable the Receive Buffer Ready Interrupt
|
||||
|
||||
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
||||
@@ -635,7 +640,7 @@ void spi_enable_rx_buffer_not_empty_interrupt(u32 spi)
|
||||
SPI_CR2(spi) |= SPI_CR2_RXNEIE;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief SPI Disable the Receive Buffer Ready Interrupt
|
||||
|
||||
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
||||
@@ -646,7 +651,7 @@ void spi_disable_rx_buffer_not_empty_interrupt(u32 spi)
|
||||
SPI_CR2(spi) &= ~SPI_CR2_RXNEIE;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief SPI Enable the Error Interrupt
|
||||
|
||||
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
||||
@@ -657,7 +662,7 @@ void spi_enable_error_interrupt(u32 spi)
|
||||
SPI_CR2(spi) |= SPI_CR2_ERRIE;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief SPI Disable the Error Interrupt
|
||||
|
||||
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
||||
@@ -668,7 +673,7 @@ void spi_disable_error_interrupt(u32 spi)
|
||||
SPI_CR2(spi) &= ~SPI_CR2_ERRIE;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief SPI Set the NSS Pin as an Output
|
||||
|
||||
Normally used in master mode to allows the master to place all devices on the
|
||||
@@ -682,7 +687,7 @@ void spi_enable_ss_output(u32 spi)
|
||||
SPI_CR2(spi) |= SPI_CR2_SSOE;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief SPI Set the NSS Pin as an Input
|
||||
|
||||
In master mode this allows the master to sense the presence of other masters. If
|
||||
@@ -697,7 +702,7 @@ void spi_disable_ss_output(u32 spi)
|
||||
SPI_CR2(spi) &= ~SPI_CR2_SSOE;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief SPI Enable Transmit Transfers via DMA
|
||||
|
||||
This allows transmissions to proceed unattended using DMA to move data to the
|
||||
@@ -712,7 +717,7 @@ void spi_enable_tx_dma(u32 spi)
|
||||
SPI_CR2(spi) |= SPI_CR2_TXDMAEN;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief SPI Disable Transmit Transfers via DMA
|
||||
|
||||
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
||||
@@ -723,12 +728,12 @@ void spi_disable_tx_dma(u32 spi)
|
||||
SPI_CR2(spi) &= ~SPI_CR2_TXDMAEN;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief SPI Enable Receive Transfers via DMA
|
||||
|
||||
This allows received data streams to proceed unattended using DMA to move data from
|
||||
the receive buffer as data becomes available. The DMA channels provided for each
|
||||
SPI peripheral are given in the Technical Manual DMA section.
|
||||
This allows received data streams to proceed unattended using DMA to move data
|
||||
from the receive buffer as data becomes available. The DMA channels provided
|
||||
for each SPI peripheral are given in the Technical Manual DMA section.
|
||||
|
||||
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
||||
*/
|
||||
@@ -738,7 +743,7 @@ void spi_enable_rx_dma(u32 spi)
|
||||
SPI_CR2(spi) |= SPI_CR2_RXDMAEN;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief SPI Disable Receive Transfers via DMA
|
||||
|
||||
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
||||
|
||||
Reference in New Issue
Block a user