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First coarse run to fix coding style in locm3.

Browse Source 
Added --terse and --mailback options to the make stylecheck target. It
also does continue even if it enounters a possible error.

We decided on two exceptions from the linux kernel coding standard:
- Empty wait while loops may end with ; on the same line.
- All blocks after while, if, for have to be in brackets even if they
  only contain one statement. Otherwise it is easy to introduce an
  error.

Checkpatch needs to be adapted to reflect those changes.
This commit is contained in:
Piotr Esden-Tempski
2013-06-12 17:44:07 -07:00
parent 48e0f3326b
commit 7df63fcae0
147 changed files with 3323 additions and 2565 deletions
Download Patch File Download Diff File Expand all files Collapse all files

62
lib/stm32/common/rtc_common_bcd.c
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@@ -33,7 +33,8 @@
This sets the RTC synchronous and asynchronous prescalars.
*/
void rtc_set_prescaler(u32 sync, u32 async) {
void rtc_set_prescaler(u32 sync, u32 async)
{
/*
* Even if only one of the two fields needs to be changed,
* 2 separate write accesses must be performed to the RTC_PRER register.
@@ -48,16 +49,16 @@ void rtc_set_prescaler(u32 sync, u32 async) {
Time and Date are accessed through shadow registers which must be synchronized
*/
void rtc_wait_for_synchro(void) {
void rtc_wait_for_synchro(void)
{
/* Unlock RTC registers */
RTC_WPR = 0xca;
RTC_WPR = 0x53;
RTC_ISR &= ~(RTC_ISR_RSF);
while (!(RTC_ISR & RTC_ISR_RSF)) {
;
}
while (!(RTC_ISR & RTC_ISR_RSF));
/* disable write protection again */
RTC_WPR = 0xff;
}
@@ -66,7 +67,8 @@ void rtc_wait_for_synchro(void) {
/** @brief Unlock write access to the RTC registers
*/
void rtc_unlock(void) {
void rtc_unlock(void)
{
RTC_WPR = 0xca;
RTC_WPR = 0x53;
}
@@ -75,7 +77,8 @@ void rtc_unlock(void) {
/** @brief Lock write access to the RTC registers
*/
void rtc_lock(void) {
void rtc_lock(void)
{
RTC_WPR = 0xff;
}
@@ -83,31 +86,38 @@ void rtc_lock(void) {
/** @brief Sets the wakeup time auto-reload value
*/
void rtc_set_wakeup_time(u16 wkup_time, u8 rtc_cr_wucksel) {
// FTFM:
// The following sequence is required to configure or change the wakeup timer
// auto-reload value (WUT[15:0] in RTC_WUTR):
// 1. Clear WUTE in RTC_CR to disable the wakeup timer.
RTC_CR &= ~RTC_CR_WUTE;
// 2. Poll WUTWF until it is set in RTC_ISR to make sure the access to wakeup
// auto-reload counter and to WUCKSEL[2:0] bits is allowed. It takes around 2
// RTCCLK clock cycles (due to clock synchronization).
while (!((RTC_ISR) & (RTC_ISR_WUTWF))) { }
// 3. Program the wakeup auto-reload value WUT[15:0], and the wakeup clock
// selection (WUCKSEL[2:0] bits in RTC_CR).Set WUTE in RTC_CR to enable the
// timer again. The wakeup timer restarts down-counting.
RTC_WUTR = wkup_time;
RTC_CR |= (rtc_cr_wucksel << RTC_CR_WUCLKSEL_SHIFT);
RTC_CR |= RTC_CR_WUTE;
void rtc_set_wakeup_time(u16 wkup_time, u8 rtc_cr_wucksel)
{
/* FTFM:
* The following sequence is required to configure or change the wakeup
* timer auto-reload value (WUT[15:0] in RTC_WUTR):
* 1. Clear WUTE in RTC_CR to disable the wakeup timer.
*/
RTC_CR &= ~RTC_CR_WUTE;
/* 2. Poll WUTWF until it is set in RTC_ISR to make sure the access to
* wakeup auto-reload counter and to WUCKSEL[2:0] bits is allowed.
* It takes around 2 RTCCLK clock cycles (due to clock
* synchronization).
*/
while (!((RTC_ISR) & (RTC_ISR_WUTWF)));
/* 3. Program the wakeup auto-reload value WUT[15:0], and the wakeup
* clock selection (WUCKSEL[2:0] bits in RTC_CR).Set WUTE in RTC_CR
* to enable the timer again. The wakeup timer restarts
* down-counting.
*/
RTC_WUTR = wkup_time;
RTC_CR |= (rtc_cr_wucksel << RTC_CR_WUCLKSEL_SHIFT);
RTC_CR |= RTC_CR_WUTE;
}
/*---------------------------------------------------------------------------*/
/** @brief Clears the wakeup flag
@details This function should be called first in the rtc_wkup_isr()
@details This function should be called first in the rtc_wkup_isr()
*/
void rtc_clear_wakeup_flag(void) {
RTC_ISR &= ~RTC_ISR_WUTF;
void rtc_clear_wakeup_flag(void)
{
RTC_ISR &= ~RTC_ISR_WUTF;
}
/**@}*/