First coarse run to fix coding style in locm3.
Added --terse and --mailback options to the make stylecheck target. It also does continue even if it enounters a possible error. We decided on two exceptions from the linux kernel coding standard: - Empty wait while loops may end with ; on the same line. - All blocks after while, if, for have to be in brackets even if they only contain one statement. Otherwise it is easy to introduce an error. Checkpatch needs to be adapted to reflect those changes.
This commit is contained in:
Piotr Esden-Tempski
@@ -1,6 +1,7 @@
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/** @addtogroup dma_file
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@author @htmlonly © @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
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@author @htmlonly © @endhtmlonly 2012
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Ken Sarkies <ksarkies@internode.on.net>
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This library supports the DMA Control System in the STM32F2 and STM32F4
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series of ARM Cortex Microcontrollers by ST Microelectronics.
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@@ -47,7 +48,7 @@ LGPL License Terms @ref lgpl_license
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#include <libopencm3/stm32/dma.h>
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Reset
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The specified stream is disabled and configuration registers are cleared.
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@@ -72,17 +73,14 @@ void dma_stream_reset(u32 dma, u8 stream)
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DMA_SFCR(dma, stream) = 0x21;
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/* Reset all stream interrupt flags using the interrupt flag clear register. */
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u32 mask = DMA_ISR_MASK(stream);
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if (stream < 4)
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{
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if (stream < 4) {
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DMA_LIFCR(dma) |= mask;
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}
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else
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{
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} else {
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DMA_HIFCR(dma) |= mask;
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}
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}
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Clear Interrupt Flag
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The interrupt flag for the stream is cleared. More than one interrupt for the
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@@ -90,25 +88,25 @@ same stream may be cleared by using the bitwise OR of the interrupt flags.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] stream unsigned int8. Stream number: @ref dma_st_number
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@param[in] interrupts unsigned int32. Bitwise OR of interrupt numbers: @ref dma_if_offset
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@param[in] interrupts unsigned int32. Bitwise OR of interrupt numbers: @ref
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dma_if_offset
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*/
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void dma_clear_interrupt_flags(u32 dma, u8 stream, u32 interrupts)
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{
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/* Get offset to interrupt flag location in stream field */
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/* Get offset to interrupt flag location in stream field */
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u32 flags = (interrupts << DMA_ISR_OFFSET(stream));
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/* First four streams are in low register. Flag clear must be set then reset. */
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if (stream < 4)
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{
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/* First four streams are in low register. Flag clear must be set then
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* reset.
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*/
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if (stream < 4) {
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DMA_LIFCR(dma) = flags;
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}
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else
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{
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} else {
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DMA_HIFCR(dma) = flags;
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}
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Read Interrupt Flag
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The interrupt flag for the stream is returned.
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@@ -121,15 +119,19 @@ The interrupt flag for the stream is returned.
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bool dma_get_interrupt_flag(u32 dma, u8 stream, u32 interrupt)
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{
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/* get offset to interrupt flag location in stream field.
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Assumes stream and interrupt parameters are integers */
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/* get offset to interrupt flag location in stream field. Assumes
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* stream and interrupt parameters are integers.
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*/
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u32 flag = (interrupt << DMA_ISR_OFFSET(stream));
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/* First four streams are in low register */
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if (stream < 4) return ((DMA_LISR(dma) & flag) > 0);
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else return ((DMA_HISR(dma) & flag) > 0);
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/* First four streams are in low register */
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if (stream < 4) {
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return ((DMA_LISR(dma) & flag) > 0);
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} else {
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return ((DMA_HISR(dma) & flag) > 0);
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}
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Enable Transfer Direction
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Set peripheral to memory, memory to peripheral or memory to memory. If memory
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@@ -146,16 +148,18 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
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void dma_set_transfer_mode(u32 dma, u8 stream, u32 direction)
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{
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u32 reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_DIR_MASK);
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/* Disable circular and double buffer modes if memory to memory transfers
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are in effect (Direct Mode is automatically disabled by hardware) */
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if (direction == DMA_SxCR_DIR_MEM_TO_MEM)
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{
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/* Disable circular and double buffer modes if memory to memory
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* transfers are in effect. (Direct Mode is automatically disabled by
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* hardware)
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*/
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if (direction == DMA_SxCR_DIR_MEM_TO_MEM) {
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reg32 &= ~(DMA_SxCR_CIRC | DMA_SxCR_DBM);
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}
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DMA_SCR(dma, stream) = (reg32 | direction);
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Set Priority
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Stream Priority has four levels: low to very high. This has precedence over the
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@@ -175,7 +179,7 @@ void dma_set_priority(u32 dma, u8 stream, u32 prio)
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DMA_SCR(dma, stream) |= prio;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Set Memory Word Width
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Set the memory word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for
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@@ -190,23 +194,23 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
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void dma_set_memory_size(u32 dma, u8 stream, u32 mem_size)
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{
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DMA_SCR(dma, stream) &= ~(DMA_SxCR_MSIZE_MASK);
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DMA_SCR(dma, stream) |= mem_size;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Set Peripheral Word Width
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Set the peripheral word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for
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alignment information if the source and destination widths do not match, or
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Set the peripheral word width 8 bits, 16 bits, or 32 bits. Refer to datasheet
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for alignment information if the source and destination widths do not match, or
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if the peripheral does not support byte or half-word writes.
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Ensure that the stream is disabled otherwise the setting will not be changed.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] stream unsigned int8. Stream number: @ref dma_st_number
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@param[in] peripheral_size unsigned int32. Peripheral word width @ref dma_st_perwidth.
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@param[in] peripheral_size unsigned int32. Peripheral word width @ref
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dma_st_perwidth.
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*/
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void dma_set_peripheral_size(u32 dma, u8 stream, u32 peripheral_size)
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@@ -215,7 +219,7 @@ void dma_set_peripheral_size(u32 dma, u8 stream, u32 peripheral_size)
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DMA_SCR(dma, stream) |= peripheral_size;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Enable Memory Increment after Transfer
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Following each transfer the current memory address is incremented by
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@@ -233,7 +237,7 @@ void dma_enable_memory_increment_mode(u32 dma, u8 stream)
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DMA_SCR(dma, stream) |= DMA_SxCR_MINC;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Disable Memory Increment after Transfer
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Ensure that the stream is disabled otherwise the setting will not be changed.
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@@ -247,7 +251,7 @@ void dma_disable_memory_increment_mode(u32 dma, u8 stream)
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DMA_SCR(dma, stream) &= ~DMA_SxCR_MINC;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Enable Variable Sized Peripheral Increment after Transfer
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Following each transfer the current peripheral address is incremented by
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@@ -266,7 +270,7 @@ void dma_enable_peripheral_increment_mode(u32 dma, u8 stream)
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DMA_SCR(dma, stream) = (reg32 & ~DMA_SxCR_PINCOS);
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Disable Peripheral Increment after Transfer
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Ensure that the stream is disabled otherwise the setting will not be changed.
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@@ -280,7 +284,7 @@ void dma_disable_peripheral_increment_mode(u32 dma, u8 stream)
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DMA_SCR(dma, stream) &= ~DMA_SxCR_PINC;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Enable Fixed Sized Peripheral Increment after Transfer
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Following each transfer the current peripheral address is incremented by
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@@ -298,7 +302,7 @@ void dma_enable_fixed_peripheral_increment_mode(u32 dma, u8 stream)
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DMA_SCR(dma, stream) |= (DMA_SxCR_PINC | DMA_SxCR_PINCOS);
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Enable Memory Circular Mode
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After the number of bytes/words to be transferred has been completed, the
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@@ -320,7 +324,7 @@ void dma_enable_circular_mode(u32 dma, u8 stream)
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DMA_SCR(dma, stream) |= DMA_SxCR_CIRC;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Channel Select
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Associate an input channel to the stream. Not every channel is allocated to a
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@@ -339,7 +343,7 @@ void dma_channel_select(u32 dma, u8 stream, u32 channel)
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DMA_SCR(dma, stream) |= channel;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Set Memory Burst Configuration
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Set the memory burst type to none, 4 8 or 16 word length. This is forced to none
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@@ -358,7 +362,7 @@ void dma_set_memory_burst(u32 dma, u8 stream, u32 burst)
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DMA_SCR(dma, stream) = (reg32 | burst);
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Set Peripheral Burst Configuration
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Set the memory burst type to none, 4 8 or 16 word length. This is forced to none
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@@ -377,11 +381,11 @@ void dma_set_peripheral_burst(u32 dma, u8 stream, u32 burst)
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DMA_SCR(dma, stream) = (reg32 | burst);
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Set Initial Target Memory
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In double buffered mode, set the target memory (M0 or M1) to be used for the first
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transfer.
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In double buffered mode, set the target memory (M0 or M1) to be used for the
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first transfer.
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Ensure that the stream is disabled otherwise the setting will not be changed.
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@@ -393,17 +397,20 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
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void dma_set_initial_target(u32 dma, u8 stream, u8 memory)
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{
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u32 reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_CT);
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if (memory == 1) reg32 |= DMA_SxCR_CT;
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if (memory == 1) {
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reg32 |= DMA_SxCR_CT;
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}
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DMA_SCR(dma, stream) = reg32;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Read Current Memory Target
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In double buffer mode, return the current memory target (M0 or M1). It is possible
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to update the memory pointer in the register that is <b> not </b> currently in
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use. An attempt to change the register currently in use will cause the stream
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to be disabled and the transfer error flag to be set.
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In double buffer mode, return the current memory target (M0 or M1). It is
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possible to update the memory pointer in the register that is <b> not </b>
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currently in use. An attempt to change the register currently in use will cause
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the stream to be disabled and the transfer error flag to be set.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] stream unsigned int8. Stream number: @ref dma_st_number
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@@ -412,11 +419,14 @@ to be disabled and the transfer error flag to be set.
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u8 dma_get_target(u32 dma, u8 stream)
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{
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if (DMA_SCR(dma, stream) & DMA_SxCR_CT) return 1;
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if (DMA_SCR(dma, stream) & DMA_SxCR_CT) {
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return 1;
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}
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return 0;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Enable Double Buffer Mode
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Double buffer mode is used for memory to/from peripheral transfers only, and in
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@@ -436,7 +446,7 @@ void dma_enable_double_buffer_mode(u32 dma, u8 stream)
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DMA_SCR(dma, stream) |= DMA_SxCR_DBM;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Disable Double Buffer Mode
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@@ -448,7 +458,7 @@ void dma_disable_double_buffer_mode(u32 dma, u8 stream)
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DMA_SCR(dma, stream) &= ~DMA_SxCR_DBM;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Set Peripheral Flow Control
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Set the peripheral to control DMA flow. Useful when the number of transfers is
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@@ -465,7 +475,7 @@ void dma_set_peripheral_flow_control(u32 dma, u8 stream)
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DMA_SCR(dma, stream) |= DMA_SxCR_PFCTRL;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Set DMA Flow Control
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Set the DMA controller to control DMA flow. This is the default.
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@@ -481,7 +491,7 @@ void dma_set_dma_flow_control(u32 dma, u8 stream)
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DMA_SCR(dma, stream) &= ~DMA_SxCR_PFCTRL;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Enable Interrupt on Transfer Error
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@@ -494,7 +504,7 @@ void dma_enable_transfer_error_interrupt(u32 dma, u8 stream)
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DMA_SCR(dma, stream) |= DMA_SxCR_TEIE;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Disable Interrupt on Transfer Error
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@@ -506,7 +516,7 @@ void dma_disable_transfer_error_interrupt(u32 dma, u8 stream)
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DMA_SCR(dma, stream) &= ~DMA_SxCR_TEIE;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Enable Interrupt on Transfer Half Complete
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@@ -519,7 +529,7 @@ void dma_enable_half_transfer_interrupt(u32 dma, u8 stream)
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DMA_SCR(dma, stream) |= DMA_SxCR_HTIE;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Disable Interrupt on Transfer Half Complete
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@@ -531,7 +541,7 @@ void dma_disable_half_transfer_interrupt(u32 dma, u8 stream)
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DMA_SCR(dma, stream) &= ~DMA_SxCR_HTIE;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Enable Interrupt on Transfer Complete
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@@ -544,7 +554,7 @@ void dma_enable_transfer_complete_interrupt(u32 dma, u8 stream)
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DMA_SCR(dma, stream) |= DMA_SxCR_TCIE;
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}
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/*-----------------------------------------------------------------------------*/
|
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Disable Interrupt on Transfer Complete
|
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
|
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@@ -556,7 +566,7 @@ void dma_disable_transfer_complete_interrupt(u32 dma, u8 stream)
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DMA_SCR(dma, stream) &= ~DMA_SxCR_TCIE;
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}
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/*-----------------------------------------------------------------------------*/
|
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/*---------------------------------------------------------------------------*/
|
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/** @brief DMA Stream Enable Interrupt on Direct Mode Error
|
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
|
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@@ -569,7 +579,7 @@ void dma_enable_direct_mode_error_interrupt(u32 dma, u8 stream)
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DMA_SCR(dma, stream) |= DMA_SxCR_DMEIE;
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}
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|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
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/** @brief DMA Stream Disable Interrupt on Direct Mode Error
|
||||
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
|
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@@ -581,7 +591,7 @@ void dma_disable_direct_mode_error_interrupt(u32 dma, u8 stream)
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DMA_SCR(dma, stream) &= ~DMA_SxCR_DMEIE;
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}
|
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|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief DMA Enable Interrupt on FIFO Error
|
||||
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
|
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@@ -594,7 +604,7 @@ void dma_enable_fifo_error_interrupt(u32 dma, u8 stream)
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DMA_SFCR(dma, stream) |= DMA_SxFCR_FEIE;
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}
|
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|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
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/** @brief DMA Disable Interrupt on FIFO Error
|
||||
|
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
|
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@@ -606,7 +616,7 @@ void dma_disable_fifo_error_interrupt(u32 dma, u8 stream)
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DMA_SFCR(dma, stream) &= ~DMA_SxFCR_FEIE;
|
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}
|
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|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief DMA Get FIFO Status
|
||||
|
||||
Status of FIFO (empty. full or partial filled states) is returned. This has no
|
||||
@@ -619,10 +629,10 @@ meaning if direct mode is enabled (as the FIFO is not used).
|
||||
|
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u32 dma_fifo_status(u32 dma, u8 stream)
|
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{
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return (DMA_SFCR(dma, stream) & DMA_SxFCR_FS_MASK);
|
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return DMA_SFCR(dma, stream) & DMA_SxFCR_FS_MASK;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief DMA Enable Direct Mode
|
||||
|
||||
Direct mode is the default. Data is transferred as soon as a DMA request is
|
||||
@@ -638,7 +648,7 @@ void dma_enable_direct_mode(u32 dma, u8 stream)
|
||||
DMA_SFCR(dma, stream) &= ~DMA_SxFCR_DMDIS;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief DMA Enable FIFO Mode
|
||||
|
||||
Data is transferred via a FIFO.
|
||||
@@ -652,7 +662,7 @@ void dma_enable_fifo_mode(u32 dma, u8 stream)
|
||||
DMA_SFCR(dma, stream) |= DMA_SxFCR_DMDIS;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief DMA Set FIFO Threshold
|
||||
|
||||
This is the filled level at which data is transferred out of the FIFO to the
|
||||
@@ -669,7 +679,7 @@ void dma_set_fifo_threshold(u32 dma, u8 stream, u32 threshold)
|
||||
DMA_SFCR(dma, stream) = (reg32 | threshold);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief DMA Stream Enable
|
||||
|
||||
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
|
||||
@@ -681,7 +691,7 @@ void dma_enable_stream(u32 dma, u8 stream)
|
||||
DMA_SCR(dma, stream) |= DMA_SxCR_EN;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief DMA Stream Disable
|
||||
|
||||
@note The DMA stream registers retain their values when the stream is disabled.
|
||||
@@ -695,11 +705,11 @@ void dma_disable_stream(u32 dma, u8 stream)
|
||||
DMA_SCR(dma, stream) &= ~DMA_SxCR_EN;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief DMA Stream Set the Peripheral Address
|
||||
|
||||
Set the address of the peripheral register to or from which data is to be transferred.
|
||||
Refer to the documentation for the specific peripheral.
|
||||
Set the address of the peripheral register to or from which data is to be
|
||||
transferred. Refer to the documentation for the specific peripheral.
|
||||
|
||||
@note The DMA stream must be disabled before setting this address. This function
|
||||
has no effect if the stream is enabled.
|
||||
@@ -711,11 +721,12 @@ has no effect if the stream is enabled.
|
||||
|
||||
void dma_set_peripheral_address(u32 dma, u8 stream, u32 address)
|
||||
{
|
||||
if (!(DMA_SCR(dma, stream) & DMA_SxCR_EN))
|
||||
if (!(DMA_SCR(dma, stream) & DMA_SxCR_EN)) {
|
||||
DMA_SPAR(dma, stream) = (u32 *) address;
|
||||
}
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief DMA Stream Set the Base Memory Address 0
|
||||
|
||||
Set the address pointer to the memory location for DMA transfers. The DMA stream
|
||||
@@ -733,11 +744,13 @@ This is the default base memory address used in direct mode.
|
||||
void dma_set_memory_address(u32 dma, u8 stream, u32 address)
|
||||
{
|
||||
u32 reg32 = DMA_SCR(dma, stream);
|
||||
if ( !(reg32 & DMA_SxCR_EN) || ((reg32 & DMA_SxCR_CT) && (reg32 & DMA_SxCR_DBM)) )
|
||||
if (!(reg32 & DMA_SxCR_EN) ||
|
||||
((reg32 & DMA_SxCR_CT) && (reg32 & DMA_SxCR_DBM))) {
|
||||
DMA_SM0AR(dma, stream) = (u32 *) address;
|
||||
}
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief DMA Stream Set the Base Memory Address 1
|
||||
|
||||
Set the address pointer to the memory location for DMA transfers. The DMA stream
|
||||
@@ -753,11 +766,13 @@ to change this in double buffer mode when the current target is memory area 0
|
||||
void dma_set_memory_address_1(u32 dma, u8 stream, u32 address)
|
||||
{
|
||||
u32 reg32 = DMA_SCR(dma, stream);
|
||||
if ( !(reg32 & DMA_SxCR_EN) || (!(reg32 & DMA_SxCR_CT) && (reg32 & DMA_SxCR_DBM)) )
|
||||
if (!(reg32 & DMA_SxCR_EN) ||
|
||||
(!(reg32 & DMA_SxCR_CT) && (reg32 & DMA_SxCR_DBM))) {
|
||||
DMA_SM1AR(dma, stream) = (u32 *) address;
|
||||
}
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief DMA Stream Set the Transfer Block Size
|
||||
|
||||
@note The DMA stream must be disabled before setting this count value. The count
|
||||
@@ -765,7 +780,8 @@ is not changed if the stream is enabled.
|
||||
|
||||
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
|
||||
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
|
||||
@param[in] number unsigned int16. Number of data words to transfer (65535 maximum).
|
||||
@param[in] number unsigned int16. Number of data words to transfer (65535
|
||||
maximum).
|
||||
*/
|
||||
|
||||
void dma_set_number_of_data(u32 dma, u8 stream, u16 number)
|
||||
|
||||
Reference in New Issue
Block a user