First coarse run to fix coding style in locm3.
Added --terse and --mailback options to the make stylecheck target. It also does continue even if it enounters a possible error. We decided on two exceptions from the linux kernel coding standard: - Empty wait while loops may end with ; on the same line. - All blocks after while, if, for have to be in brackets even if they only contain one statement. Otherwise it is easy to introduce an error. Checkpatch needs to be adapted to reflect those changes.
This commit is contained in:
Piotr Esden-Tempski
@@ -40,7 +40,7 @@ LGPL License Terms @ref lgpl_license
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#include <libopencm3/stm32/dma.h>
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Reset
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The channel is disabled and configuration registers are cleared.
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@@ -63,7 +63,7 @@ void dma_channel_reset(u32 dma, u8 channel)
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DMA_IFCR(dma) |= DMA_IFCR_CIF(channel);
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Clear Interrupt Flag
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The interrupt flag for the channel is cleared. More than one interrupt for the
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@@ -71,7 +71,8 @@ same channel may be cleared by using the logical OR of the interrupt flags.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: @ref dma_ch
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@param[in] interrupts unsigned int32. Logical OR of interrupt numbers: @ref dma_if_offset
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@param[in] interrupts unsigned int32. Logical OR of interrupt numbers: @ref
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dma_if_offset
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*/
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void dma_clear_interrupt_flags(u32 dma, u8 channel, u32 interrupts)
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@@ -81,7 +82,7 @@ void dma_clear_interrupt_flags(u32 dma, u8 channel, u32 interrupts)
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DMA_IFCR(dma) = flags;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Read Interrupt Flag
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The interrupt flag for the channel is returned.
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@@ -99,7 +100,7 @@ bool dma_get_interrupt_flag(u32 dma, u8 channel, u32 interrupt)
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return ((DMA_ISR(dma) & flag) > 0);
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Enable Memory to Memory Transfers
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Memory to memory transfers do not require a trigger to activate each transfer.
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@@ -116,7 +117,7 @@ void dma_enable_mem2mem_mode(u32 dma, u8 channel)
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DMA_CCR(dma, channel) &= ~DMA_CCR_CIRC;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Set Priority
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Channel Priority has four levels: low to very high. This has precedence over the
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@@ -133,7 +134,7 @@ void dma_set_priority(u32 dma, u8 channel, u32 prio)
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DMA_CCR(dma, channel) |= prio;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Set Memory Word Width
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Set the memory word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for
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@@ -151,16 +152,17 @@ void dma_set_memory_size(u32 dma, u8 channel, u32 mem_size)
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DMA_CCR(dma, channel) |= mem_size;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Set Peripheral Word Width
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Set the peripheral word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for
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alignment information if the source and destination widths do not match, or
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Set the peripheral word width 8 bits, 16 bits, or 32 bits. Refer to datasheet
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for alignment information if the source and destination widths do not match, or
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if the peripheral does not support byte or half-word writes.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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@param[in] peripheral_size unsigned int32. Peripheral word width @ref dma_ch_perwidth.
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@param[in] peripheral_size unsigned int32. Peripheral word width @ref
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dma_ch_perwidth.
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*/
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void dma_set_peripheral_size(u32 dma, u8 channel, u32 peripheral_size)
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@@ -169,7 +171,7 @@ void dma_set_peripheral_size(u32 dma, u8 channel, u32 peripheral_size)
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DMA_CCR(dma, channel) |= peripheral_size;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Enable Memory Increment after Transfer
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Following each transfer the current memory address is incremented by
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@@ -185,7 +187,7 @@ void dma_enable_memory_increment_mode(u32 dma, u8 channel)
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DMA_CCR(dma, channel) |= DMA_CCR_MINC;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Disable Memory Increment after Transfer
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@@ -197,7 +199,7 @@ void dma_disable_memory_increment_mode(u32 dma, u8 channel)
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DMA_CCR(dma, channel) &= ~DMA_CCR_MINC;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Enable Peripheral Increment after Transfer
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Following each transfer the current peripheral address is incremented by
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@@ -213,7 +215,7 @@ void dma_enable_peripheral_increment_mode(u32 dma, u8 channel)
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DMA_CCR(dma, channel) |= DMA_CCR_PINC;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Disable Peripheral Increment after Transfer
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@@ -225,7 +227,7 @@ void dma_disable_peripheral_increment_mode(u32 dma, u8 channel)
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DMA_CCR(dma, channel) &= ~DMA_CCR_PINC;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Enable Memory Circular Mode
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After the number of bytes/words to be transferred has been completed, the
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@@ -245,7 +247,7 @@ void dma_enable_circular_mode(u32 dma, u8 channel)
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DMA_CCR(dma, channel) &= ~DMA_CCR_MEM2MEM;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Enable Transfers from a Peripheral
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The data direction is set to read from a peripheral.
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@@ -259,7 +261,7 @@ void dma_set_read_from_peripheral(u32 dma, u8 channel)
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DMA_CCR(dma, channel) &= ~DMA_CCR_DIR;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Enable Transfers from Memory
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The data direction is set to read from memory.
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@@ -273,7 +275,7 @@ void dma_set_read_from_memory(u32 dma, u8 channel)
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DMA_CCR(dma, channel) |= DMA_CCR_DIR;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Enable Interrupt on Transfer Error
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@@ -285,7 +287,7 @@ void dma_enable_transfer_error_interrupt(u32 dma, u8 channel)
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DMA_CCR(dma, channel) |= DMA_CCR_TEIE;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Disable Interrupt on Transfer Error
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@@ -297,7 +299,7 @@ void dma_disable_transfer_error_interrupt(u32 dma, u8 channel)
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DMA_CCR(dma, channel) &= ~DMA_CCR_TEIE;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Enable Interrupt on Transfer Half Complete
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@@ -309,7 +311,7 @@ void dma_enable_half_transfer_interrupt(u32 dma, u8 channel)
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DMA_CCR(dma, channel) |= DMA_CCR_HTIE;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Disable Interrupt on Transfer Half Complete
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@@ -321,7 +323,7 @@ void dma_disable_half_transfer_interrupt(u32 dma, u8 channel)
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DMA_CCR(dma, channel) &= ~DMA_CCR_HTIE;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Enable Interrupt on Transfer Complete
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@@ -333,7 +335,7 @@ void dma_enable_transfer_complete_interrupt(u32 dma, u8 channel)
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DMA_CCR(dma, channel) |= DMA_CCR_TCIE;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Disable Interrupt on Transfer Complete
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@@ -345,7 +347,7 @@ void dma_disable_transfer_complete_interrupt(u32 dma, u8 channel)
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DMA_CCR(dma, channel) &= ~DMA_CCR_TCIE;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Enable
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@@ -357,10 +359,11 @@ void dma_enable_channel(u32 dma, u8 channel)
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DMA_CCR(dma, channel) |= DMA_CCR_EN;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Disable
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@note The DMA channel registers retain their values when the channel is disabled.
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@note The DMA channel registers retain their values when the channel is
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disabled.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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@@ -371,14 +374,14 @@ void dma_disable_channel(u32 dma, u8 channel)
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DMA_CCR(dma, channel) &= ~DMA_CCR_EN;
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Set the Peripheral Address
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Set the address of the peripheral register to or from which data is to be transferred.
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Refer to the documentation for the specific peripheral.
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Set the address of the peripheral register to or from which data is to be
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transferred. Refer to the documentation for the specific peripheral.
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@note The DMA channel must be disabled before setting this address. This function
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has no effect if the channel is enabled.
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@note The DMA channel must be disabled before setting this address. This
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function has no effect if the channel is enabled.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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@@ -387,15 +390,16 @@ has no effect if the channel is enabled.
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void dma_set_peripheral_address(u32 dma, u8 channel, u32 address)
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{
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if (!(DMA_CCR(dma, channel) & DMA_CCR_EN))
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if (!(DMA_CCR(dma, channel) & DMA_CCR_EN)) {
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DMA_CPAR(dma, channel) = (u32) address;
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}
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Set the Base Memory Address
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@note The DMA channel must be disabled before setting this address. This function
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has no effect if the channel is enabled.
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@note The DMA channel must be disabled before setting this address. This
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function has no effect if the channel is enabled.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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@@ -404,19 +408,21 @@ has no effect if the channel is enabled.
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void dma_set_memory_address(u32 dma, u8 channel, u32 address)
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{
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if (!(DMA_CCR(dma, channel) & DMA_CCR_EN))
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if (!(DMA_CCR(dma, channel) & DMA_CCR_EN)) {
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DMA_CMAR(dma, channel) = (u32) address;
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}
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}
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/*-----------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Set the Transfer Block Size
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@note The DMA channel must be disabled before setting this count value. The count
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is not changed if the channel is enabled.
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@note The DMA channel must be disabled before setting this count value. The
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count is not changed if the channel is enabled.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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@param[in] number unsigned int16. Number of data words to transfer (65535 maximum).
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@param[in] number unsigned int16. Number of data words to transfer (65535
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maximum).
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*/
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void dma_set_number_of_data(u32 dma, u8 channel, u16 number)
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