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First coarse run to fix coding style in locm3.

Browse Source 
Added --terse and --mailback options to the make stylecheck target. It
also does continue even if it enounters a possible error.

We decided on two exceptions from the linux kernel coding standard:
- Empty wait while loops may end with ; on the same line.
- All blocks after while, if, for have to be in brackets even if they
  only contain one statement. Otherwise it is easy to introduce an
  error.

Checkpatch needs to be adapted to reflect those changes.
This commit is contained in:
Piotr Esden-Tempski
2013-06-12 17:44:07 -07:00
parent 48e0f3326b
commit 7df63fcae0
147 changed files with 3323 additions and 2565 deletions
Download Patch File Download Diff File Expand all files Collapse all files

159
lib/stm32/can.c
View File

@@ -59,13 +59,15 @@ LGPL License Terms @ref lgpl_license
*/
#define CAN_MSR_INAK_TIMEOUT 0x0000FFFF
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Reset
The CAN peripheral and all its associated configuration registers are placed in the
reset condition. The reset is effective via the RCC peripheral reset system.
The CAN peripheral and all its associated configuration registers are placed in
the reset condition. The reset is effective via the RCC peripheral reset
system.
@param[in] canport Unsigned int32. CAN block register address base @ref can_reg_base.
@param[in] canport Unsigned int32. CAN block register address base @ref
can_reg_base.
*/
void can_reset(u32 canport)
{
@@ -78,7 +80,7 @@ void can_reset(u32 canport)
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Init
Initialize the selected CAN peripheral block.
@@ -112,11 +114,10 @@ int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart,
/* Wait for acknowledge. */
wait_ack = CAN_MSR_INAK_TIMEOUT;
while ((--wait_ack) &&
((CAN_MSR(canport) & CAN_MSR_INAK) != CAN_MSR_INAK)) {
}
((CAN_MSR(canport) & CAN_MSR_INAK) != CAN_MSR_INAK));
/* Check the acknowledge. */
if ((CAN_MSR(canport) & CAN_MSR_INAK) != CAN_MSR_INAK){
if ((CAN_MSR(canport) & CAN_MSR_INAK) != CAN_MSR_INAK) {
return 1;
}
@@ -126,64 +127,55 @@ int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart,
/* Set the automatic bus-off management. */
if (ttcm) {
CAN_MCR(canport) |= CAN_MCR_TTCM;
}
else {
} else {
CAN_MCR(canport) &= ~CAN_MCR_TTCM;
}
if (abom) {
CAN_MCR(canport) |= CAN_MCR_ABOM;
}
else {
} else {
CAN_MCR(canport) &= ~CAN_MCR_ABOM;
}
if (awum) {
CAN_MCR(canport) |= CAN_MCR_AWUM;
}
else {
} else {
CAN_MCR(canport) &= ~CAN_MCR_AWUM;
}
if (nart) {
CAN_MCR(canport) |= CAN_MCR_NART;
}
else{
} else {
CAN_MCR(canport) &= ~CAN_MCR_NART;
}
if (rflm) {
CAN_MCR(canport) |= CAN_MCR_RFLM;
}
else {
} else {
CAN_MCR(canport) &= ~CAN_MCR_RFLM;
}
if (txfp) {
CAN_MCR(canport) |= CAN_MCR_TXFP;
}
else {
} else {
CAN_MCR(canport) &= ~CAN_MCR_TXFP;
}
if (silent) {
CAN_BTR(canport) |= CAN_BTR_SILM;
}
else {
} else {
CAN_BTR(canport) &= ~CAN_BTR_SILM;
}
if (loopback) {
CAN_BTR(canport) |= CAN_BTR_LBKM;
}
else {
} else {
CAN_BTR(canport) &= ~CAN_BTR_LBKM;
}
/* Set bit timings. */
CAN_BTR(canport) |= sjw | ts2 | ts1 |
((brp - 1ul) & CAN_BTR_BRP_MASK);
((brp - 1ul) & CAN_BTR_BRP_MASK);
/* Request initialization "leave". */
CAN_MCR(canport) &= ~CAN_MCR_INRQ;
@@ -191,8 +183,7 @@ int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart,
/* Wait for acknowledge. */
wait_ack = CAN_MSR_INAK_TIMEOUT;
while ((--wait_ack) &&
((CAN_MSR(canport) & CAN_MSR_INAK) == CAN_MSR_INAK)) {
}
((CAN_MSR(canport) & CAN_MSR_INAK) == CAN_MSR_INAK));
if ((CAN_MSR(canport) & CAN_MSR_INAK) == CAN_MSR_INAK) {
ret = 1;
@@ -201,7 +192,7 @@ int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart,
return ret;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Filter Init
Initialize incoming message filter and assign to FIFO.
@@ -251,10 +242,10 @@ void can_filter_init(u32 canport, u32 nr, bool scale_32bit, bool id_list_mode,
/* Select FIFO0 or FIFO1 as filter assignement. */
if (fifo) {
CAN_FFA1R(canport) |= filter_select_bit; /* FIFO1 */
}
else {
} else {
CAN_FFA1R(canport) &= ~filter_select_bit; /* FIFO0 */
}
if (enable) {
CAN_FA1R(canport) |= filter_select_bit; /* Activate filter. */
}
@@ -263,7 +254,7 @@ void can_filter_init(u32 canport, u32 nr, bool scale_32bit, bool id_list_mode,
CAN_FMR(canport) &= ~CAN_FMR_FINIT;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Initialize a 16bit Message ID Mask Filter
@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
@@ -283,7 +274,7 @@ void can_filter_id_mask_16bit_init(u32 canport, u32 nr, u16 id1, u16 mask1,
((u32)id2 << 16) | (u32)mask2, fifo, enable);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Initialize a 32bit Message ID Mask Filter
@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
@@ -299,7 +290,7 @@ void can_filter_id_mask_32bit_init(u32 canport, u32 nr, u32 id, u32 mask,
can_filter_init(canport, nr, true, false, id, mask, fifo, enable);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Initialize a 16bit Message ID List Filter
@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
@@ -319,7 +310,7 @@ void can_filter_id_list_16bit_init(u32 canport, u32 nr, u16 id1, u16 id2,
((u32)id3 << 16) | (u32)id4, fifo, enable);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Initialize a 32bit Message ID List Filter
@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
@@ -335,7 +326,7 @@ void can_filter_id_list_32bit_init(u32 canport, u32 nr, u32 id1, u32 id2,
can_filter_init(canport, nr, true, true, id1, id2, fifo, enable);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Enable IRQ
@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
@@ -346,7 +337,7 @@ void can_enable_irq(u32 canport, u32 irq)
CAN_IER(canport) |= irq;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Disable IRQ
@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
@@ -357,7 +348,7 @@ void can_disable_irq(u32 canport, u32 irq)
CAN_IER(canport) &= ~irq;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Transmit Message
@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
@@ -376,7 +367,7 @@ int can_transmit(u32 canport, u32 id, bool ext, bool rtr, u8 length, u8 *data)
union {
u8 data8[4];
u32 data32;
}tdlxr,tdhxr;
} tdlxr, tdhxr;
/* Check which transmit mailbox is empty if any. */
if ((CAN_TSR(canport) & CAN_TSR_TME0) == CAN_TSR_TME0) {
@@ -394,53 +385,54 @@ int can_transmit(u32 canport, u32 id, bool ext, bool rtr, u8 length, u8 *data)
/* If we have no empty mailbox return with an error. */
if (ret == -1) {
return ret;
}
if (ext) {
/* Set extended ID. */
CAN_TIxR(canport, mailbox) = (id << CAN_TIxR_EXID_SHIFT) | CAN_TIxR_IDE;
CAN_TIxR(canport, mailbox) = (id << CAN_TIxR_EXID_SHIFT) |
CAN_TIxR_IDE;
} else {
/* Set standard ID. */
CAN_TIxR(canport, mailbox) = id << CAN_TIxR_STID_SHIFT;
}
/* Set/clear remote transmission request bit. */
if (rtr){
if (rtr) {
CAN_TIxR(canport, mailbox) |= CAN_TIxR_RTR; /* Set */
}
/* Set the DLC. */
CAN_TDTxR(canport, mailbox) &= ~CAN_TDTxR_DLC_MASK;
CAN_TDTxR(canport, mailbox) |= (length & CAN_TDTxR_DLC_MASK);
switch(length) {
case 8:
tdhxr.data8[3] = data[7];
/* no break */
case 7:
tdhxr.data8[2] = data[6];
/* no break */
case 6:
tdhxr.data8[1] = data[5];
/* no break */
case 5:
tdhxr.data8[0] = data[4];
/* no break */
case 4:
tdlxr.data8[3] = data[3];
/* no break */
case 3:
tdlxr.data8[2] = data[2];
/* no break */
case 2:
tdlxr.data8[1] = data[1];
/* no break */
case 1:
tdlxr.data8[0] = data[0];
/* no break */
default:
break;
switch (length) {
case 8:
tdhxr.data8[3] = data[7];
/* no break */
case 7:
tdhxr.data8[2] = data[6];
/* no break */
case 6:
tdhxr.data8[1] = data[5];
/* no break */
case 5:
tdhxr.data8[0] = data[4];
/* no break */
case 4:
tdlxr.data8[3] = data[3];
/* no break */
case 3:
tdlxr.data8[2] = data[2];
/* no break */
case 2:
tdlxr.data8[1] = data[1];
/* no break */
case 1:
tdlxr.data8[0] = data[0];
/* no break */
default:
break;
}
/* Set the data. */
@@ -453,7 +445,7 @@ int can_transmit(u32 canport, u32 id, bool ext, bool rtr, u8 length, u8 *data)
return ret;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Release FIFO
@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
@@ -463,13 +455,12 @@ void can_fifo_release(u32 canport, u8 fifo)
{
if (fifo == 0) {
CAN_RF0R(canport) |= CAN_RF1R_RFOM1;
}
else {
} else {
CAN_RF1R(canport) |= CAN_RF1R_RFOM1;
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Receive Message
@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
@@ -489,8 +480,8 @@ void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext,
union {
u8 data8[4];
u32 data32;
}rdlxr,rdhxr;
const u32 fifoid_array[2] = {CAN_FIFO0,CAN_FIFO1};
} rdlxr, rdhxr;
const u32 fifoid_array[2] = {CAN_FIFO0, CAN_FIFO1};
fifo_id = fifoid_array[fifo];
@@ -498,18 +489,19 @@ void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext,
if (CAN_RIxR(canport, fifo_id) & CAN_RIxR_IDE) {
*ext = true;
/* Get extended CAN ID. */
*id = (CAN_RIxR(canport, fifo_id) >> CAN_RIxR_EXID_SHIFT) & CAN_RIxR_EXID_MASK;
*id = (CAN_RIxR(canport, fifo_id) >> CAN_RIxR_EXID_SHIFT) &
CAN_RIxR_EXID_MASK;
} else {
*ext = false;
/* Get standard CAN ID. */
*id = (CAN_RIxR(canport, fifo_id) >> CAN_RIxR_STID_SHIFT) & CAN_RIxR_STID_MASK;
*id = (CAN_RIxR(canport, fifo_id) >> CAN_RIxR_STID_SHIFT) &
CAN_RIxR_STID_MASK;
}
/* Get remote transmit flag. */
if (CAN_RIxR(canport, fifo_id) & CAN_RIxR_RTR) {
if (CAN_RIxR(canport, fifo_id) & CAN_RIxR_RTR) {
*rtr = true;
}
else {
} else {
*rtr = false;
}
@@ -519,8 +511,9 @@ void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext,
/* Get data length. */
*length = CAN_RDTxR(canport, fifo_id) & CAN_RDTxR_DLC_MASK;
/* accelerate reception by copying the CAN data from the controller memory to
* the fast internal RAM */
/* accelerate reception by copying the CAN data from the controller
* memory to the fast internal RAM
*/
rdlxr.data32 = CAN_RDLxR(canport, fifo_id);
rdhxr.data32 = CAN_RDHxR(canport, fifo_id);
@@ -546,7 +539,7 @@ void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext,
data[7] = rdhxr.data8[3];
/* Release the FIFO. */
if (release){
if (release) {
can_fifo_release(canport, fifo);
}
}