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First coarse run to fix coding style in locm3.

Browse Source 
Added --terse and --mailback options to the make stylecheck target. It
also does continue even if it enounters a possible error.

We decided on two exceptions from the linux kernel coding standard:
- Empty wait while loops may end with ; on the same line.
- All blocks after while, if, for have to be in brackets even if they
  only contain one statement. Otherwise it is easy to introduce an
  error.

Checkpatch needs to be adapted to reflect those changes.
This commit is contained in:
Piotr Esden-Tempski
2013-06-12 17:44:07 -07:00
parent 48e0f3326b
commit 7df63fcae0
147 changed files with 3323 additions and 2565 deletions
Download Patch File Download Diff File Expand all files Collapse all files

159
lib/stm32/can.c
View File

@@ -59,13 +59,15 @@ LGPL License Terms @ref lgpl_license
*/
#define CAN_MSR_INAK_TIMEOUT 0x0000FFFF
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Reset
The CAN peripheral and all its associated configuration registers are placed in the
reset condition. The reset is effective via the RCC peripheral reset system.
The CAN peripheral and all its associated configuration registers are placed in
the reset condition. The reset is effective via the RCC peripheral reset
system.
@param[in] canport Unsigned int32. CAN block register address base @ref can_reg_base.
@param[in] canport Unsigned int32. CAN block register address base @ref
can_reg_base.
*/
void can_reset(u32 canport)
{
@@ -78,7 +80,7 @@ void can_reset(u32 canport)
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Init
Initialize the selected CAN peripheral block.
@@ -112,11 +114,10 @@ int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart,
/* Wait for acknowledge. */
wait_ack = CAN_MSR_INAK_TIMEOUT;
while ((--wait_ack) &&
((CAN_MSR(canport) & CAN_MSR_INAK) != CAN_MSR_INAK)) {
}
((CAN_MSR(canport) & CAN_MSR_INAK) != CAN_MSR_INAK));
/* Check the acknowledge. */
if ((CAN_MSR(canport) & CAN_MSR_INAK) != CAN_MSR_INAK){
if ((CAN_MSR(canport) & CAN_MSR_INAK) != CAN_MSR_INAK) {
return 1;
}
@@ -126,64 +127,55 @@ int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart,
/* Set the automatic bus-off management. */
if (ttcm) {
CAN_MCR(canport) |= CAN_MCR_TTCM;
}
else {
} else {
CAN_MCR(canport) &= ~CAN_MCR_TTCM;
}
if (abom) {
CAN_MCR(canport) |= CAN_MCR_ABOM;
}
else {
} else {
CAN_MCR(canport) &= ~CAN_MCR_ABOM;
}
if (awum) {
CAN_MCR(canport) |= CAN_MCR_AWUM;
}
else {
} else {
CAN_MCR(canport) &= ~CAN_MCR_AWUM;
}
if (nart) {
CAN_MCR(canport) |= CAN_MCR_NART;
}
else{
} else {
CAN_MCR(canport) &= ~CAN_MCR_NART;
}
if (rflm) {
CAN_MCR(canport) |= CAN_MCR_RFLM;
}
else {
} else {
CAN_MCR(canport) &= ~CAN_MCR_RFLM;
}
if (txfp) {
CAN_MCR(canport) |= CAN_MCR_TXFP;
}
else {
} else {
CAN_MCR(canport) &= ~CAN_MCR_TXFP;
}
if (silent) {
CAN_BTR(canport) |= CAN_BTR_SILM;
}
else {
} else {
CAN_BTR(canport) &= ~CAN_BTR_SILM;
}
if (loopback) {
CAN_BTR(canport) |= CAN_BTR_LBKM;
}
else {
} else {
CAN_BTR(canport) &= ~CAN_BTR_LBKM;
}
/* Set bit timings. */
CAN_BTR(canport) |= sjw | ts2 | ts1 |
((brp - 1ul) & CAN_BTR_BRP_MASK);
((brp - 1ul) & CAN_BTR_BRP_MASK);
/* Request initialization "leave". */
CAN_MCR(canport) &= ~CAN_MCR_INRQ;
@@ -191,8 +183,7 @@ int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart,
/* Wait for acknowledge. */
wait_ack = CAN_MSR_INAK_TIMEOUT;
while ((--wait_ack) &&
((CAN_MSR(canport) & CAN_MSR_INAK) == CAN_MSR_INAK)) {
}
((CAN_MSR(canport) & CAN_MSR_INAK) == CAN_MSR_INAK));
if ((CAN_MSR(canport) & CAN_MSR_INAK) == CAN_MSR_INAK) {
ret = 1;
@@ -201,7 +192,7 @@ int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart,
return ret;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Filter Init
Initialize incoming message filter and assign to FIFO.
@@ -251,10 +242,10 @@ void can_filter_init(u32 canport, u32 nr, bool scale_32bit, bool id_list_mode,
/* Select FIFO0 or FIFO1 as filter assignement. */
if (fifo) {
CAN_FFA1R(canport) |= filter_select_bit; /* FIFO1 */
}
else {
} else {
CAN_FFA1R(canport) &= ~filter_select_bit; /* FIFO0 */
}
if (enable) {
CAN_FA1R(canport) |= filter_select_bit; /* Activate filter. */
}
@@ -263,7 +254,7 @@ void can_filter_init(u32 canport, u32 nr, bool scale_32bit, bool id_list_mode,
CAN_FMR(canport) &= ~CAN_FMR_FINIT;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Initialize a 16bit Message ID Mask Filter
@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
@@ -283,7 +274,7 @@ void can_filter_id_mask_16bit_init(u32 canport, u32 nr, u16 id1, u16 mask1,
((u32)id2 << 16) | (u32)mask2, fifo, enable);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Initialize a 32bit Message ID Mask Filter
@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
@@ -299,7 +290,7 @@ void can_filter_id_mask_32bit_init(u32 canport, u32 nr, u32 id, u32 mask,
can_filter_init(canport, nr, true, false, id, mask, fifo, enable);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Initialize a 16bit Message ID List Filter
@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
@@ -319,7 +310,7 @@ void can_filter_id_list_16bit_init(u32 canport, u32 nr, u16 id1, u16 id2,
((u32)id3 << 16) | (u32)id4, fifo, enable);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Initialize a 32bit Message ID List Filter
@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
@@ -335,7 +326,7 @@ void can_filter_id_list_32bit_init(u32 canport, u32 nr, u32 id1, u32 id2,
can_filter_init(canport, nr, true, true, id1, id2, fifo, enable);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Enable IRQ
@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
@@ -346,7 +337,7 @@ void can_enable_irq(u32 canport, u32 irq)
CAN_IER(canport) |= irq;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Disable IRQ
@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
@@ -357,7 +348,7 @@ void can_disable_irq(u32 canport, u32 irq)
CAN_IER(canport) &= ~irq;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Transmit Message
@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
@@ -376,7 +367,7 @@ int can_transmit(u32 canport, u32 id, bool ext, bool rtr, u8 length, u8 *data)
union {
u8 data8[4];
u32 data32;
}tdlxr,tdhxr;
} tdlxr, tdhxr;
/* Check which transmit mailbox is empty if any. */
if ((CAN_TSR(canport) & CAN_TSR_TME0) == CAN_TSR_TME0) {
@@ -394,53 +385,54 @@ int can_transmit(u32 canport, u32 id, bool ext, bool rtr, u8 length, u8 *data)
/* If we have no empty mailbox return with an error. */
if (ret == -1) {
return ret;
}
if (ext) {
/* Set extended ID. */
CAN_TIxR(canport, mailbox) = (id << CAN_TIxR_EXID_SHIFT) | CAN_TIxR_IDE;
CAN_TIxR(canport, mailbox) = (id << CAN_TIxR_EXID_SHIFT) |
CAN_TIxR_IDE;
} else {
/* Set standard ID. */
CAN_TIxR(canport, mailbox) = id << CAN_TIxR_STID_SHIFT;
}
/* Set/clear remote transmission request bit. */
if (rtr){
if (rtr) {
CAN_TIxR(canport, mailbox) |= CAN_TIxR_RTR; /* Set */
}
/* Set the DLC. */
CAN_TDTxR(canport, mailbox) &= ~CAN_TDTxR_DLC_MASK;
CAN_TDTxR(canport, mailbox) |= (length & CAN_TDTxR_DLC_MASK);
switch(length) {
case 8:
tdhxr.data8[3] = data[7];
/* no break */
case 7:
tdhxr.data8[2] = data[6];
/* no break */
case 6:
tdhxr.data8[1] = data[5];
/* no break */
case 5:
tdhxr.data8[0] = data[4];
/* no break */
case 4:
tdlxr.data8[3] = data[3];
/* no break */
case 3:
tdlxr.data8[2] = data[2];
/* no break */
case 2:
tdlxr.data8[1] = data[1];
/* no break */
case 1:
tdlxr.data8[0] = data[0];
/* no break */
default:
break;
switch (length) {
case 8:
tdhxr.data8[3] = data[7];
/* no break */
case 7:
tdhxr.data8[2] = data[6];
/* no break */
case 6:
tdhxr.data8[1] = data[5];
/* no break */
case 5:
tdhxr.data8[0] = data[4];
/* no break */
case 4:
tdlxr.data8[3] = data[3];
/* no break */
case 3:
tdlxr.data8[2] = data[2];
/* no break */
case 2:
tdlxr.data8[1] = data[1];
/* no break */
case 1:
tdlxr.data8[0] = data[0];
/* no break */
default:
break;
}
/* Set the data. */
@@ -453,7 +445,7 @@ int can_transmit(u32 canport, u32 id, bool ext, bool rtr, u8 length, u8 *data)
return ret;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Release FIFO
@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
@@ -463,13 +455,12 @@ void can_fifo_release(u32 canport, u8 fifo)
{
if (fifo == 0) {
CAN_RF0R(canport) |= CAN_RF1R_RFOM1;
}
else {
} else {
CAN_RF1R(canport) |= CAN_RF1R_RFOM1;
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Receive Message
@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
@@ -489,8 +480,8 @@ void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext,
union {
u8 data8[4];
u32 data32;
}rdlxr,rdhxr;
const u32 fifoid_array[2] = {CAN_FIFO0,CAN_FIFO1};
} rdlxr, rdhxr;
const u32 fifoid_array[2] = {CAN_FIFO0, CAN_FIFO1};
fifo_id = fifoid_array[fifo];
@@ -498,18 +489,19 @@ void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext,
if (CAN_RIxR(canport, fifo_id) & CAN_RIxR_IDE) {
*ext = true;
/* Get extended CAN ID. */
*id = (CAN_RIxR(canport, fifo_id) >> CAN_RIxR_EXID_SHIFT) & CAN_RIxR_EXID_MASK;
*id = (CAN_RIxR(canport, fifo_id) >> CAN_RIxR_EXID_SHIFT) &
CAN_RIxR_EXID_MASK;
} else {
*ext = false;
/* Get standard CAN ID. */
*id = (CAN_RIxR(canport, fifo_id) >> CAN_RIxR_STID_SHIFT) & CAN_RIxR_STID_MASK;
*id = (CAN_RIxR(canport, fifo_id) >> CAN_RIxR_STID_SHIFT) &
CAN_RIxR_STID_MASK;
}
/* Get remote transmit flag. */
if (CAN_RIxR(canport, fifo_id) & CAN_RIxR_RTR) {
if (CAN_RIxR(canport, fifo_id) & CAN_RIxR_RTR) {
*rtr = true;
}
else {
} else {
*rtr = false;
}
@@ -519,8 +511,9 @@ void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext,
/* Get data length. */
*length = CAN_RDTxR(canport, fifo_id) & CAN_RDTxR_DLC_MASK;
/* accelerate reception by copying the CAN data from the controller memory to
* the fast internal RAM */
/* accelerate reception by copying the CAN data from the controller
* memory to the fast internal RAM
*/
rdlxr.data32 = CAN_RDLxR(canport, fifo_id);
rdhxr.data32 = CAN_RDHxR(canport, fifo_id);
@@ -546,7 +539,7 @@ void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext,
data[7] = rdhxr.data8[3];
/* Release the FIFO. */
if (release){
if (release) {
can_fifo_release(canport, fifo);
}
}

10
lib/stm32/common/crc_common_all.c
View File

@@ -27,7 +27,7 @@
/**@{*/
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CRC Reset.
Reset the CRC unit and forces the data register to all 1s.
@@ -39,7 +39,7 @@ void crc_reset(void)
CRC_CR |= CRC_CR_RESET;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CRC Calculate.
Writes a data word to the register, the write operation stalling until the
@@ -52,11 +52,11 @@ computation is complete.
u32 crc_calculate(u32 data)
{
CRC_DR = data;
// Data sheet says this blocks until it's ready....
/* Data sheet says this blocks until it's ready.... */
return CRC_DR;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CRC Calculate of a Block of Data.
Writes data words consecutively to the register, the write operation stalling
@@ -70,9 +70,11 @@ until the computation of each word is complete.
u32 crc_calculate_block(u32 *datap, int size)
{
int i;
for (i = 0; i < size; i++) {
CRC_DR = datap[i];
}
return CRC_DR;
}
/**@}*/

121
lib/stm32/common/dac_common_all.c
View File

@@ -120,12 +120,12 @@ LGPL License Terms @ref lgpl_license
#define MASK8 0xFF
#define MASK12 0xFFF
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DAC Channel Enable.
Enable a digital to analog converter channel. After setting this enable, the DAC
requires a t<sub>wakeup</sub> time typically around 10 microseconds before it
actually wakes up.
Enable a digital to analog converter channel. After setting this enable, the
DAC requires a t<sub>wakeup</sub> time typically around 10 microseconds before
it actually wakes up.
@param[in] dac_channel enum ::data_channel.
*/
@@ -145,7 +145,7 @@ void dac_enable(data_channel dac_channel)
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DAC Channel Disable.
Disable a digital to analog converter channel.
@@ -168,13 +168,13 @@ void dac_disable(data_channel dac_channel)
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DAC Channel Output Buffer Enable.
Enable a digital to analog converter channel output drive buffer. This is an optional
amplifying buffer that provides additional drive for the output signal. The
buffer is enabled by default after a reset and needs to be explicitly disabled
if required.
Enable a digital to analog converter channel output drive buffer. This is an
optional amplifying buffer that provides additional drive for the output
signal. The buffer is enabled by default after a reset and needs to be
explicitly disabled if required.
@param[in] dac_channel enum ::data_channel.
*/
@@ -193,12 +193,12 @@ void dac_buffer_enable(data_channel dac_channel)
break;
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DAC Channel Output Buffer Disable.
Disable a digital to analog converter channel output drive buffer. Disabling this will
reduce power consumption slightly and will increase the output impedance of the DAC.
The buffers are enabled by default after a reset.
Disable a digital to analog converter channel output drive buffer. Disabling
this will reduce power consumption slightly and will increase the output
impedance of the DAC. The buffers are enabled by default after a reset.
@param[in] dac_channel enum ::data_channel.
*/
@@ -217,7 +217,7 @@ void dac_buffer_disable(data_channel dac_channel)
break;
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DAC Channel DMA Enable.
Enable a digital to analog converter channel DMA mode (connected to DMA2 channel
@@ -242,7 +242,7 @@ void dac_dma_enable(data_channel dac_channel)
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DAC Channel DMA Disable.
Disable a digital to analog converter channel DMA mode.
@@ -265,13 +265,13 @@ void dac_dma_disable(data_channel dac_channel)
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DAC Channel Trigger Enable.
Enable a digital to analog converter channel external trigger mode. This allows an
external trigger to initiate register transfers from the buffer register to the DAC
output register, followed by a DMA transfer to the buffer register if DMA is enabled.
The trigger source must also be selected.
Enable a digital to analog converter channel external trigger mode. This allows
an external trigger to initiate register transfers from the buffer register to
the DAC output register, followed by a DMA transfer to the buffer register if
DMA is enabled. The trigger source must also be selected.
@param[in] dac_channel enum ::data_channel.
*/
@@ -291,7 +291,7 @@ void dac_trigger_enable(data_channel dac_channel)
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DAC Channel Trigger Disable.
Disable a digital to analog converter channel external trigger.
@@ -314,14 +314,15 @@ void dac_trigger_disable(data_channel dac_channel)
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Set DAC Channel Trigger Source.
Sets the digital to analog converter trigger source, which can be taken from various
timers, an external trigger or a software trigger.
Sets the digital to analog converter trigger source, which can be taken from
various timers, an external trigger or a software trigger.
@param[in] dac_trig_src u32. Taken from @ref dac_trig2_sel or @ref dac_trig1_sel or
a logical OR of one of each of these to set both channels simultaneously.
@param[in] dac_trig_src u32. Taken from @ref dac_trig2_sel or @ref
dac_trig1_sel or a logical OR of one of each of these to set both channels
simultaneously.
*/
void dac_set_trigger_source(u32 dac_trig_src)
@@ -329,17 +330,17 @@ void dac_set_trigger_source(u32 dac_trig_src)
DAC_CR |= dac_trig_src;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Enable and Set DAC Channel Waveform Generation.
Enable the digital to analog converter waveform generation as either pseudo-random
noise or triangular wave. These signals are superimposed on existing output values
in the DAC output registers.
Enable the digital to analog converter waveform generation as either
pseudo-random noise or triangular wave. These signals are superimposed on
existing output values in the DAC output registers.
@note The DAC trigger must be enabled for this to work.
@param[in] dac_wave_ens u32. Taken from @ref dac_wave1_en or @ref dac_wave2_en or
a logical OR of one of each of these to set both channels simultaneously.
@param[in] dac_wave_ens u32. Taken from @ref dac_wave1_en or @ref dac_wave2_en
or a logical OR of one of each of these to set both channels simultaneously.
*/
void dac_set_waveform_generation(u32 dac_wave_ens)
@@ -347,7 +348,7 @@ void dac_set_waveform_generation(u32 dac_wave_ens)
DAC_CR |= dac_wave_ens;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Disable DAC Channel Waveform Generation.
Disable a digital to analog converter channel superimposed waveform generation.
@@ -370,22 +371,24 @@ void dac_disable_waveform_generation(data_channel dac_channel)
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Set DAC Channel LFSR Mask or Triangle Wave Amplitude.
Sets the digital to analog converter superimposed waveform generation characteristics.
@li If the noise generation mode is set, this sets the length of the PRBS sequence and
hence the amplitude of the output noise signal. Default setting is length 1.
@li If the triangle wave generation mode is set, this sets the amplitude of the
output signal as 2^(n)-1 where n is the parameter value. Default setting is 1.
Sets the digital to analog converter superimposed waveform generation
characteristics. @li If the noise generation mode is set, this sets the length
of the PRBS sequence and hence the amplitude of the output noise signal.
Default setting is length 1. @li If the triangle wave generation mode is set,
this sets the amplitude of the output signal as 2^(n)-1 where n is the
parameter value. Default setting is 1.
@note High amplitude levels of these waveforms can overload the DAC and distort the
signal output.
@note This must be called before enabling the DAC as the settings will then become read-only.
@note High amplitude levels of these waveforms can overload the DAC and distort
the signal output.
@note This must be called before enabling the DAC as the settings will then
become read-only.
@note The DAC trigger must be enabled for this to work.
@param[in] dac_mamp u32. Taken from @ref dac_mamp2 or @ref dac_mamp1 or a logical OR
of one of each of these to set both channels simultaneously.
@param[in] dac_mamp u32. Taken from @ref dac_mamp2 or @ref dac_mamp1 or a
logical OR of one of each of these to set both channels simultaneously.
*/
void dac_set_waveform_characteristics(u32 dac_mamp)
@@ -393,7 +396,7 @@ void dac_set_waveform_characteristics(u32 dac_mamp)
DAC_CR |= dac_mamp;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Load DAC Data Register.
Loads the appropriate digital to analog converter data register with 12 or 8 bit
@@ -407,10 +410,10 @@ data to be converted on a channel. The data can be aligned as follows:
@param[in] dac_channel enum ::data_channel.
*/
void dac_load_data_buffer_single(u16 dac_data, data_align dac_data_format, data_channel dac_channel)
void dac_load_data_buffer_single(u16 dac_data, data_align dac_data_format,
data_channel dac_channel)
{
if (dac_channel == CHANNEL_1)
{
if (dac_channel == CHANNEL_1) {
switch (dac_data_format) {
case RIGHT8:
DAC_DHR8R1 = dac_data;
@@ -422,9 +425,7 @@ void dac_load_data_buffer_single(u16 dac_data, data_align dac_data_format, data_
DAC_DHR12L1 = dac_data;
break;
}
}
else if (dac_channel == CHANNEL_2)
{
} else if (dac_channel == CHANNEL_2) {
switch (dac_data_format) {
case RIGHT8:
DAC_DHR8R2 = dac_data;
@@ -439,7 +440,7 @@ void dac_load_data_buffer_single(u16 dac_data, data_align dac_data_format, data_
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Load DAC Dual Data Register.
Loads the appropriate digital to analog converter dual data register with 12 or
@@ -449,25 +450,29 @@ identically.
@param[in] dac_data1 u16 for channel 1 with appropriate alignment.
@param[in] dac_data2 u16 for channel 2 with appropriate alignment.
@param[in] dac_data_format enum ::data_align. Right or left aligned, and 8 or 12 bit.
@param[in] dac_data_format enum ::data_align. Right or left aligned, and 8 or
12 bit.
*/
void dac_load_data_buffer_dual(u16 dac_data1, u16 dac_data2, data_align dac_data_format)
void dac_load_data_buffer_dual(u16 dac_data1, u16 dac_data2,
data_align dac_data_format)
{
switch (dac_data_format) {
case RIGHT8:
DAC_DHR8RD = ((dac_data1 & MASK8) | ((dac_data2 & MASK8) << 8));
break;
case RIGHT12:
DAC_DHR12RD = ((dac_data1 & MASK12) | ((dac_data2 & MASK12) << 16));
DAC_DHR12RD = ((dac_data1 & MASK12) |
((dac_data2 & MASK12) << 16));
break;
case LEFT12:
DAC_DHR12LD = ((dac_data1 & MASK12) | ((dac_data2 & MASK12) << 16));
DAC_DHR12LD = ((dac_data1 & MASK12) |
((dac_data2 & MASK12) << 16));
break;
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Trigger the DAC by a Software Trigger.
If the trigger source is set to be a software trigger, cause a trigger to occur.

88
lib/stm32/common/dma_common_f13.c
View File

@@ -40,7 +40,7 @@ LGPL License Terms @ref lgpl_license
#include <libopencm3/stm32/dma.h>
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Reset
The channel is disabled and configuration registers are cleared.
@@ -63,7 +63,7 @@ void dma_channel_reset(u32 dma, u8 channel)
DMA_IFCR(dma) |= DMA_IFCR_CIF(channel);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Clear Interrupt Flag
The interrupt flag for the channel is cleared. More than one interrupt for the
@@ -71,7 +71,8 @@ same channel may be cleared by using the logical OR of the interrupt flags.
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] channel unsigned int8. Channel number: @ref dma_ch
@param[in] interrupts unsigned int32. Logical OR of interrupt numbers: @ref dma_if_offset
@param[in] interrupts unsigned int32. Logical OR of interrupt numbers: @ref
dma_if_offset
*/
void dma_clear_interrupt_flags(u32 dma, u8 channel, u32 interrupts)
@@ -81,7 +82,7 @@ void dma_clear_interrupt_flags(u32 dma, u8 channel, u32 interrupts)
DMA_IFCR(dma) = flags;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Read Interrupt Flag
The interrupt flag for the channel is returned.
@@ -99,7 +100,7 @@ bool dma_get_interrupt_flag(u32 dma, u8 channel, u32 interrupt)
return ((DMA_ISR(dma) & flag) > 0);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Enable Memory to Memory Transfers
Memory to memory transfers do not require a trigger to activate each transfer.
@@ -116,7 +117,7 @@ void dma_enable_mem2mem_mode(u32 dma, u8 channel)
DMA_CCR(dma, channel) &= ~DMA_CCR_CIRC;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Set Priority
Channel Priority has four levels: low to very high. This has precedence over the
@@ -133,7 +134,7 @@ void dma_set_priority(u32 dma, u8 channel, u32 prio)
DMA_CCR(dma, channel) |= prio;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Set Memory Word Width
Set the memory word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for
@@ -151,16 +152,17 @@ void dma_set_memory_size(u32 dma, u8 channel, u32 mem_size)
DMA_CCR(dma, channel) |= mem_size;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Set Peripheral Word Width
Set the peripheral word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for
alignment information if the source and destination widths do not match, or
Set the peripheral word width 8 bits, 16 bits, or 32 bits. Refer to datasheet
for alignment information if the source and destination widths do not match, or
if the peripheral does not support byte or half-word writes.
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
@param[in] peripheral_size unsigned int32. Peripheral word width @ref dma_ch_perwidth.
@param[in] peripheral_size unsigned int32. Peripheral word width @ref
dma_ch_perwidth.
*/
void dma_set_peripheral_size(u32 dma, u8 channel, u32 peripheral_size)
@@ -169,7 +171,7 @@ void dma_set_peripheral_size(u32 dma, u8 channel, u32 peripheral_size)
DMA_CCR(dma, channel) |= peripheral_size;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Enable Memory Increment after Transfer
Following each transfer the current memory address is incremented by
@@ -185,7 +187,7 @@ void dma_enable_memory_increment_mode(u32 dma, u8 channel)
DMA_CCR(dma, channel) |= DMA_CCR_MINC;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Disable Memory Increment after Transfer
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@@ -197,7 +199,7 @@ void dma_disable_memory_increment_mode(u32 dma, u8 channel)
DMA_CCR(dma, channel) &= ~DMA_CCR_MINC;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Enable Peripheral Increment after Transfer
Following each transfer the current peripheral address is incremented by
@@ -213,7 +215,7 @@ void dma_enable_peripheral_increment_mode(u32 dma, u8 channel)
DMA_CCR(dma, channel) |= DMA_CCR_PINC;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Disable Peripheral Increment after Transfer
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@@ -225,7 +227,7 @@ void dma_disable_peripheral_increment_mode(u32 dma, u8 channel)
DMA_CCR(dma, channel) &= ~DMA_CCR_PINC;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Enable Memory Circular Mode
After the number of bytes/words to be transferred has been completed, the
@@ -245,7 +247,7 @@ void dma_enable_circular_mode(u32 dma, u8 channel)
DMA_CCR(dma, channel) &= ~DMA_CCR_MEM2MEM;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Enable Transfers from a Peripheral
The data direction is set to read from a peripheral.
@@ -259,7 +261,7 @@ void dma_set_read_from_peripheral(u32 dma, u8 channel)
DMA_CCR(dma, channel) &= ~DMA_CCR_DIR;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Enable Transfers from Memory
The data direction is set to read from memory.
@@ -273,7 +275,7 @@ void dma_set_read_from_memory(u32 dma, u8 channel)
DMA_CCR(dma, channel) |= DMA_CCR_DIR;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Enable Interrupt on Transfer Error
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@@ -285,7 +287,7 @@ void dma_enable_transfer_error_interrupt(u32 dma, u8 channel)
DMA_CCR(dma, channel) |= DMA_CCR_TEIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Disable Interrupt on Transfer Error
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@@ -297,7 +299,7 @@ void dma_disable_transfer_error_interrupt(u32 dma, u8 channel)
DMA_CCR(dma, channel) &= ~DMA_CCR_TEIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Enable Interrupt on Transfer Half Complete
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@@ -309,7 +311,7 @@ void dma_enable_half_transfer_interrupt(u32 dma, u8 channel)
DMA_CCR(dma, channel) |= DMA_CCR_HTIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Disable Interrupt on Transfer Half Complete
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@@ -321,7 +323,7 @@ void dma_disable_half_transfer_interrupt(u32 dma, u8 channel)
DMA_CCR(dma, channel) &= ~DMA_CCR_HTIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Enable Interrupt on Transfer Complete
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@@ -333,7 +335,7 @@ void dma_enable_transfer_complete_interrupt(u32 dma, u8 channel)
DMA_CCR(dma, channel) |= DMA_CCR_TCIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Disable Interrupt on Transfer Complete
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@@ -345,7 +347,7 @@ void dma_disable_transfer_complete_interrupt(u32 dma, u8 channel)
DMA_CCR(dma, channel) &= ~DMA_CCR_TCIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Enable
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@@ -357,10 +359,11 @@ void dma_enable_channel(u32 dma, u8 channel)
DMA_CCR(dma, channel) |= DMA_CCR_EN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Disable
@note The DMA channel registers retain their values when the channel is disabled.
@note The DMA channel registers retain their values when the channel is
disabled.
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
@@ -371,14 +374,14 @@ void dma_disable_channel(u32 dma, u8 channel)
DMA_CCR(dma, channel) &= ~DMA_CCR_EN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Set the Peripheral Address
Set the address of the peripheral register to or from which data is to be transferred.
Refer to the documentation for the specific peripheral.
Set the address of the peripheral register to or from which data is to be
transferred. Refer to the documentation for the specific peripheral.
@note The DMA channel must be disabled before setting this address. This function
has no effect if the channel is enabled.
@note The DMA channel must be disabled before setting this address. This
function has no effect if the channel is enabled.
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
@@ -387,15 +390,16 @@ has no effect if the channel is enabled.
void dma_set_peripheral_address(u32 dma, u8 channel, u32 address)
{
if (!(DMA_CCR(dma, channel) & DMA_CCR_EN))
if (!(DMA_CCR(dma, channel) & DMA_CCR_EN)) {
DMA_CPAR(dma, channel) = (u32) address;
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Set the Base Memory Address
@note The DMA channel must be disabled before setting this address. This function
has no effect if the channel is enabled.
@note The DMA channel must be disabled before setting this address. This
function has no effect if the channel is enabled.
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
@@ -404,19 +408,21 @@ has no effect if the channel is enabled.
void dma_set_memory_address(u32 dma, u8 channel, u32 address)
{
if (!(DMA_CCR(dma, channel) & DMA_CCR_EN))
if (!(DMA_CCR(dma, channel) & DMA_CCR_EN)) {
DMA_CMAR(dma, channel) = (u32) address;
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Set the Transfer Block Size
@note The DMA channel must be disabled before setting this count value. The count
is not changed if the channel is enabled.
@note The DMA channel must be disabled before setting this count value. The
count is not changed if the channel is enabled.
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
@param[in] number unsigned int16. Number of data words to transfer (65535 maximum).
@param[in] number unsigned int16. Number of data words to transfer (65535
maximum).
*/
void dma_set_number_of_data(u32 dma, u8 channel, u16 number)

186
lib/stm32/common/dma_common_f24.c
View File

@@ -1,6 +1,7 @@
/** @addtogroup dma_file
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
@author @htmlonly &copy; @endhtmlonly 2012
Ken Sarkies <ksarkies@internode.on.net>
This library supports the DMA Control System in the STM32F2 and STM32F4
series of ARM Cortex Microcontrollers by ST Microelectronics.
@@ -47,7 +48,7 @@ LGPL License Terms @ref lgpl_license
#include <libopencm3/stm32/dma.h>
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Reset
The specified stream is disabled and configuration registers are cleared.
@@ -72,17 +73,14 @@ void dma_stream_reset(u32 dma, u8 stream)
DMA_SFCR(dma, stream) = 0x21;
/* Reset all stream interrupt flags using the interrupt flag clear register. */
u32 mask = DMA_ISR_MASK(stream);
if (stream < 4)
{
if (stream < 4) {
DMA_LIFCR(dma) |= mask;
}
else
{
} else {
DMA_HIFCR(dma) |= mask;
}
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Clear Interrupt Flag
The interrupt flag for the stream is cleared. More than one interrupt for the
@@ -90,25 +88,25 @@ same stream may be cleared by using the bitwise OR of the interrupt flags.
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
@param[in] interrupts unsigned int32. Bitwise OR of interrupt numbers: @ref dma_if_offset
@param[in] interrupts unsigned int32. Bitwise OR of interrupt numbers: @ref
dma_if_offset
*/
void dma_clear_interrupt_flags(u32 dma, u8 stream, u32 interrupts)
{
/* Get offset to interrupt flag location in stream field */
/* Get offset to interrupt flag location in stream field */
u32 flags = (interrupts << DMA_ISR_OFFSET(stream));
/* First four streams are in low register. Flag clear must be set then reset. */
if (stream < 4)
{
/* First four streams are in low register. Flag clear must be set then
* reset.
*/
if (stream < 4) {
DMA_LIFCR(dma) = flags;
}
else
{
} else {
DMA_HIFCR(dma) = flags;
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Read Interrupt Flag
The interrupt flag for the stream is returned.
@@ -121,15 +119,19 @@ The interrupt flag for the stream is returned.
bool dma_get_interrupt_flag(u32 dma, u8 stream, u32 interrupt)
{
/* get offset to interrupt flag location in stream field.
Assumes stream and interrupt parameters are integers */
/* get offset to interrupt flag location in stream field. Assumes
* stream and interrupt parameters are integers.
*/
u32 flag = (interrupt << DMA_ISR_OFFSET(stream));
/* First four streams are in low register */
if (stream < 4) return ((DMA_LISR(dma) & flag) > 0);
else return ((DMA_HISR(dma) & flag) > 0);
/* First four streams are in low register */
if (stream < 4) {
return ((DMA_LISR(dma) & flag) > 0);
} else {
return ((DMA_HISR(dma) & flag) > 0);
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Enable Transfer Direction
Set peripheral to memory, memory to peripheral or memory to memory. If memory
@@ -146,16 +148,18 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
void dma_set_transfer_mode(u32 dma, u8 stream, u32 direction)
{
u32 reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_DIR_MASK);
/* Disable circular and double buffer modes if memory to memory transfers
are in effect (Direct Mode is automatically disabled by hardware) */
if (direction == DMA_SxCR_DIR_MEM_TO_MEM)
{
/* Disable circular and double buffer modes if memory to memory
* transfers are in effect. (Direct Mode is automatically disabled by
* hardware)
*/
if (direction == DMA_SxCR_DIR_MEM_TO_MEM) {
reg32 &= ~(DMA_SxCR_CIRC | DMA_SxCR_DBM);
}
DMA_SCR(dma, stream) = (reg32 | direction);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Set Priority
Stream Priority has four levels: low to very high. This has precedence over the
@@ -175,7 +179,7 @@ void dma_set_priority(u32 dma, u8 stream, u32 prio)
DMA_SCR(dma, stream) |= prio;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Set Memory Word Width
Set the memory word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for
@@ -190,23 +194,23 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
void dma_set_memory_size(u32 dma, u8 stream, u32 mem_size)
{
DMA_SCR(dma, stream) &= ~(DMA_SxCR_MSIZE_MASK);
DMA_SCR(dma, stream) |= mem_size;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Set Peripheral Word Width
Set the peripheral word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for
alignment information if the source and destination widths do not match, or
Set the peripheral word width 8 bits, 16 bits, or 32 bits. Refer to datasheet
for alignment information if the source and destination widths do not match, or
if the peripheral does not support byte or half-word writes.
Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
@param[in] peripheral_size unsigned int32. Peripheral word width @ref dma_st_perwidth.
@param[in] peripheral_size unsigned int32. Peripheral word width @ref
dma_st_perwidth.
*/
void dma_set_peripheral_size(u32 dma, u8 stream, u32 peripheral_size)
@@ -215,7 +219,7 @@ void dma_set_peripheral_size(u32 dma, u8 stream, u32 peripheral_size)
DMA_SCR(dma, stream) |= peripheral_size;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Enable Memory Increment after Transfer
Following each transfer the current memory address is incremented by
@@ -233,7 +237,7 @@ void dma_enable_memory_increment_mode(u32 dma, u8 stream)
DMA_SCR(dma, stream) |= DMA_SxCR_MINC;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Disable Memory Increment after Transfer
Ensure that the stream is disabled otherwise the setting will not be changed.
@@ -247,7 +251,7 @@ void dma_disable_memory_increment_mode(u32 dma, u8 stream)
DMA_SCR(dma, stream) &= ~DMA_SxCR_MINC;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Enable Variable Sized Peripheral Increment after Transfer
Following each transfer the current peripheral address is incremented by
@@ -266,7 +270,7 @@ void dma_enable_peripheral_increment_mode(u32 dma, u8 stream)
DMA_SCR(dma, stream) = (reg32 & ~DMA_SxCR_PINCOS);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Disable Peripheral Increment after Transfer
Ensure that the stream is disabled otherwise the setting will not be changed.
@@ -280,7 +284,7 @@ void dma_disable_peripheral_increment_mode(u32 dma, u8 stream)
DMA_SCR(dma, stream) &= ~DMA_SxCR_PINC;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Enable Fixed Sized Peripheral Increment after Transfer
Following each transfer the current peripheral address is incremented by
@@ -298,7 +302,7 @@ void dma_enable_fixed_peripheral_increment_mode(u32 dma, u8 stream)
DMA_SCR(dma, stream) |= (DMA_SxCR_PINC | DMA_SxCR_PINCOS);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Enable Memory Circular Mode
After the number of bytes/words to be transferred has been completed, the
@@ -320,7 +324,7 @@ void dma_enable_circular_mode(u32 dma, u8 stream)
DMA_SCR(dma, stream) |= DMA_SxCR_CIRC;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Channel Select
Associate an input channel to the stream. Not every channel is allocated to a
@@ -339,7 +343,7 @@ void dma_channel_select(u32 dma, u8 stream, u32 channel)
DMA_SCR(dma, stream) |= channel;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Set Memory Burst Configuration
Set the memory burst type to none, 4 8 or 16 word length. This is forced to none
@@ -358,7 +362,7 @@ void dma_set_memory_burst(u32 dma, u8 stream, u32 burst)
DMA_SCR(dma, stream) = (reg32 | burst);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Set Peripheral Burst Configuration
Set the memory burst type to none, 4 8 or 16 word length. This is forced to none
@@ -377,11 +381,11 @@ void dma_set_peripheral_burst(u32 dma, u8 stream, u32 burst)
DMA_SCR(dma, stream) = (reg32 | burst);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Set Initial Target Memory
In double buffered mode, set the target memory (M0 or M1) to be used for the first
transfer.
In double buffered mode, set the target memory (M0 or M1) to be used for the
first transfer.
Ensure that the stream is disabled otherwise the setting will not be changed.
@@ -393,17 +397,20 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
void dma_set_initial_target(u32 dma, u8 stream, u8 memory)
{
u32 reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_CT);
if (memory == 1) reg32 |= DMA_SxCR_CT;
if (memory == 1) {
reg32 |= DMA_SxCR_CT;
}
DMA_SCR(dma, stream) = reg32;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Read Current Memory Target
In double buffer mode, return the current memory target (M0 or M1). It is possible
to update the memory pointer in the register that is <b> not </b> currently in
use. An attempt to change the register currently in use will cause the stream
to be disabled and the transfer error flag to be set.
In double buffer mode, return the current memory target (M0 or M1). It is
possible to update the memory pointer in the register that is <b> not </b>
currently in use. An attempt to change the register currently in use will cause
the stream to be disabled and the transfer error flag to be set.
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
@@ -412,11 +419,14 @@ to be disabled and the transfer error flag to be set.
u8 dma_get_target(u32 dma, u8 stream)
{
if (DMA_SCR(dma, stream) & DMA_SxCR_CT) return 1;
if (DMA_SCR(dma, stream) & DMA_SxCR_CT) {
return 1;
}
return 0;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Enable Double Buffer Mode
Double buffer mode is used for memory to/from peripheral transfers only, and in
@@ -436,7 +446,7 @@ void dma_enable_double_buffer_mode(u32 dma, u8 stream)
DMA_SCR(dma, stream) |= DMA_SxCR_DBM;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Disable Double Buffer Mode
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@@ -448,7 +458,7 @@ void dma_disable_double_buffer_mode(u32 dma, u8 stream)
DMA_SCR(dma, stream) &= ~DMA_SxCR_DBM;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Set Peripheral Flow Control
Set the peripheral to control DMA flow. Useful when the number of transfers is
@@ -465,7 +475,7 @@ void dma_set_peripheral_flow_control(u32 dma, u8 stream)
DMA_SCR(dma, stream) |= DMA_SxCR_PFCTRL;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Set DMA Flow Control
Set the DMA controller to control DMA flow. This is the default.
@@ -481,7 +491,7 @@ void dma_set_dma_flow_control(u32 dma, u8 stream)
DMA_SCR(dma, stream) &= ~DMA_SxCR_PFCTRL;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Enable Interrupt on Transfer Error
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@@ -494,7 +504,7 @@ void dma_enable_transfer_error_interrupt(u32 dma, u8 stream)
DMA_SCR(dma, stream) |= DMA_SxCR_TEIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Disable Interrupt on Transfer Error
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@@ -506,7 +516,7 @@ void dma_disable_transfer_error_interrupt(u32 dma, u8 stream)
DMA_SCR(dma, stream) &= ~DMA_SxCR_TEIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Enable Interrupt on Transfer Half Complete
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@@ -519,7 +529,7 @@ void dma_enable_half_transfer_interrupt(u32 dma, u8 stream)
DMA_SCR(dma, stream) |= DMA_SxCR_HTIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Disable Interrupt on Transfer Half Complete
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@@ -531,7 +541,7 @@ void dma_disable_half_transfer_interrupt(u32 dma, u8 stream)
DMA_SCR(dma, stream) &= ~DMA_SxCR_HTIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Enable Interrupt on Transfer Complete
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@@ -544,7 +554,7 @@ void dma_enable_transfer_complete_interrupt(u32 dma, u8 stream)
DMA_SCR(dma, stream) |= DMA_SxCR_TCIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Disable Interrupt on Transfer Complete
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@@ -556,7 +566,7 @@ void dma_disable_transfer_complete_interrupt(u32 dma, u8 stream)
DMA_SCR(dma, stream) &= ~DMA_SxCR_TCIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Enable Interrupt on Direct Mode Error
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@@ -569,7 +579,7 @@ void dma_enable_direct_mode_error_interrupt(u32 dma, u8 stream)
DMA_SCR(dma, stream) |= DMA_SxCR_DMEIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Disable Interrupt on Direct Mode Error
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@@ -581,7 +591,7 @@ void dma_disable_direct_mode_error_interrupt(u32 dma, u8 stream)
DMA_SCR(dma, stream) &= ~DMA_SxCR_DMEIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Enable Interrupt on FIFO Error
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@@ -594,7 +604,7 @@ void dma_enable_fifo_error_interrupt(u32 dma, u8 stream)
DMA_SFCR(dma, stream) |= DMA_SxFCR_FEIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Disable Interrupt on FIFO Error
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@@ -606,7 +616,7 @@ void dma_disable_fifo_error_interrupt(u32 dma, u8 stream)
DMA_SFCR(dma, stream) &= ~DMA_SxFCR_FEIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Get FIFO Status
Status of FIFO (empty. full or partial filled states) is returned. This has no
@@ -619,10 +629,10 @@ meaning if direct mode is enabled (as the FIFO is not used).
u32 dma_fifo_status(u32 dma, u8 stream)
{
return (DMA_SFCR(dma, stream) & DMA_SxFCR_FS_MASK);
return DMA_SFCR(dma, stream) & DMA_SxFCR_FS_MASK;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Enable Direct Mode
Direct mode is the default. Data is transferred as soon as a DMA request is
@@ -638,7 +648,7 @@ void dma_enable_direct_mode(u32 dma, u8 stream)
DMA_SFCR(dma, stream) &= ~DMA_SxFCR_DMDIS;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Enable FIFO Mode
Data is transferred via a FIFO.
@@ -652,7 +662,7 @@ void dma_enable_fifo_mode(u32 dma, u8 stream)
DMA_SFCR(dma, stream) |= DMA_SxFCR_DMDIS;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Set FIFO Threshold
This is the filled level at which data is transferred out of the FIFO to the
@@ -669,7 +679,7 @@ void dma_set_fifo_threshold(u32 dma, u8 stream, u32 threshold)
DMA_SFCR(dma, stream) = (reg32 | threshold);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Enable
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@@ -681,7 +691,7 @@ void dma_enable_stream(u32 dma, u8 stream)
DMA_SCR(dma, stream) |= DMA_SxCR_EN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Disable
@note The DMA stream registers retain their values when the stream is disabled.
@@ -695,11 +705,11 @@ void dma_disable_stream(u32 dma, u8 stream)
DMA_SCR(dma, stream) &= ~DMA_SxCR_EN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Set the Peripheral Address
Set the address of the peripheral register to or from which data is to be transferred.
Refer to the documentation for the specific peripheral.
Set the address of the peripheral register to or from which data is to be
transferred. Refer to the documentation for the specific peripheral.
@note The DMA stream must be disabled before setting this address. This function
has no effect if the stream is enabled.
@@ -711,11 +721,12 @@ has no effect if the stream is enabled.
void dma_set_peripheral_address(u32 dma, u8 stream, u32 address)
{
if (!(DMA_SCR(dma, stream) & DMA_SxCR_EN))
if (!(DMA_SCR(dma, stream) & DMA_SxCR_EN)) {
DMA_SPAR(dma, stream) = (u32 *) address;
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Set the Base Memory Address 0
Set the address pointer to the memory location for DMA transfers. The DMA stream
@@ -733,11 +744,13 @@ This is the default base memory address used in direct mode.
void dma_set_memory_address(u32 dma, u8 stream, u32 address)
{
u32 reg32 = DMA_SCR(dma, stream);
if ( !(reg32 & DMA_SxCR_EN) || ((reg32 & DMA_SxCR_CT) && (reg32 & DMA_SxCR_DBM)) )
if (!(reg32 & DMA_SxCR_EN) ||
((reg32 & DMA_SxCR_CT) && (reg32 & DMA_SxCR_DBM))) {
DMA_SM0AR(dma, stream) = (u32 *) address;
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Set the Base Memory Address 1
Set the address pointer to the memory location for DMA transfers. The DMA stream
@@ -753,11 +766,13 @@ to change this in double buffer mode when the current target is memory area 0
void dma_set_memory_address_1(u32 dma, u8 stream, u32 address)
{
u32 reg32 = DMA_SCR(dma, stream);
if ( !(reg32 & DMA_SxCR_EN) || (!(reg32 & DMA_SxCR_CT) && (reg32 & DMA_SxCR_DBM)) )
if (!(reg32 & DMA_SxCR_EN) ||
(!(reg32 & DMA_SxCR_CT) && (reg32 & DMA_SxCR_DBM))) {
DMA_SM1AR(dma, stream) = (u32 *) address;
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Set the Transfer Block Size
@note The DMA stream must be disabled before setting this count value. The count
@@ -765,7 +780,8 @@ is not changed if the stream is enabled.
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
@param[in] number unsigned int16. Number of data words to transfer (65535 maximum).
@param[in] number unsigned int16. Number of data words to transfer (65535
maximum).
*/
void dma_set_number_of_data(u32 dma, u8 stream, u16 number)

22
lib/stm32/common/flash_common_f24.c
View File

@@ -148,8 +148,7 @@ void flash_lock_option_bytes(void)
void flash_wait_for_last_operation(void)
{
while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY)
;
while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY);
}
void flash_program_double_word(u32 address, u64 data)
@@ -218,13 +217,15 @@ void flash_program_byte(u32 address, u8 data)
FLASH_CR &= ~FLASH_CR_PG; /* Disable the PG bit. */
}
void flash_program(u32 address, u8* data, u32 len)
void flash_program(u32 address, u8 *data, u32 len)
{
/* TODO: Use dword and word size program operations where possible for turbo
* speed. */
u32 i;
for (i=0; i<len; i++)
flash_program_byte(address+i, data[i]);
/* TODO: Use dword and word size program operations where possible for
* turbo speed.
*/
u32 i;
for (i = 0; i < len; i++) {
flash_program_byte(address+i, data[i]);
}
}
void flash_erase_sector(u8 sector, u32 program_size)
@@ -258,10 +259,11 @@ void flash_program_option_bytes(u32 data)
{
flash_wait_for_last_operation();
if (FLASH_OPTCR & FLASH_OPTCR_OPTLOCK)
if (FLASH_OPTCR & FLASH_OPTCR_OPTLOCK) {
flash_unlock_option_bytes();
}
FLASH_OPTCR = data & ~0x3;
FLASH_OPTCR |= FLASH_OPTCR_OPTSTRT; /* Enable option byte programming. */
FLASH_OPTCR |= FLASH_OPTCR_OPTSTRT; /* Enable option byte prog. */
flash_wait_for_last_operation();
}

46
lib/stm32/common/gpio_common_all.c
View File

@@ -23,69 +23,73 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#define WEAK __attribute__ ((weak))
#define WEAK __attribute__((weak))
#include <libopencm3/stm32/gpio.h>
/**@{*/
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Set a Group of Pins Atomic
Set one or more pins of the given GPIO port to 1 in an atomic operation.
@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id
If multiple pins are to be changed, use logical OR '|' to separate them.
If multiple pins are to be changed, use logical OR '|' to separate
them.
*/
void gpio_set(u32 gpioport, u16 gpios)
{
GPIO_BSRR(gpioport) = gpios;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Clear a Group of Pins Atomic
Clear one or more pins of the given GPIO port to 0 in an atomic operation.
@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id
If multiple pins are to be changed, use logical OR '|' to separate them.
If multiple pins are to be changed, use logical OR '|' to separate
them.
*/
void gpio_clear(u32 gpioport, u16 gpios)
{
GPIO_BSRR(gpioport) = (gpios << 16);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Read a Group of Pins.
@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id
If multiple pins are to be read, use logical OR '|' to separate them.
@return Unsigned int16 value of the pin values. The bit position of the pin value
returned corresponds to the pin number.
If multiple pins are to be read, use logical OR '|' to separate
them.
@return Unsigned int16 value of the pin values. The bit position of the pin
value returned corresponds to the pin number.
*/
u16 gpio_get(u32 gpioport, u16 gpios)
{
return gpio_port_read(gpioport) & gpios;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Toggle a Group of Pins
Toggle one or more pins of the given GPIO port. This is not an atomic operation.
@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id
If multiple pins are to be changed, use logical OR '|' to separate them.
If multiple pins are to be changed, use logical OR '|' to separate
them.
*/
void gpio_toggle(u32 gpioport, u16 gpios)
{
GPIO_ODR(gpioport) ^= gpios;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Read from a Port
Read the current value of the given GPIO port. Only the lower 16 bits contain
@@ -99,7 +103,7 @@ u16 gpio_port_read(u32 gpioport)
return (u16)GPIO_IDR(gpioport);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Write to a Port
Write a value to the given GPIO port.
@@ -112,15 +116,17 @@ void gpio_port_write(u32 gpioport, u16 data)
GPIO_ODR(gpioport) = data;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Lock the Configuration of a Group of Pins
The configuration of one or more pins of the given GPIO port is locked. There is
no mechanism to unlock these via software. Unlocking occurs at the next reset.
The configuration of one or more pins of the given GPIO port is locked. There
is no mechanism to unlock these via software. Unlocking occurs at the next
reset.
@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id
If multiple pins are to be locked, use logical OR '|' to separate them.
If multiple pins are to be locked, use logical OR '|' to separate
them.
*/
void gpio_port_config_lock(u32 gpioport, u16 gpios)
{
@@ -133,8 +139,10 @@ void gpio_port_config_lock(u32 gpioport, u16 gpios)
reg32 = GPIO_LCKR(gpioport); /* Read LCKK. */
reg32 = GPIO_LCKR(gpioport); /* Read LCKK again. */
/* Tell the compiler the variable is actually used. It will get optimized out anyways. */
reg32 = reg32;
/* Tell the compiler the variable is actually used. It will get
* optimized out anyways.
*/
reg32 = reg32;
/* If (reg32 & GPIO_LCKK) is true, the lock is now active. */
}

89
lib/stm32/common/gpio_common_f24.c
View File

@@ -1,20 +1,22 @@
/** @addtogroup gpio_file
@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
@author @htmlonly &copy; @endhtmlonly 2009
Uwe Hermann <uwe@hermann-uwe.de>
@author @htmlonly &copy; @endhtmlonly 2012
Ken Sarkies <ksarkies@internode.on.net>
Each I/O port has 16 individually configurable bits. Many I/O pins share GPIO
functionality with a number of alternate functions and must be configured to the
alternate function mode if these are to be accessed. A feature is available to
remap alternative functions to a limited set of alternative pins in the event
of a clash of requirements.
functionality with a number of alternate functions and must be configured to
the alternate function mode if these are to be accessed. A feature is available
to remap alternative functions to a limited set of alternative pins in the
event of a clash of requirements.
The data registers associated with each port for input and output are 32 bit with
the upper 16 bits unused. The output buffer must be written as a 32 bit word, but
individual bits may be set or reset separately in atomic operations to avoid race
conditions during interrupts. Bits may also be individually locked to prevent
accidental configuration changes. Once locked the configuration cannot be changed
until after the next reset.
The data registers associated with each port for input and output are 32 bit
with the upper 16 bits unused. The output buffer must be written as a 32 bit
word, but individual bits may be set or reset separately in atomic operations
to avoid race conditions during interrupts. Bits may also be individually
locked to prevent accidental configuration changes. Once locked the
configuration cannot be changed until after the next reset.
Each port bit can be configured as analog or digital input, the latter can be
floating or pulled up or down. As outputs they can be configured as either
@@ -29,9 +31,9 @@ Example 1: Push-pull digital output actions with pullup on ports C2 and C9
@code
gpio_mode_setup(GPIOC, GPIO_MODE_OUTPUT,
GPIO_PUPD_PULLUP, GPIO2 | GPIO9);
GPIO_PUPD_PULLUP, GPIO2 | GPIO9);
gpio_output_options(GPIOC, GPIO_OTYPE_PP,
GPIO_OSPEED_25MHZ, GPIO2 | GPIO9);
GPIO_OSPEED_25MHZ, GPIO2 | GPIO9);
gpio_set(GPIOC, GPIO2 | GPIO9);
gpio_clear(GPIOC, GPIO2);
gpio_toggle(GPIOC, GPIO2 | GPIO9);
@@ -42,7 +44,7 @@ Example 2: Digital input on port C12 with pullup
@code
gpio_mode_setup(GPIOC, GPIO_MODE_INPUT,
GPIO_PUPD_PULLUP, GPIO12);
GPIO_PUPD_PULLUP, GPIO12);
reg16 = gpio_port_read(GPIOC);
@endcode
@@ -70,7 +72,7 @@ Example 2: Digital input on port C12 with pullup
#include <libopencm3/stm32/gpio.h>
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Set GPIO Pin Mode
Sets the Pin Direction and Analog/Digital Mode, and Output Pin Pullup,
@@ -78,9 +80,11 @@ for a set of GPIO pins on a given GPIO port.
@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
@param[in] mode Unsigned int8. Pin mode @ref gpio_mode
@param[in] pull_up_down Unsigned int8. Pin pullup/pulldown configuration @ref gpio_pup
@param[in] pull_up_down Unsigned int8. Pin pullup/pulldown configuration @ref
gpio_pup
@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id
If multiple pins are to be set, use bitwise OR '|' to separate them.
If multiple pins are to be set, use bitwise OR '|' to separate
them.
*/
void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios)
{
@@ -95,8 +99,9 @@ void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios)
pupd = GPIO_PUPDR(gpioport);
for (i = 0; i < 16; i++) {
if (!((1 << i) & gpios))
if (!((1 << i) & gpios)) {
continue;
}
moder &= ~GPIO_MODE_MASK(i);
moder |= GPIO_MODE(i, mode);
@@ -109,33 +114,37 @@ void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios)
GPIO_PUPDR(gpioport) = pupd;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Set GPIO Output Options
When the pin is set to output mode, this sets the configuration (analog/digital and
open drain/push pull) and speed, for a set of GPIO pins on a given GPIO port.
When the pin is set to output mode, this sets the configuration (analog/digital
and open drain/push pull) and speed, for a set of GPIO pins on a given GPIO
port.
@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
@param[in] otype Unsigned int8. Pin output type @ref gpio_output_type
@param[in] speed Unsigned int8. Pin speed @ref gpio_speed
@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id
If multiple pins are to be set, use bitwise OR '|' to separate them.
If multiple pins are to be set, use bitwise OR '|' to separate
them.
*/
void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios)
{
u16 i;
u32 ospeedr;
if (otype == 0x1)
if (otype == 0x1) {
GPIO_OTYPER(gpioport) |= gpios;
}
else
GPIO_OTYPER(gpioport) &= ~gpios;
ospeedr = GPIO_OSPEEDR(gpioport);
for (i = 0; i < 16; i++) {
if (!((1 << i) & gpios))
if (!((1 << i) & gpios)) {
continue;
}
ospeedr &= ~GPIO_OSPEED_MASK(i);
ospeedr |= GPIO_OSPEED(i, speed);
}
@@ -143,22 +152,26 @@ void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios)
GPIO_OSPEEDR(gpioport) = ospeedr;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Set GPIO Alternate Function Selection
Set the alternate function mapping number for each pin. Most pins have alternate
functions associated with them. When set to AF mode, a pin may be used for one of
its allocated alternate functions selected by the number given here. To determine
the number to be used for the desired function refer to the individual datasheet
for the particular device. A table is given under the Pin Selection chapter.
Set the alternate function mapping number for each pin. Most pins have
alternate functions associated with them. When set to AF mode, a pin may be
used for one of its allocated alternate functions selected by the number given
here. To determine the number to be used for the desired function refer to the
individual datasheet for the particular device. A table is given under the Pin
Selection chapter.
Note that a number of pins may be set but only with a single AF number. In practice
this would rarely be useful as each pin is likely to require a different number.
Note that a number of pins may be set but only with a single AF number. In
practice this would rarely be useful as each pin is likely to require a
different number.
@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
@param[in] alt_func_num Unsigned int8. Pin alternate function number @ref gpio_af_num
@param[in] alt_func_num Unsigned int8. Pin alternate function number @ref
gpio_af_num
@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id
If multiple pins are to be set, use bitwise OR '|' to separate them.
If multiple pins are to be set, use bitwise OR '|' to separate
them.
*/
void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios)
{
@@ -169,15 +182,17 @@ void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios)
afrh = GPIO_AFRH(gpioport);
for (i = 0; i < 8; i++) {
if (!((1 << i) & gpios))
if (!((1 << i) & gpios)) {
continue;
}
afrl &= ~GPIO_AFR_MASK(i);
afrl |= GPIO_AFR(i, alt_func_num);
}
for (i = 8; i < 16; i++) {
if (!((1 << i) & gpios))
if (!((1 << i) & gpios)) {
continue;
}
afrh &= ~GPIO_AFR_MASK(i - 8);
afrh |= GPIO_AFR(i - 8, alt_func_num);
}

28
lib/stm32/common/hash_common_f24.c
View File

@@ -1,6 +1,7 @@
/** @addtogroup hash_file
@author @htmlonly &copy; @endhtmlonly 2013 Mikhail Avkhimenia <mikhail@avkhimenia.net>
@author @htmlonly &copy; @endhtmlonly 2013
Mikhail Avkhimenia <mikhail@avkhimenia.net>
This library supports the HASH processor in the STM32F2 and STM32F4
series of ARM Cortex Microcontrollers by ST Microelectronics.
@@ -31,7 +32,7 @@ LGPL License Terms @ref lgpl_license
#include <libopencm3/stm32/hash.h>
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief HASH Set Mode
Sets up the specified mode - either HASH or HMAC.
@@ -45,7 +46,7 @@ void hash_set_mode(u8 mode)
HASH_CR |= mode;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief HASH Set Algorithm
Sets up the specified algorithm - either MD5 or SHA1.
@@ -59,7 +60,7 @@ void hash_set_algorithm(u8 algorithm)
HASH_CR |= algorithm;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief HASH Set Data Type
Sets up the specified data type: 32Bit, 16Bit, 8Bit, Bitstring.
@@ -70,10 +71,10 @@ Sets up the specified data type: 32Bit, 16Bit, 8Bit, Bitstring.
void hash_set_data_type(u8 datatype)
{
HASH_CR &= ~HASH_CR_DATATYPE;
HASH_CR |= datatype;
HASH_CR |= datatype;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief HASH Set Key Length
Sets up the specified key length: Long, Short.
@@ -84,10 +85,10 @@ Sets up the specified key length: Long, Short.
void hash_set_key_length(u8 keylength)
{
HASH_CR &= ~HASH_CR_LKEY;
HASH_CR |= keylength;
HASH_CR |= keylength;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief HASH Set Last Word Valid Bits
Specifies the number of valid bits in the last word.
@@ -101,7 +102,7 @@ void hash_set_last_word_valid_bits(u8 validbits)
HASH_STR |= 32 - validbits;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief HASH Init
Initializes the HASH processor.
@@ -113,7 +114,7 @@ void hash_init()
HASH_CR |= HASH_CR_INIT;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief HASH Add data
Puts data into the HASH processor's queue.
@@ -126,7 +127,7 @@ void hash_add_data(u32 data)
HASH_DIN = data;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief HASH Digest
Starts the processing of the last data block.
@@ -138,7 +139,7 @@ void hash_digest()
HASH_STR |= HASH_STR_DCAL;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief HASH Get Hash Result
Makes a copy of the resulting hash.
@@ -154,6 +155,7 @@ void hash_get_result(u32 *data)
data[2] = HASH_HR[2];
data[3] = HASH_HR[3];
if ((HASH_CR & HASH_CR_ALGO) == HASH_ALGO_SHA1)
if ((HASH_CR & HASH_CR_ALGO) == HASH_ALGO_SHA1) {
data[4] = HASH_HR[4];
}
}

83
lib/stm32/common/i2c_common_all.c
View File

@@ -1,7 +1,9 @@
/** @addtogroup i2c_file
@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
@author @htmlonly &copy; @endhtmlonly 2010
Thomas Otto <tommi@viadmin.org>
@author @htmlonly &copy; @endhtmlonly 2012
Ken Sarkies <ksarkies@internode.on.net>
Devices can have up to two I2C peripherals. The peripherals support SMBus and
PMBus variants.
@@ -38,11 +40,11 @@ register access, Error conditions
/**@{*/
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief I2C Reset.
The I2C peripheral and all its associated configuration registers are placed in the
reset condition. The reset is effected via the RCC peripheral reset system.
The I2C peripheral and all its associated configuration registers are placed in
the reset condition. The reset is effected via the RCC peripheral reset system.
@param[in] i2c Unsigned int32. I2C peripheral identifier @ref i2c_reg_base.
*/
@@ -61,7 +63,7 @@ void i2c_reset(u32 i2c)
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief I2C Peripheral Enable.
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
@@ -72,7 +74,7 @@ void i2c_peripheral_enable(u32 i2c)
I2C_CR1(i2c) |= I2C_CR1_PE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief I2C Peripheral Disable.
This must not be reset while in Master mode until a communication has finished.
@@ -86,7 +88,7 @@ void i2c_peripheral_disable(u32 i2c)
I2C_CR1(i2c) &= ~I2C_CR1_PE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief I2C Send Start Condition.
If in Master mode this will cause a restart condition to occur at the end of the
@@ -101,7 +103,7 @@ void i2c_send_start(u32 i2c)
I2C_CR1(i2c) |= I2C_CR1_START;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief I2C Send Stop Condition.
After the current byte transfer this will initiate a stop condition if in Master
@@ -115,7 +117,7 @@ void i2c_send_stop(u32 i2c)
I2C_CR1(i2c) |= I2C_CR1_STOP;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief I2C Clear Stop Flag.
Clear the "Send Stop" flag in the I2C config register
@@ -127,7 +129,7 @@ void i2c_clear_stop(u32 i2c)
I2C_CR1(i2c) &= ~I2C_CR1_STOP;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief I2C Set the 7 bit Slave Address for the Peripheral.
This sets an address for Slave mode operation, in 7 bit form.
@@ -143,7 +145,7 @@ void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave)
I2C_OAR1(i2c) |= (1 << 14); /* Datasheet: always keep 1 by software. */
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief I2C Set the 10 bit Slave Address for the Peripheral.
This sets an address for Slave mode operation, in 10 bit form.
@@ -159,7 +161,7 @@ void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave)
I2C_OAR1(i2c) = (u16)(I2C_OAR1_ADDMODE | slave);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief I2C Set Fast Mode.
Set the clock frequency to the high clock rate mode (up to 400kHz). The actual
@@ -173,11 +175,11 @@ void i2c_set_fast_mode(u32 i2c)
I2C_CCR(i2c) |= I2C_CCR_FS;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief I2C Set Standard Mode.
Set the clock frequency to the standard clock rate mode (up to 100kHz). The actual
clock frequency must be set with @ref i2c_set_clock_frequency
Set the clock frequency to the standard clock rate mode (up to 100kHz). The
actual clock frequency must be set with @ref i2c_set_clock_frequency
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
@@ -187,12 +189,13 @@ void i2c_set_standard_mode(u32 i2c)
I2C_CCR(i2c) &= ~I2C_CCR_FS;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief I2C Set Peripheral Clock Frequency.
Set the peripheral clock frequency: 2MHz to 36MHz (the APB frequency). Note that
this is <b> not </b> the I2C bus clock. This is set in conjunction with the Clock
Control register to generate the Master bus clock, see @ref i2c_set_ccr
Set the peripheral clock frequency: 2MHz to 36MHz (the APB frequency). Note
that this is <b> not </b> the I2C bus clock. This is set in conjunction with
the Clock Control register to generate the Master bus clock, see @ref
i2c_set_ccr
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
@param[in] freq Unsigned int8. Clock Frequency Setting @ref i2c_clock.
@@ -206,7 +209,7 @@ void i2c_set_clock_frequency(u32 i2c, u8 freq)
I2C_CR2(i2c) = reg16;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief I2C Set Bus Clock Frequency.
Set the bus clock frequency. This is a 12 bit number (0...4095) calculated
@@ -229,7 +232,7 @@ void i2c_set_ccr(u32 i2c, u16 freq)
I2C_CCR(i2c) = reg16;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief I2C Set the Rise Time.
Set the maximum rise time on the bus according to the I2C specification, as 1
@@ -247,12 +250,13 @@ void i2c_set_trise(u32 i2c, u16 trise)
I2C_TRISE(i2c) = trise;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief I2C Send the 7-bit Slave Address.
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
@param[in] slave Unsigned int16. Slave address 0...1023.
@param[in] readwrite Unsigned int8. Single bit to instruct slave to receive or send @ref i2c_rw.
@param[in] readwrite Unsigned int8. Single bit to instruct slave to receive or
send @ref i2c_rw.
*/
void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite)
@@ -260,7 +264,7 @@ void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite)
I2C_DR(i2c) = (u8)((slave << 1) | readwrite);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief I2C Send Data.
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
@@ -272,7 +276,7 @@ void i2c_send_data(u32 i2c, u8 data)
I2C_DR(i2c) = data;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief I2C Get Data.
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
@@ -282,7 +286,7 @@ uint8_t i2c_get_data(u32 i2c)
return I2C_DR(i2c) & 0xff;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief I2C Enable Interrupt
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
@@ -293,7 +297,7 @@ void i2c_enable_interrupt(u32 i2c, u32 interrupt)
I2C_CR2(i2c) |= interrupt;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief I2C Disable Interrupt
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
@@ -304,7 +308,7 @@ void i2c_disable_interrupt(u32 i2c, u32 interrupt)
I2C_CR2(i2c) &= ~interrupt;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief I2C Enable ACK
Enables acking of own 7/10 bit address
@@ -315,7 +319,7 @@ void i2c_enable_ack(u32 i2c)
I2C_CR1(i2c) |= I2C_CR1_ACK;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief I2C Disable ACK
Disables acking of own 7/10 bit address
@@ -326,7 +330,7 @@ void i2c_disable_ack(u32 i2c)
I2C_CR1(i2c) &= ~I2C_CR1_ACK;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief I2C NACK Next Byte
Causes the I2C controller to NACK the reception of the next byte
@@ -337,7 +341,7 @@ void i2c_nack_next(u32 i2c)
I2C_CR1(i2c) |= I2C_CR1_POS;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief I2C NACK Next Byte
Causes the I2C controller to NACK the reception of the current byte
@@ -349,7 +353,7 @@ void i2c_nack_current(u32 i2c)
I2C_CR1(i2c) &= ~I2C_CR1_POS;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief I2C Set clock duty cycle
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
@@ -357,13 +361,14 @@ void i2c_nack_current(u32 i2c)
*/
void i2c_set_dutycycle(u32 i2c, u32 dutycycle)
{
if (dutycycle == I2C_CCR_DUTY_DIV2)
if (dutycycle == I2C_CCR_DUTY_DIV2) {
I2C_CCR(i2c) &= ~I2C_CCR_DUTY;
else
} else {
I2C_CCR(i2c) |= I2C_CCR_DUTY;
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief I2C Enable DMA
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
@@ -373,7 +378,7 @@ void i2c_enable_dma(u32 i2c)
I2C_CR2(i2c) |= I2C_CR2_DMAEN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief I2C Disable DMA
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
@@ -383,7 +388,7 @@ void i2c_disable_dma(u32 i2c)
I2C_CR2(i2c) &= ~I2C_CR2_DMAEN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief I2C Set DMA last transfer
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
@@ -393,7 +398,7 @@ void i2c_set_dma_last_transfer(u32 i2c)
I2C_CR2(i2c) |= I2C_CR2_LAST;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief I2C Clear DMA last transfer
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.

66
lib/stm32/common/iwdg_common_all.c
View File

@@ -42,7 +42,7 @@ relevant bit is not set, the IWDG timer must be enabled by software.
#define COUNT_LENGTH 12
#define COUNT_MASK ((1 << COUNT_LENGTH)-1)
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief IWDG Enable Watchdog Timer
The watchdog timer is started. The timeout period defaults to 512 milliseconds
@@ -55,7 +55,7 @@ void iwdg_start(void)
IWDG_KR = IWDG_KR_START;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief IWDG Set Period in Milliseconds
The countdown period is converted into count and prescale values. The maximum
@@ -66,27 +66,41 @@ A delay of up to 5 clock cycles of the LSI clock (about 156 microseconds)
can occasionally occur if the prescale or preload registers are currently busy
loading a previous value.
@param[in] period u32 Period in milliseconds (< 32760) from a watchdog reset until
a system reset is issued.
@param[in] period u32 Period in milliseconds (< 32760) from a watchdog reset
until a system reset is issued.
*/
void iwdg_set_period_ms(u32 period)
{
u32 count, prescale, reload, exponent;
/* Set the count to represent ticks of the 32kHz LSI clock */
u32 count, prescale, reload, exponent;
/* Set the count to represent ticks of the 32kHz LSI clock */
count = (period << 5);
/* Strip off the first 12 bits to get the prescale value required */
/* Strip off the first 12 bits to get the prescale value required */
prescale = (count >> 12);
if (prescale > 256) {exponent = IWDG_PR_DIV256; reload = COUNT_MASK;}
else if (prescale > 128) {exponent = IWDG_PR_DIV256; reload = (count >> 8);}
else if (prescale > 64) {exponent = IWDG_PR_DIV128; reload = (count >> 7);}
else if (prescale > 32) {exponent = IWDG_PR_DIV64; reload = (count >> 6);}
else if (prescale > 16) {exponent = IWDG_PR_DIV32; reload = (count >> 5);}
else if (prescale > 8) {exponent = IWDG_PR_DIV16; reload = (count >> 4);}
else if (prescale > 4) {exponent = IWDG_PR_DIV8; reload = (count >> 3);}
else {exponent = IWDG_PR_DIV4; reload = (count >> 2);}
/* Avoid the undefined situation of a zero count */
if (count == 0) count = 1;
if (prescale > 256) {
exponent = IWDG_PR_DIV256; reload = COUNT_MASK;
} else if (prescale > 128) {
exponent = IWDG_PR_DIV256; reload = (count >> 8);
} else if (prescale > 64) {
exponent = IWDG_PR_DIV128; reload = (count >> 7);
} else if (prescale > 32) {
exponent = IWDG_PR_DIV64; reload = (count >> 6);
} else if (prescale > 16) {
exponent = IWDG_PR_DIV32; reload = (count >> 5);
} else if (prescale > 8) {
exponent = IWDG_PR_DIV16; reload = (count >> 4);
} else if (prescale > 4) {
exponent = IWDG_PR_DIV8; reload = (count >> 3);
} else {
exponent = IWDG_PR_DIV4; reload = (count >> 2);
}
/* Avoid the undefined situation of a zero count */
if (count == 0) {
count = 1;
}
while (iwdg_prescaler_busy());
IWDG_KR = IWDG_KR_UNLOCK;
@@ -96,31 +110,31 @@ u32 count, prescale, reload, exponent;
IWDG_RLR = (reload & COUNT_MASK);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief IWDG Get Reload Register Status
@returns boolean: TRUE if the reload register is busy and unavailable for loading
a new count value.
@returns boolean: TRUE if the reload register is busy and unavailable for
loading a new count value.
*/
bool iwdg_reload_busy(void)
{
return (IWDG_SR & IWDG_SR_RVU);
return IWDG_SR & IWDG_SR_RVU;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief IWDG Get Prescaler Register Status
@returns boolean: TRUE if the prescaler register is busy and unavailable for loading
a new period value.
@returns boolean: TRUE if the prescaler register is busy and unavailable for
loading a new period value.
*/
bool iwdg_prescaler_busy(void)
{
return (IWDG_SR & IWDG_SR_PVU);
return IWDG_SR & IWDG_SR_PVU;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief IWDG reset Watchdog Timer
The watchdog timer is reset. The counter restarts from the value in the reload

5
lib/stm32/common/pwr_common_all.c
View File

@@ -1,6 +1,7 @@
/** @addtogroup pwr-file PWR
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
@author @htmlonly &copy; @endhtmlonly 2012
Ken Sarkies <ksarkies@internode.on.net>
*/
/*
@@ -199,7 +200,7 @@ cleared by software (see @ref pwr_clear_wakeup_flag).
bool pwr_get_wakeup_flag(void)
{
return (PWR_CSR & PWR_CSR_WUF);
return PWR_CSR & PWR_CSR_WUF;
}
/**@}*/

62
lib/stm32/common/rtc_common_bcd.c
View File

@@ -33,7 +33,8 @@
This sets the RTC synchronous and asynchronous prescalars.
*/
void rtc_set_prescaler(u32 sync, u32 async) {
void rtc_set_prescaler(u32 sync, u32 async)
{
/*
* Even if only one of the two fields needs to be changed,
* 2 separate write accesses must be performed to the RTC_PRER register.
@@ -48,16 +49,16 @@ void rtc_set_prescaler(u32 sync, u32 async) {
Time and Date are accessed through shadow registers which must be synchronized
*/
void rtc_wait_for_synchro(void) {
void rtc_wait_for_synchro(void)
{
/* Unlock RTC registers */
RTC_WPR = 0xca;
RTC_WPR = 0x53;
RTC_ISR &= ~(RTC_ISR_RSF);
while (!(RTC_ISR & RTC_ISR_RSF)) {
;
}
while (!(RTC_ISR & RTC_ISR_RSF));
/* disable write protection again */
RTC_WPR = 0xff;
}
@@ -66,7 +67,8 @@ void rtc_wait_for_synchro(void) {
/** @brief Unlock write access to the RTC registers
*/
void rtc_unlock(void) {
void rtc_unlock(void)
{
RTC_WPR = 0xca;
RTC_WPR = 0x53;
}
@@ -75,7 +77,8 @@ void rtc_unlock(void) {
/** @brief Lock write access to the RTC registers
*/
void rtc_lock(void) {
void rtc_lock(void)
{
RTC_WPR = 0xff;
}
@@ -83,31 +86,38 @@ void rtc_lock(void) {
/** @brief Sets the wakeup time auto-reload value
*/
void rtc_set_wakeup_time(u16 wkup_time, u8 rtc_cr_wucksel) {
// FTFM:
// The following sequence is required to configure or change the wakeup timer
// auto-reload value (WUT[15:0] in RTC_WUTR):
// 1. Clear WUTE in RTC_CR to disable the wakeup timer.
RTC_CR &= ~RTC_CR_WUTE;
// 2. Poll WUTWF until it is set in RTC_ISR to make sure the access to wakeup
// auto-reload counter and to WUCKSEL[2:0] bits is allowed. It takes around 2
// RTCCLK clock cycles (due to clock synchronization).
while (!((RTC_ISR) & (RTC_ISR_WUTWF))) { }
// 3. Program the wakeup auto-reload value WUT[15:0], and the wakeup clock
// selection (WUCKSEL[2:0] bits in RTC_CR).Set WUTE in RTC_CR to enable the
// timer again. The wakeup timer restarts down-counting.
RTC_WUTR = wkup_time;
RTC_CR |= (rtc_cr_wucksel << RTC_CR_WUCLKSEL_SHIFT);
RTC_CR |= RTC_CR_WUTE;
void rtc_set_wakeup_time(u16 wkup_time, u8 rtc_cr_wucksel)
{
/* FTFM:
* The following sequence is required to configure or change the wakeup
* timer auto-reload value (WUT[15:0] in RTC_WUTR):
* 1. Clear WUTE in RTC_CR to disable the wakeup timer.
*/
RTC_CR &= ~RTC_CR_WUTE;
/* 2. Poll WUTWF until it is set in RTC_ISR to make sure the access to
* wakeup auto-reload counter and to WUCKSEL[2:0] bits is allowed.
* It takes around 2 RTCCLK clock cycles (due to clock
* synchronization).
*/
while (!((RTC_ISR) & (RTC_ISR_WUTWF)));
/* 3. Program the wakeup auto-reload value WUT[15:0], and the wakeup
* clock selection (WUCKSEL[2:0] bits in RTC_CR).Set WUTE in RTC_CR
* to enable the timer again. The wakeup timer restarts
* down-counting.
*/
RTC_WUTR = wkup_time;
RTC_CR |= (rtc_cr_wucksel << RTC_CR_WUCLKSEL_SHIFT);
RTC_CR |= RTC_CR_WUTE;
}
/*---------------------------------------------------------------------------*/
/** @brief Clears the wakeup flag
@details This function should be called first in the rtc_wkup_isr()
@details This function should be called first in the rtc_wkup_isr()
*/
void rtc_clear_wakeup_flag(void) {
RTC_ISR &= ~RTC_ISR_WUTF;
void rtc_clear_wakeup_flag(void)
{
RTC_ISR &= ~RTC_ISR_WUTF;
}
/**@}*/

167
lib/stm32/common/spi_common_all.c
View File

@@ -1,7 +1,9 @@
/** @addtogroup spi_file
@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
@author @htmlonly &copy; @endhtmlonly 2009
Uwe Hermann <uwe@hermann-uwe.de>
@author @htmlonly &copy; @endhtmlonly 2012
Ken Sarkies <ksarkies@internode.on.net>
Devices can have up to three SPI peripherals. The common 4-wire full-duplex
mode of operation is supported, along with 3-wire variants using unidirectional
@@ -18,8 +20,8 @@ Example: 1Mbps, positive clock polarity, leading edge trigger, 8-bit words,
LSB first.
@code
spi_init_master(SPI1, 1000000, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE,
SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT,
SPI_CR1_LSBFIRST);
SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT,
SPI_CR1_LSBFIRST);
spi_write(SPI1, 0x55); // 8-bit write
spi_write(SPI1, 0xaa88); // 16-bit write
reg8 = spi_read(SPI1); // 8-bit read
@@ -67,13 +69,14 @@ LSB first.
/**@{*/
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Reset.
The SPI peripheral and all its associated configuration registers are placed in the
reset condition. The reset is effected via the RCC peripheral reset system.
The SPI peripheral and all its associated configuration registers are placed in
the reset condition. The reset is effected via the RCC peripheral reset system.
@param[in] spi_peripheral Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
@param[in] spi_peripheral Unsigned int32. SPI peripheral identifier @ref
spi_reg_base.
*/
void spi_reset(u32 spi_peripheral)
@@ -96,7 +99,7 @@ void spi_reset(u32 spi_peripheral)
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Configure the SPI as Master.
The SPI peripheral is configured as a master with communication parameters
@@ -111,7 +114,8 @@ These must be controlled separately.
@param[in] cpol Unsigned int32. Clock polarity @ref spi_cpol.
@param[in] cpha Unsigned int32. Clock Phase @ref spi_cpha.
@param[in] dff Unsigned int32. Data frame format 8/16 bits @ref spi_dff.
@param[in] lsbfirst Unsigned int32. Frame format lsb/msb first @ref spi_lsbfirst.
@param[in] lsbfirst Unsigned int32. Frame format lsb/msb first @ref
spi_lsbfirst.
@returns int. Error code.
*/
@@ -138,7 +142,7 @@ int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst)
}
/* TODO: Error handling? */
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Enable.
The SPI peripheral is enabled.
@@ -154,7 +158,7 @@ void spi_enable(u32 spi)
}
/* TODO: Error handling? */
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Disable.
The SPI peripheral is disabled.
@@ -171,7 +175,7 @@ void spi_disable(u32 spi)
SPI_CR1(spi) = reg32;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Clean Disable.
Disable the SPI peripheral according to the procedure in section 23.3.8 of the
@@ -185,25 +189,22 @@ prevents the BSY flag from becoming unreliable.
u16 spi_clean_disable(u32 spi)
{
/* Wait to receive last data */
while (!(SPI_SR(spi) & SPI_SR_RXNE))
;
while (!(SPI_SR(spi) & SPI_SR_RXNE));
u16 data = SPI_DR(spi);
/* Wait to transmit last data */
while (!(SPI_SR(spi) & SPI_SR_TXE))
;
while (!(SPI_SR(spi) & SPI_SR_TXE));
/* Wait until not busy */
while (SPI_SR(spi) & SPI_SR_BSY)
;
while (SPI_SR(spi) & SPI_SR_BSY);
SPI_CR1(spi) &= ~SPI_CR1_SPE;
return data;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Data Write.
Data is written to the SPI interface.
@@ -218,10 +219,11 @@ void spi_write(u32 spi, u16 data)
SPI_DR(spi) = data;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Data Write with Blocking.
Data is written to the SPI interface after the previous write transfer has finished.
Data is written to the SPI interface after the previous write transfer has
finished.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
@param[in] data Unsigned int16. 8 or 16 bit data to be written.
@@ -230,14 +232,13 @@ Data is written to the SPI interface after the previous write transfer has finis
void spi_send(u32 spi, u16 data)
{
/* Wait for transfer finished. */
while (!(SPI_SR(spi) & SPI_SR_TXE))
;
while (!(SPI_SR(spi) & SPI_SR_TXE));
/* Write data (8 or 16 bits, depending on DFF) into DR. */
SPI_DR(spi) = data;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Data Read.
Data is read from the SPI interface after the incoming transfer has finished.
@@ -249,18 +250,17 @@ Data is read from the SPI interface after the incoming transfer has finished.
u16 spi_read(u32 spi)
{
/* Wait for transfer finished. */
while (!(SPI_SR(spi) & SPI_SR_RXNE))
;
while (!(SPI_SR(spi) & SPI_SR_RXNE));
/* Read the data (8 or 16 bits, depending on DFF bit) from DR. */
return SPI_DR(spi);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Data Write and Read Exchange.
Data is written to the SPI interface, then a read is done after the incoming transfer
has finished.
Data is written to the SPI interface, then a read is done after the incoming
transfer has finished.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
@param[in] data Unsigned int16. 8 or 16 bit data to be written.
@@ -272,14 +272,13 @@ u16 spi_xfer(u32 spi, u16 data)
spi_write(spi, data);
/* Wait for transfer finished. */
while (!(SPI_SR(spi) & SPI_SR_RXNE))
;
while (!(SPI_SR(spi) & SPI_SR_RXNE));
/* Read the data (8 or 16 bits, depending on DFF bit) from DR. */
return SPI_DR(spi);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Set Bidirectional Simplex Mode.
The SPI peripheral is set for bidirectional transfers in two-wire simplex mode
@@ -293,12 +292,12 @@ void spi_set_bidirectional_mode(u32 spi)
SPI_CR1(spi) |= SPI_CR1_BIDIMODE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Set Unidirectional Mode.
The SPI peripheral is set for unidirectional transfers. This is used in full duplex
mode or when the SPI is placed in two-wire simplex mode that uses a clock wire and a
unidirectional data wire.
The SPI peripheral is set for unidirectional transfers. This is used in full
duplex mode or when the SPI is placed in two-wire simplex mode that uses a
clock wire and a unidirectional data wire.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
@@ -308,11 +307,12 @@ void spi_set_unidirectional_mode(u32 spi)
SPI_CR1(spi) &= ~SPI_CR1_BIDIMODE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Set Bidirectional Simplex Receive Only Mode.
The SPI peripheral is set for bidirectional transfers in two-wire simplex mode
(using a clock wire and a bidirectional data wire), and is placed in a receive state.
(using a clock wire and a bidirectional data wire), and is placed in a receive
state.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
@@ -323,11 +323,12 @@ void spi_set_bidirectional_receive_only_mode(u32 spi)
SPI_CR1(spi) &= ~SPI_CR1_BIDIOE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Set Bidirectional Simplex Receive Only Mode.
The SPI peripheral is set for bidirectional transfers in two-wire simplex mode
(using a clock wire and a bidirectional data wire), and is placed in a transmit state.
(using a clock wire and a bidirectional data wire), and is placed in a transmit
state.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
@@ -338,7 +339,7 @@ void spi_set_bidirectional_transmit_only_mode(u32 spi)
SPI_CR1(spi) |= SPI_CR1_BIDIOE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Enable the CRC.
The SPI peripheral is set to use a CRC field for transmit and receive.
@@ -351,7 +352,7 @@ void spi_enable_crc(u32 spi)
SPI_CR1(spi) |= SPI_CR1_CRCEN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Disable the CRC.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
@@ -362,7 +363,7 @@ void spi_disable_crc(u32 spi)
SPI_CR1(spi) &= ~SPI_CR1_CRCEN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Next Transmit is a Data Word
The next transmission to take place is a data word from the transmit buffer.
@@ -377,7 +378,7 @@ void spi_set_next_tx_from_buffer(u32 spi)
SPI_CR1(spi) &= ~SPI_CR1_CRCNEXT;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Next Transmit is a CRC Word
The next transmission to take place is a crc word from the hardware crc unit.
@@ -392,7 +393,7 @@ void spi_set_next_tx_from_crc(u32 spi)
SPI_CR1(spi) |= SPI_CR1_CRCNEXT;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Set Data Frame Format to 8 bits
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
@@ -403,7 +404,7 @@ void spi_set_dff_8bit(u32 spi)
SPI_CR1(spi) &= ~SPI_CR1_DFF;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Set Data Frame Format to 16 bits
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
@@ -414,7 +415,7 @@ void spi_set_dff_16bit(u32 spi)
SPI_CR1(spi) |= SPI_CR1_DFF;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Set Full Duplex (3-wire) Mode
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
@@ -425,8 +426,9 @@ void spi_set_full_duplex_mode(u32 spi)
SPI_CR1(spi) &= ~SPI_CR1_RXONLY;
}
/*-----------------------------------------------------------------------------*/
/** @brief SPI Set Receive Only Mode for Simplex (2-wire) Unidirectional Transfers
/*---------------------------------------------------------------------------*/
/** @brief SPI Set Receive Only Mode for Simplex (2-wire) Unidirectional
Transfers
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
@@ -436,7 +438,7 @@ void spi_set_receive_only_mode(u32 spi)
SPI_CR1(spi) |= SPI_CR1_RXONLY;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Enable Slave Management by Hardware
In slave mode the NSS hardware input is used as a select enable for the slave.
@@ -449,7 +451,7 @@ void spi_disable_software_slave_management(u32 spi)
SPI_CR1(spi) &= ~SPI_CR1_SSM;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Enable Slave Management by Software
In slave mode the NSS hardware input is replaced by an internal software
@@ -463,13 +465,14 @@ void spi_enable_software_slave_management(u32 spi)
SPI_CR1(spi) |= SPI_CR1_SSM;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Set the Software NSS Signal High
In slave mode, and only when software slave management is used, this replaces
the NSS signal with a slave select enable signal.
@todo these should perhaps be combined with an SSM enable as it is meaningless otherwise
@todo these should perhaps be combined with an SSM enable as it is meaningless
otherwise
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
@@ -479,7 +482,7 @@ void spi_set_nss_high(u32 spi)
SPI_CR1(spi) |= SPI_CR1_SSI;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Set the Software NSS Signal Low
In slave mode, and only when software slave management is used, this replaces
@@ -493,7 +496,7 @@ void spi_set_nss_low(u32 spi)
SPI_CR1(spi) &= ~SPI_CR1_SSI;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Set to Send LSB First
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
@@ -504,7 +507,7 @@ void spi_send_lsb_first(u32 spi)
SPI_CR1(spi) |= SPI_CR1_LSBFIRST;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Set to Send MSB First
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
@@ -515,10 +518,11 @@ void spi_send_msb_first(u32 spi)
SPI_CR1(spi) &= ~SPI_CR1_LSBFIRST;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Set the Baudrate Prescaler
@todo Why is this specification different to the spi_init_master baudrate values?
@todo Why is this specification different to the spi_init_master baudrate
values?
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
@param[in] baudrate Unsigned int8. Baudrate prescale value @ref spi_br_pre.
@@ -528,15 +532,16 @@ void spi_set_baudrate_prescaler(u32 spi, u8 baudrate)
{
u32 reg32;
if (baudrate > 7)
if (baudrate > 7) {
return;
}
reg32 = (SPI_CR1(spi) & 0xffc7); /* Clear bits [5:3]. */
reg32 |= (baudrate << 3);
SPI_CR1(spi) = reg32;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Set to Master Mode
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
@@ -547,7 +552,7 @@ void spi_set_master_mode(u32 spi)
SPI_CR1(spi) |= SPI_CR1_MSTR;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Set to Slave Mode
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
@@ -558,7 +563,7 @@ void spi_set_slave_mode(u32 spi)
SPI_CR1(spi) &= ~SPI_CR1_MSTR;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Set the Clock Polarity to High when Idle
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
@@ -569,7 +574,7 @@ void spi_set_clock_polarity_1(u32 spi)
SPI_CR1(spi) |= SPI_CR1_CPOL;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Set the Clock Polarity to Low when Idle
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
@@ -580,7 +585,7 @@ void spi_set_clock_polarity_0(u32 spi)
SPI_CR1(spi) &= ~SPI_CR1_CPOL;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Set the Clock Phase to Capture on Trailing Edge
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
@@ -591,7 +596,7 @@ void spi_set_clock_phase_1(u32 spi)
SPI_CR1(spi) |= SPI_CR1_CPHA;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Set the Clock Phase to Capture on Leading Edge
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
@@ -602,7 +607,7 @@ void spi_set_clock_phase_0(u32 spi)
SPI_CR1(spi) &= ~SPI_CR1_CPHA;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Enable the Transmit Buffer Empty Interrupt
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
@@ -613,7 +618,7 @@ void spi_enable_tx_buffer_empty_interrupt(u32 spi)
SPI_CR2(spi) |= SPI_CR2_TXEIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Disable the Transmit Buffer Empty Interrupt
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
@@ -624,7 +629,7 @@ void spi_disable_tx_buffer_empty_interrupt(u32 spi)
SPI_CR2(spi) &= ~SPI_CR2_TXEIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Enable the Receive Buffer Ready Interrupt
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
@@ -635,7 +640,7 @@ void spi_enable_rx_buffer_not_empty_interrupt(u32 spi)
SPI_CR2(spi) |= SPI_CR2_RXNEIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Disable the Receive Buffer Ready Interrupt
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
@@ -646,7 +651,7 @@ void spi_disable_rx_buffer_not_empty_interrupt(u32 spi)
SPI_CR2(spi) &= ~SPI_CR2_RXNEIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Enable the Error Interrupt
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
@@ -657,7 +662,7 @@ void spi_enable_error_interrupt(u32 spi)
SPI_CR2(spi) |= SPI_CR2_ERRIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Disable the Error Interrupt
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
@@ -668,7 +673,7 @@ void spi_disable_error_interrupt(u32 spi)
SPI_CR2(spi) &= ~SPI_CR2_ERRIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Set the NSS Pin as an Output
Normally used in master mode to allows the master to place all devices on the
@@ -682,7 +687,7 @@ void spi_enable_ss_output(u32 spi)
SPI_CR2(spi) |= SPI_CR2_SSOE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Set the NSS Pin as an Input
In master mode this allows the master to sense the presence of other masters. If
@@ -697,7 +702,7 @@ void spi_disable_ss_output(u32 spi)
SPI_CR2(spi) &= ~SPI_CR2_SSOE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Enable Transmit Transfers via DMA
This allows transmissions to proceed unattended using DMA to move data to the
@@ -712,7 +717,7 @@ void spi_enable_tx_dma(u32 spi)
SPI_CR2(spi) |= SPI_CR2_TXDMAEN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Disable Transmit Transfers via DMA
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
@@ -723,12 +728,12 @@ void spi_disable_tx_dma(u32 spi)
SPI_CR2(spi) &= ~SPI_CR2_TXDMAEN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Enable Receive Transfers via DMA
This allows received data streams to proceed unattended using DMA to move data from
the receive buffer as data becomes available. The DMA channels provided for each
SPI peripheral are given in the Technical Manual DMA section.
This allows received data streams to proceed unattended using DMA to move data
from the receive buffer as data becomes available. The DMA channels provided
for each SPI peripheral are given in the Technical Manual DMA section.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
@@ -738,7 +743,7 @@ void spi_enable_rx_dma(u32 spi)
SPI_CR2(spi) |= SPI_CR2_RXDMAEN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Disable Receive Transfers via DMA
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.

491
lib/stm32/common/timer_common_all.c
View File

File diff suppressed because it is too large Load Diff

31
lib/stm32/common/timer_common_f24.c
View File

@@ -33,7 +33,8 @@ Set timer options register on TIM2 or TIM5, used for trigger remapping on TIM2,
and similarly for TIM5 for oscillator calibration purposes.
@param[in] timer_peripheral Unsigned int32. Timer register address base
@returns Unsigned int32. Option flags TIM2: @ref tim2_opt_trigger_remap, TIM5: @ref tim5_opt_trigger_remap.
@returns Unsigned int32. Option flags TIM2: @ref tim2_opt_trigger_remap, TIM5:
@ref tim5_opt_trigger_remap.
*/
void timer_set_option(u32 timer_peripheral, u32 option)
@@ -57,20 +58,22 @@ The timer channel must be set to input capture mode.
@param[in] pol ::tim_ic_pol. Input Capture polarity control.
*/
void timer_ic_set_polarity(u32 timer_peripheral, enum tim_ic_id ic, enum tim_ic_pol pol)
void timer_ic_set_polarity(u32 timer_peripheral, enum tim_ic_id ic,
enum tim_ic_pol pol)
{
/* Clear CCxP and CCxNP to zero. For both edge trigger both fields are set. Case 10 is invalid. */
TIM_CCER(timer_peripheral) &= ~(0x6 << (ic * 4));
switch (pol)
{
case TIM_IC_RISING: /* 00 */
break;
case TIM_IC_BOTH: /* 11 */
TIM_CCER(timer_peripheral) |= (0x6 << (ic * 4));
break;
case TIM_IC_FALLING: /* 01 */
TIM_CCER(timer_peripheral) |= (0x2 << (ic * 4));
}
/* Clear CCxP and CCxNP to zero. For both edge trigger both fields are
* set. Case 10 is invalid.
*/
TIM_CCER(timer_peripheral) &= ~(0x6 << (ic * 4));
switch (pol) {
case TIM_IC_RISING: /* 00 */
break;
case TIM_IC_BOTH: /* 11 */
TIM_CCER(timer_peripheral) |= (0x6 << (ic * 4));
break;
case TIM_IC_FALLING: /* 01 */
TIM_CCER(timer_peripheral) |= (0x2 << (ic * 4));
}
}
/**@}*/

165
lib/stm32/common/usart_common_all.c
View File

@@ -33,15 +33,16 @@ Devices can have up to 3 USARTs and 2 UARTs.
#include <libopencm3/stm32/usart.h>
#include <libopencm3/stm32/rcc.h>
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief USART Set Baudrate.
The baud rate is computed from the APB high-speed prescaler clock (for USART1/6)
or the APB low-speed prescaler clock (for other USARTs). These values must
be correctly set before calling this function (refer to the rcc_clock_setup-*
functions in RCC).
The baud rate is computed from the APB high-speed prescaler clock (for
USART1/6) or the APB low-speed prescaler clock (for other USARTs). These values
must be correctly set before calling this function (refer to the
rcc_clock_setup-* functions in RCC).
@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
@param[in] usart unsigned 32 bit. USART block register address base @ref
usart_reg_base
@param[in] baud unsigned 32 bit. Baud rate specified in Hz.
*/
@@ -72,30 +73,34 @@ void usart_set_baudrate(u32 usart, u32 baud)
USART_BRR(usart) = ((2 * clock) + baud) / (2 * baud);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief USART Set Word Length.
The word length is set to 8 or 9 bits. Note that the last bit will be a parity bit
if parity is enabled, in which case the data length will be 7 or 8 bits respectively.
The word length is set to 8 or 9 bits. Note that the last bit will be a parity
bit if parity is enabled, in which case the data length will be 7 or 8 bits
respectively.
@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
@param[in] usart unsigned 32 bit. USART block register address base @ref
usart_reg_base
@param[in] bits unsigned 32 bit. Word length in bits 8 or 9.
*/
void usart_set_databits(u32 usart, u32 bits)
{
if (bits == 8)
if (bits == 8) {
USART_CR1(usart) &= ~USART_CR1_M; /* 8 data bits */
else
} else {
USART_CR1(usart) |= USART_CR1_M; /* 9 data bits */
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief USART Set Stop Bit(s).
The stop bits are specified as 0.5, 1, 1.5 or 2.
@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
@param[in] usart unsigned 32 bit. USART block register address base @ref
usart_reg_base
@param[in] stopbits unsigned 32 bit. Stop bits @ref usart_cr2_stopbits.
*/
@@ -108,12 +113,13 @@ void usart_set_stopbits(u32 usart, u32 stopbits)
USART_CR2(usart) = reg32;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief USART Set Parity.
The parity bit can be selected as none, even or odd.
@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
@param[in] usart unsigned 32 bit. USART block register address base @ref
usart_reg_base
@param[in] parity unsigned 32 bit. Parity @ref usart_cr1_parity.
*/
@@ -126,12 +132,13 @@ void usart_set_parity(u32 usart, u32 parity)
USART_CR1(usart) = reg32;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief USART Set Rx/Tx Mode.
The mode can be selected as Rx only, Tx only or Rx+Tx.
@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
@param[in] usart unsigned 32 bit. USART block register address base @ref
usart_reg_base
@param[in] mode unsigned 32 bit. Mode @ref usart_cr1_mode.
*/
@@ -144,12 +151,13 @@ void usart_set_mode(u32 usart, u32 mode)
USART_CR1(usart) = reg32;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief USART Set Hardware Flow Control.
The flow control bit can be selected as none, RTS, CTS or RTS+CTS.
@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
@param[in] usart unsigned 32 bit. USART block register address base @ref
usart_reg_base
@param[in] flowcontrol unsigned 32 bit. Flowcontrol @ref usart_cr3_flowcontrol.
*/
@@ -162,10 +170,11 @@ void usart_set_flow_control(u32 usart, u32 flowcontrol)
USART_CR3(usart) = reg32;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief USART Enable.
@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
@param[in] usart unsigned 32 bit. USART block register address base @ref
usart_reg_base
*/
void usart_enable(u32 usart)
@@ -173,12 +182,13 @@ void usart_enable(u32 usart)
USART_CR1(usart) |= USART_CR1_UE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief USART Disable.
At the end of the current frame, the USART is disabled to reduce power.
@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
@param[in] usart unsigned 32 bit. USART block register address base @ref
usart_reg_base
*/
void usart_disable(u32 usart)
@@ -186,10 +196,11 @@ void usart_disable(u32 usart)
USART_CR1(usart) &= ~USART_CR1_UE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief USART Send a Data Word.
@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
@param[in] usart unsigned 32 bit. USART block register address base @ref
usart_reg_base
@param[in] data unsigned 16 bit.
*/
@@ -199,12 +210,14 @@ void usart_send(u32 usart, u16 data)
USART_DR(usart) = (data & USART_DR_MASK);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief USART Read a Received Data Word.
If parity is enabled the MSB (bit 7 or 8 depending on the word length) is the parity bit.
If parity is enabled the MSB (bit 7 or 8 depending on the word length) is the
parity bit.
@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
@param[in] usart unsigned 32 bit. USART block register address base @ref
usart_reg_base
@returns unsigned 16 bit data word.
*/
@@ -214,13 +227,14 @@ u16 usart_recv(u32 usart)
return USART_DR(usart) & USART_DR_MASK;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief USART Wait for Transmit Data Buffer Empty
Blocks until the transmit data buffer becomes empty and is ready to accept the
next data word.
@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
@param[in] usart unsigned 32 bit. USART block register address base @ref
usart_reg_base
*/
void usart_wait_send_ready(u32 usart)
@@ -229,12 +243,13 @@ void usart_wait_send_ready(u32 usart)
while ((USART_SR(usart) & USART_SR_TXE) == 0);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief USART Wait for Received Data Available
Blocks until the receive data buffer holds a valid received data word.
@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
@param[in] usart unsigned 32 bit. USART block register address base @ref
usart_reg_base
*/
void usart_wait_recv_ready(u32 usart)
@@ -243,13 +258,14 @@ void usart_wait_recv_ready(u32 usart)
while ((USART_SR(usart) & USART_SR_RXNE) == 0);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief USART Send Data Word with Blocking
Blocks until the transmit data buffer becomes empty then writes the next data word
for transmission.
Blocks until the transmit data buffer becomes empty then writes the next data
word for transmission.
@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
@param[in] usart unsigned 32 bit. USART block register address base @ref
usart_reg_base
@param[in] data unsigned 16 bit.
*/
@@ -259,12 +275,13 @@ void usart_send_blocking(u32 usart, u16 data)
usart_send(usart, data);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief USART Read a Received Data Word with Blocking.
Wait until a data word has been received then return the word.
@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
@param[in] usart unsigned 32 bit. USART block register address base @ref
usart_reg_base
@returns unsigned 16 bit data word.
*/
@@ -275,7 +292,7 @@ u16 usart_recv_blocking(u32 usart)
return usart_recv(usart);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief USART Receiver DMA Enable.
DMA is available on:
@@ -284,7 +301,8 @@ DMA is available on:
@li USART3 Rx DMA1 channel 3.
@li UART4 Rx DMA2 channel 3.
@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
@param[in] usart unsigned 32 bit. USART block register address base @ref
usart_reg_base
*/
void usart_enable_rx_dma(u32 usart)
@@ -292,10 +310,11 @@ void usart_enable_rx_dma(u32 usart)
USART_CR3(usart) |= USART_CR3_DMAR;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief USART Receiver DMA Disable.
@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
@param[in] usart unsigned 32 bit. USART block register address base @ref
usart_reg_base
*/
void usart_disable_rx_dma(u32 usart)
@@ -303,7 +322,7 @@ void usart_disable_rx_dma(u32 usart)
USART_CR3(usart) &= ~USART_CR3_DMAR;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief USART Transmitter DMA Enable.
DMA is available on:
@@ -312,7 +331,8 @@ DMA is available on:
@li USART3 Tx DMA1 channel 2.
@li UART4 Tx DMA2 channel 5.
@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
@param[in] usart unsigned 32 bit. USART block register address base @ref
usart_reg_base
*/
void usart_enable_tx_dma(u32 usart)
@@ -320,10 +340,11 @@ void usart_enable_tx_dma(u32 usart)
USART_CR3(usart) |= USART_CR3_DMAT;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief USART Transmitter DMA Disable.
@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
@param[in] usart unsigned 32 bit. USART block register address base @ref
usart_reg_base
*/
void usart_disable_tx_dma(u32 usart)
@@ -331,10 +352,11 @@ void usart_disable_tx_dma(u32 usart)
USART_CR3(usart) &= ~USART_CR3_DMAT;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief USART Receiver Interrupt Enable.
@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
@param[in] usart unsigned 32 bit. USART block register address base @ref
usart_reg_base
*/
void usart_enable_rx_interrupt(u32 usart)
@@ -343,10 +365,11 @@ void usart_enable_rx_interrupt(u32 usart)
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief USART Receiver Interrupt Disable.
@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
@param[in] usart unsigned 32 bit. USART block register address base @ref
usart_reg_base
*/
void usart_disable_rx_interrupt(u32 usart)
@@ -354,10 +377,11 @@ void usart_disable_rx_interrupt(u32 usart)
USART_CR1(usart) &= ~USART_CR1_RXNEIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief USART Transmitter Interrupt Enable.
@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
@param[in] usart unsigned 32 bit. USART block register address base @ref
usart_reg_base
*/
void usart_enable_tx_interrupt(u32 usart)
@@ -365,10 +389,11 @@ void usart_enable_tx_interrupt(u32 usart)
USART_CR1(usart) |= USART_CR1_TXEIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief USART Transmitter Interrupt Disable.
@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
@param[in] usart unsigned 32 bit. USART block register address base @ref
usart_reg_base
*/
void usart_disable_tx_interrupt(u32 usart)
@@ -376,10 +401,11 @@ void usart_disable_tx_interrupt(u32 usart)
USART_CR1(usart) &= ~USART_CR1_TXEIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief USART Error Interrupt Enable.
@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
@param[in] usart unsigned 32 bit. USART block register address base @ref
usart_reg_base
*/
void usart_enable_error_interrupt(u32 usart)
@@ -387,10 +413,11 @@ void usart_enable_error_interrupt(u32 usart)
USART_CR3(usart) |= USART_CR3_EIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief USART Error Interrupt Disable.
@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
@param[in] usart unsigned 32 bit. USART block register address base @ref
usart_reg_base
*/
void usart_disable_error_interrupt(u32 usart)
@@ -401,7 +428,8 @@ void usart_disable_error_interrupt(u32 usart)
/*---------------------------------------------------------------------------*/
/** @brief USART Read a Status Flag.
@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
@param[in] usart unsigned 32 bit. USART block register address base @ref
usart_reg_base
@param[in] flag Unsigned int32. Status register flag @ref usart_sr_flags.
@returns boolean: flag set.
*/
@@ -422,7 +450,8 @@ flag, the function returns false.
relating to LIN break, and error conditions in multibuffer communication, need
to be added for completeness.
@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
@param[in] usart unsigned 32 bit. USART block register address base @ref
usart_reg_base
@param[in] flag Unsigned int32. Status register flag @ref usart_sr_flags.
@returns boolean: flag and interrupt enable both set.
*/
@@ -430,13 +459,15 @@ to be added for completeness.
bool usart_get_interrupt_source(u32 usart, u32 flag)
{
u32 flag_set = (USART_SR(usart) & flag);
/* IDLE, RXNE, TC, TXE interrupts */
if ((flag >= USART_SR_IDLE) && (flag <= USART_SR_TXE))
/* IDLE, RXNE, TC, TXE interrupts */
if ((flag >= USART_SR_IDLE) && (flag <= USART_SR_TXE)) {
return ((flag_set & USART_CR1(usart)) != 0);
/* Overrun error */
else if (flag == USART_SR_ORE)
return (flag_set && (USART_CR3(usart) & USART_CR3_CTSIE));
return (false);
/* Overrun error */
} else if (flag == USART_SR_ORE) {
return flag_set && (USART_CR3(usart) & USART_CR3_CTSIE);
}
return false;
}
/**@}*/

19
lib/stm32/desig.c
View File

@@ -21,19 +21,20 @@
u16 desig_get_flash_size(void)
{
return DESIG_FLASH_SIZE;
return DESIG_FLASH_SIZE;
}
void desig_get_unique_id(u32 result[])
{
// Could also just return a pointer to the start? read it as they wish?
u16 bits15_0 = DESIG_UID_15_0;
u32 bits31_16 = DESIG_UID_31_16;
u32 bits63_32 = DESIG_UID_63_32;
u32 bits95_64 = DESIG_UID_95_64;
result[0] = bits95_64;
result[1] = bits63_32;
result[2] = bits31_16 << 16 | bits15_0;
/* Could also just return a pointer to the start? read it as they wish?
*/
u16 bits15_0 = DESIG_UID_15_0;
u32 bits31_16 = DESIG_UID_31_16;
u32 bits63_32 = DESIG_UID_63_32;
u32 bits95_64 = DESIG_UID_95_64;
result[0] = bits95_64;
result[1] = bits63_32;
result[2] = bits31_16 << 16 | bits15_0;
}
void desig_get_unique_id_as_string(char *string,

550
lib/stm32/f1/adc.c
View File

File diff suppressed because it is too large Load Diff

1
lib/stm32/f1/crc.c
View File

@@ -31,4 +31,3 @@ LGPL License Terms @ref lgpl_license
#include <libopencm3/stm32/crc.h>
#include <libopencm3/stm32/common/crc_common_all.h>

11
lib/stm32/f1/flash.c
View File

@@ -95,7 +95,10 @@ void flash_clear_status_flags(void)
u32 flash_get_status_flags(void)
{
return (FLASH_SR &= (FLASH_SR_PGERR | FLASH_SR_EOP | FLASH_SR_WRPRTERR | FLASH_SR_BSY));
return FLASH_SR &= (FLASH_SR_PGERR |
FLASH_SR_EOP |
FLASH_SR_WRPRTERR |
FLASH_SR_BSY);
}
void flash_unlock_option_bytes(void)
@@ -174,8 +177,9 @@ void flash_erase_option_bytes(void)
{
flash_wait_for_last_operation();
if ((FLASH_CR & FLASH_CR_OPTWRE) == 0)
if ((FLASH_CR & FLASH_CR_OPTWRE) == 0) {
flash_unlock_option_bytes();
}
FLASH_CR |= FLASH_CR_OPTER; /* Enable option byte erase. */
FLASH_CR |= FLASH_CR_STRT;
@@ -187,8 +191,9 @@ void flash_program_option_bytes(u32 address, u16 data)
{
flash_wait_for_last_operation();
if ((FLASH_CR & FLASH_CR_OPTWRE) == 0)
if ((FLASH_CR & FLASH_CR_OPTWRE) == 0) {
flash_unlock_option_bytes();
}
FLASH_CR |= FLASH_CR_OPTPG; /* Enable option byte programming. */
(*(volatile u16 *)address) = data;

78
lib/stm32/f1/gpio.c
View File

@@ -6,23 +6,25 @@
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
@author @htmlonly &copy; @endhtmlonly 2009
Uwe Hermann <uwe@hermann-uwe.de>
@author @htmlonly &copy; @endhtmlonly 2012
Ken Sarkies <ksarkies@internode.on.net>
@date 18 August 2012
Each I/O port has 16 individually configurable bits. Many I/O pins share GPIO
functionality with a number of alternate functions and must be configured to the
alternate function mode if these are to be accessed. A feature is available to
remap alternative functions to a limited set of alternative pins in the event
of a clash of requirements.
functionality with a number of alternate functions and must be configured to
the alternate function mode if these are to be accessed. A feature is available
to remap alternative functions to a limited set of alternative pins in the
event of a clash of requirements.
The data registers associated with each port for input and output are 32 bit with
the upper 16 bits unused. The output buffer must be written as a 32 bit word, but
individual bits may be set or reset separately in atomic operations to avoid race
conditions during interrupts. Bits may also be individually locked to prevent
accidental configuration changes. Once locked the configuration cannot be changed
until after the next reset.
The data registers associated with each port for input and output are 32 bit
with the upper 16 bits unused. The output buffer must be written as a 32 bit
word, but individual bits may be set or reset separately in atomic operations
to avoid race conditions during interrupts. Bits may also be individually
locked to prevent accidental configuration changes. Once locked the
configuration cannot be changed until after the next reset.
Each port bit can be configured as analog or digital input, the latter can be
floating or pulled up or down. As outputs they can be configured as either
@@ -76,7 +78,7 @@ LGPL License Terms @ref lgpl_license
/**@{*/
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Set GPIO Pin Mode
Sets the mode (input/output) and configuration (analog/digitial and
@@ -86,7 +88,8 @@ open drain/push pull), for a set of GPIO pins on a given GPIO port.
@param[in] mode Unsigned int8. Pin mode @ref gpio_mode
@param[in] cnf Unsigned int8. Pin configuration @ref gpio_cnf
@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id
If multiple pins are to be set, use logical OR '|' to separate them.
If multiple pins are to be set, use logical OR '|' to separate
them.
*/
void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios)
@@ -104,8 +107,9 @@ void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios)
/* Iterate over all bits, use i as the bitnumber. */
for (i = 0; i < 16; i++) {
/* Only set the config if the bit is set in gpios. */
if (!((1 << i) & gpios))
if (!((1 << i) & gpios)) {
continue;
}
/* Calculate bit offset. */
offset = (i < 8) ? (i * 4) : ((i - 8) * 4);
@@ -126,7 +130,7 @@ void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios)
GPIO_CRH(gpioport) = crh;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Map the EVENTOUT signal
Enable the EVENTOUT signal and select the port and pin to be used.
@@ -139,45 +143,47 @@ void gpio_set_eventout(u8 evoutport, u8 evoutpin)
AFIO_EVCR = AFIO_EVCR_EVOE | evoutport | evoutpin;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Map Alternate Function Port Bits (Main Set)
A number of alternate function ports can be remapped to defined alternative
port bits to avoid clashes in cases where multiple alternate functions are present.
Refer to the datasheets for the particular mapping desired. This provides the main
set of remap functionality. See @ref gpio_secondary_remap for a number of lesser used
remaps.
port bits to avoid clashes in cases where multiple alternate functions are
present. Refer to the datasheets for the particular mapping desired. This
provides the main set of remap functionality. See @ref gpio_secondary_remap for
a number of lesser used remaps.
The AFIO remapping feature is used only with the STM32F10x series.
@note The Serial Wire JTAG disable controls allow certain GPIO ports to become available
in place of some of the SWJ signals. Full SWJ capability is obtained by setting this to
zero. The value of this must be specified for every call to this function as its current
value cannot be ascertained from the hardware.
@note The Serial Wire JTAG disable controls allow certain GPIO ports to become
available in place of some of the SWJ signals. Full SWJ capability is obtained
by setting this to zero. The value of this must be specified for every call to
this function as its current value cannot be ascertained from the hardware.
@param[in] swjdisable Unsigned int8. Disable parts of the SWJ capability @ref afio_swj_disable.
@param[in] maps Unsigned int32. Logical OR of map enable controls from @ref afio_remap,
@ref afio_remap_can1, @ref afio_remap_tim3, @ref afio_remap_tim2, @ref afio_remap_tim1,
@ref afio_remap_usart3. For connectivity line devices only @ref afio_remap_cld are
also available.
@param[in] swjdisable Unsigned int8. Disable parts of the SWJ capability @ref
afio_swj_disable.
@param[in] maps Unsigned int32. Logical OR of map enable controls from @ref
afio_remap, @ref afio_remap_can1, @ref afio_remap_tim3, @ref afio_remap_tim2,
@ref afio_remap_tim1, @ref afio_remap_usart3. For connectivity line devices
only @ref afio_remap_cld are also available.
*/
void gpio_primary_remap(u32 swjdisable, u32 maps)
{
AFIO_MAPR |= (swjdisable & AFIO_MAPR_SWJ_MASK) | (maps & 0x1FFFFF);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Map Alternate Function Port Bits (Secondary Set)
A number of alternate function ports can be remapped to defined alternative
port bits to avoid clashes in cases where multiple alternate functions are present.
Refer to the datasheets for the particular mapping desired. This provides the second
smaller and less used set of remap functionality. See @ref gpio_primary_remap for
the main set of remaps.
port bits to avoid clashes in cases where multiple alternate functions are
present. Refer to the datasheets for the particular mapping desired. This
provides the second smaller and less used set of remap functionality. See @ref
gpio_primary_remap for the main set of remaps.
The AFIO remapping feature is used only with the STM32F10x series.
@param[in] maps Unsigned int32. Logical OR of map enable controls from @ref afio_remap2
@param[in] maps Unsigned int32. Logical OR of map enable controls from @ref
afio_remap2
*/
void gpio_secondary_remap(u32 maps)
{

3
lib/stm32/f1/pwr.c
View File

@@ -6,7 +6,8 @@
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
@author @htmlonly &copy; @endhtmlonly 2012
Ken Sarkies <ksarkies@internode.on.net>
@date 18 August 2012

205
lib/stm32/f1/rcc.c
View File

@@ -6,7 +6,8 @@
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2009 Federico Ruiz-Ugalde \<memeruiz at gmail dot com\>
@author @htmlonly &copy; @endhtmlonly 2009
Federico Ruiz-Ugalde \<memeruiz at gmail dot com\>
@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
@@ -17,8 +18,8 @@ series of ARM Cortex Microcontrollers by ST Microelectronics.
@note Full support for connection line devices is not yet provided.
Clock settings and resets for many peripherals are given here rather than in the
corresponding peripheral library.
Clock settings and resets for many peripherals are given here rather than in
the corresponding peripheral library.
The library also provides a number of common configurations for the processor
system clock. Not all possible configurations are included.
@@ -57,10 +58,11 @@ u32 rcc_ppre1_frequency = 8000000;
/** Default ppre2 peripheral clock frequency after reset. */
u32 rcc_ppre2_frequency = 8000000;
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Clear the Oscillator Ready Interrupt Flag
Clear the interrupt flag that was set when a clock oscillator became ready to use.
Clear the interrupt flag that was set when a clock oscillator became ready to
use.
@param[in] osc enum ::osc_t. Oscillator ID
*/
@@ -92,7 +94,7 @@ void rcc_osc_ready_int_clear(osc_t osc)
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Enable the Oscillator Ready Interrupt
@param[in] osc enum ::osc_t. Oscillator ID
@@ -125,7 +127,7 @@ void rcc_osc_ready_int_enable(osc_t osc)
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Disable the Oscillator Ready Interrupt
@param[in] osc enum ::osc_t. Oscillator ID
@@ -158,7 +160,7 @@ void rcc_osc_ready_int_disable(osc_t osc)
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Read the Oscillator Ready Interrupt Flag
@param[in] osc enum ::osc_t. Oscillator ID
@@ -194,7 +196,7 @@ int rcc_osc_ready_int_flag(osc_t osc)
cm3_assert_not_reached();
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Clear the Clock Security System Interrupt Flag
*/
@@ -204,7 +206,7 @@ void rcc_css_int_clear(void)
RCC_CIR |= RCC_CIR_CSSC;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Read the Clock Security System Interrupt Flag
@returns int. Boolean value for flag set.
@@ -215,7 +217,7 @@ int rcc_css_int_flag(void)
return ((RCC_CIR & RCC_CIR_CSSF) != 0);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Wait for Oscillator Ready.
@param[in] osc enum ::osc_t. Oscillator ID
@@ -248,16 +250,17 @@ void rcc_wait_for_osc_ready(osc_t osc)
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Turn on an Oscillator.
Enable an oscillator and power on. Each oscillator requires an amount of time to
settle to a usable state. Refer to datasheets for time delay information. A status
flag is available to indicate when the oscillator becomes ready (see
Enable an oscillator and power on. Each oscillator requires an amount of time
to settle to a usable state. Refer to datasheets for time delay information. A
status flag is available to indicate when the oscillator becomes ready (see
@ref rcc_osc_ready_int_flag and @ref rcc_wait_for_osc_ready).
@note The LSE clock is in the backup domain and cannot be enabled until the
backup domain write protection has been removed (see @ref pwr_disable_backup_domain_write_protect).
backup domain write protection has been removed (see @ref
pwr_disable_backup_domain_write_protect).
@param[in] osc enum ::osc_t. Oscillator ID
*/
@@ -289,7 +292,7 @@ void rcc_osc_on(osc_t osc)
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Turn off an Oscillator.
Disable an oscillator and power off.
@@ -330,7 +333,7 @@ void rcc_osc_off(osc_t osc)
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Enable the Clock Security System.
*/
@@ -340,7 +343,7 @@ void rcc_css_enable(void)
RCC_CR |= RCC_CR_CSSON;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Disable the Clock Security System.
*/
@@ -350,15 +353,16 @@ void rcc_css_disable(void)
RCC_CR &= ~RCC_CR_CSSON;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Enable Bypass.
Enable an external clock to bypass the internal clock (high speed and low speed
clocks only). The external clock must be enabled (see @ref rcc_osc_on)
and the internal clock must be disabled (see @ref rcc_osc_off) for this to have effect.
clocks only). The external clock must be enabled (see @ref rcc_osc_on) and the
internal clock must be disabled (see @ref rcc_osc_off) for this to have effect.
@note The LSE clock is in the backup domain and cannot be bypassed until the
backup domain write protection has been removed (see @ref pwr_disable_backup_domain_write_protect).
backup domain write protection has been removed (see @ref
pwr_disable_backup_domain_write_protect).
@param[in] osc enum ::osc_t. Oscillator ID. Only HSE and LSE have effect.
*/
@@ -382,15 +386,16 @@ void rcc_osc_bypass_enable(osc_t osc)
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Disable Bypass.
Re-enable the internal clock (high speed and low speed clocks only). The internal
clock must be disabled (see @ref rcc_osc_off) for this to have effect.
Re-enable the internal clock (high speed and low speed clocks only). The
internal clock must be disabled (see @ref rcc_osc_off) for this to have effect.
@note The LSE clock is in the backup domain and cannot have bypass removed until the
backup domain write protection has been removed (see @ref pwr_disable_backup_domain_write_protect)
or the backup domain has been reset (see @ref rcc_backupdomain_reset).
@note The LSE clock is in the backup domain and cannot have bypass removed
until the backup domain write protection has been removed (see @ref
pwr_disable_backup_domain_write_protect) or the backup domain has been reset
(see @ref rcc_backupdomain_reset).
@param[in] osc enum ::osc_t. Oscillator ID. Only HSE and LSE have effect.
*/
@@ -414,13 +419,13 @@ void rcc_osc_bypass_disable(osc_t osc)
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Enable Peripheral Clocks.
Enable the clock on particular peripherals. There are three registers
involved, each one controlling the enabling of clocks associated with the AHB,
APB1 and APB2 respectively. Several peripherals could be
enabled simultaneously <em>only if they are controlled by the same register</em>.
Enable the clock on particular peripherals. There are three registers involved,
each one controlling the enabling of clocks associated with the AHB, APB1 and
APB2 respectively. Several peripherals could be enabled simultaneously <em>only
if they are controlled by the same register</em>.
@param[in] *reg Unsigned int32. Pointer to a Clock Enable Register
(either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
@@ -435,17 +440,18 @@ void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en)
*reg |= en;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Disable Peripheral Clocks.
Enable the clock on particular peripherals. There are three registers
involved, each one controlling the enabling of clocks associated with the AHB,
APB1 and APB2 respectively. Several peripherals could be
disabled simultaneously <em>only if they are controlled by the same register</em>.
Enable the clock on particular peripherals. There are three registers involved,
each one controlling the enabling of clocks associated with the AHB, APB1 and
APB2 respectively. Several peripherals could be disabled simultaneously
<em>only if they are controlled by the same register</em>.
@param[in] *reg Unsigned int32. Pointer to a Clock Enable Register
(either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
@param[in] en Unsigned int32. Logical OR of all enables to be used for disabling.
@param[in] en Unsigned int32. Logical OR of all enables to be used for
disabling.
@li If register is RCC_AHBER, from @ref rcc_ahbenr_en
@li If register is RCC_APB1ENR, from @ref rcc_apb1enr_en
@li If register is RCC_APB2ENR, from @ref rcc_apb2enr_en
@@ -456,13 +462,13 @@ void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en)
*reg &= ~en;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Reset Peripherals.
Reset particular peripherals. There are three registers
involved, each one controlling reset of peripherals associated with the AHB,
APB1 and APB2 respectively. Several peripherals could be reset simultaneously
<em>only if they are controlled by the same register</em>.
Reset particular peripherals. There are three registers involved, each one
controlling reset of peripherals associated with the AHB, APB1 and APB2
respectively. Several peripherals could be reset simultaneously <em>only if
they are controlled by the same register</em>.
@param[in] *reg Unsigned int32. Pointer to a Reset Register
(either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
@@ -477,7 +483,7 @@ void rcc_peripheral_reset(volatile u32 *reg, u32 reset)
*reg |= reset;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Remove Reset on Peripherals.
Remove the reset on particular peripherals. There are three registers
@@ -498,7 +504,7 @@ void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset)
*reg &= ~clear_reset;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Set the Source for the System Clock.
@param[in] clk Unsigned int32. System Clock Selection @ref rcc_cfgr_scs
@@ -513,7 +519,7 @@ void rcc_set_sysclk_source(u32 clk)
RCC_CFGR = (reg32 | clk);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Set the PLL Multiplication Factor.
@note This only has effect when the PLL is disabled.
@@ -530,7 +536,7 @@ void rcc_set_pll_multiplication_factor(u32 mul)
RCC_CFGR = (reg32 | (mul << 18));
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Set the PLL2 Multiplication Factor.
@note This only has effect when the PLL is disabled.
@@ -547,7 +553,7 @@ void rcc_set_pll2_multiplication_factor(u32 mul)
RCC_CFGR2 = (reg32 | (mul << 8));
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Set the PLL3 Multiplication Factor.
@note This only has effect when the PLL is disabled.
@@ -564,7 +570,7 @@ void rcc_set_pll3_multiplication_factor(u32 mul)
RCC_CFGR2 = (reg32 | (mul << 12));
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Set the PLL Clock Source.
@note This only has effect when the PLL is disabled.
@@ -581,7 +587,7 @@ void rcc_set_pll_source(u32 pllsrc)
RCC_CFGR = (reg32 | (pllsrc << 16));
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Set the HSE Frequency Divider used as PLL Clock Source.
@note This only has effect when the PLL is disabled.
@@ -598,7 +604,7 @@ void rcc_set_pllxtpre(u32 pllxtpre)
RCC_CFGR = (reg32 | (pllxtpre << 17));
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Setup the A/D Clock
The ADC's have a common clock prescale setting.
@@ -615,7 +621,7 @@ void rcc_set_adcpre(u32 adcpre)
RCC_CFGR = (reg32 | (adcpre << 14));
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Set the APB2 Prescale Factor.
@param[in] ppre2 Unsigned int32. APB2 prescale factor @ref rcc_cfgr_apb2pre
@@ -630,7 +636,7 @@ void rcc_set_ppre2(u32 ppre2)
RCC_CFGR = (reg32 | (ppre2 << 11));
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Set the APB1 Prescale Factor.
@note The APB1 clock frequency must not exceed 36MHz.
@@ -647,7 +653,7 @@ void rcc_set_ppre1(u32 ppre1)
RCC_CFGR = (reg32 | (ppre1 << 8));
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Set the AHB Prescale Factor.
@param[in] hpre Unsigned int32. AHB prescale factor @ref rcc_cfgr_ahbpre
@@ -662,7 +668,7 @@ void rcc_set_hpre(u32 hpre)
RCC_CFGR = (reg32 | (hpre << 4));
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Set the USB Prescale Factor.
The prescale factor can be set to 1 (no prescale) for use when the PLL clock is
@@ -712,7 +718,7 @@ void rcc_set_mco(u32 mcosrc)
RCC_CFGR |= (reg32 | (mcosrc << 24));
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Get the System Clock Source.
@returns Unsigned int32. System clock source:
@@ -724,15 +730,15 @@ void rcc_set_mco(u32 mcosrc)
u32 rcc_system_clock_source(void)
{
/* Return the clock source which is used as system clock. */
return ((RCC_CFGR & 0x000c) >> 2);
return (RCC_CFGR & 0x000c) >> 2;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/*
* These functions are setting up the whole clock system for the most common
* input clock and output clock configurations.
*/
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Set System Clock PLL at 64MHz from HSI
*/
@@ -750,10 +756,10 @@ void rcc_clock_setup_in_hsi_out_64mhz(void)
* Set prescalers for AHB, ADC, ABP1, ABP2.
* Do this before touching the PLL (TODO: why?).
*/
rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 64MHz Max. 72MHz */
rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 8MHz Max. 14MHz */
rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 32MHz Max. 36MHz */
rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 64MHz Max. 72MHz */
rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 64MHz Max. 72MHz */
rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 8MHz Max. 14MHz */
rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 32MHz Max. 36MHz */
rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 64MHz Max. 72MHz */
/*
* Sysclk is running with 64MHz -> 2 waitstates.
@@ -784,7 +790,7 @@ void rcc_clock_setup_in_hsi_out_64mhz(void)
rcc_ppre2_frequency = 64000000;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Set System Clock PLL at 48MHz from HSI
*/
@@ -802,11 +808,11 @@ void rcc_clock_setup_in_hsi_out_48mhz(void)
* Set prescalers for AHB, ADC, ABP1, ABP2.
* Do this before touching the PLL (TODO: why?).
*/
rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 48MHz Max. 72MHz */
rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 6MHz Max. 14MHz */
rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 24MHz Max. 36MHz */
rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 48MHz Max. 72MHz */
rcc_set_usbpre(RCC_CFGR_USBPRE_PLL_CLK_NODIV); /* Set. 48MHz Max. 48MHz */
rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /*Set.48MHz Max.72MHz */
rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /*Set. 6MHz Max.14MHz */
rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /*Set.24MHz Max.36MHz */
rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /*Set.48MHz Max.72MHz */
rcc_set_usbpre(RCC_CFGR_USBPRE_PLL_CLK_NODIV); /*Set.48MHz Max.48MHz */
/*
* Sysclk runs with 48MHz -> 1 waitstates.
@@ -837,12 +843,13 @@ void rcc_clock_setup_in_hsi_out_48mhz(void)
rcc_ppre2_frequency = 48000000;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Set System Clock PLL at 24MHz from HSI
*/
void rcc_clock_setup_in_hsi_out_24mhz(void) {
void rcc_clock_setup_in_hsi_out_24mhz(void)
{
/* Enable internal high-speed oscillator. */
rcc_osc_on(HSI);
rcc_wait_for_osc_ready(HSI);
@@ -888,7 +895,7 @@ void rcc_clock_setup_in_hsi_out_24mhz(void) {
rcc_ppre2_frequency = 24000000;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Set System Clock PLL at 24MHz from HSE at 8MHz
*/
@@ -911,10 +918,10 @@ void rcc_clock_setup_in_hse_8mhz_out_24mhz(void)
* Set prescalers for AHB, ADC, ABP1, ABP2.
* Do this before touching the PLL (TODO: why?).
*/
rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 24MHz Max. 72MHz */
rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV2); /* Set. 12MHz Max. 14MHz */
rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_NODIV); /* Set. 24MHz Max. 36MHz */
rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 24MHz Max. 72MHz */
rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 24MHz Max. 72MHz */
rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV2); /* Set. 12MHz Max. 14MHz */
rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_NODIV); /* Set. 24MHz Max. 36MHz */
rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 24MHz Max. 72MHz */
/*
* Sysclk runs with 24MHz -> 0 waitstates.
@@ -951,7 +958,7 @@ void rcc_clock_setup_in_hse_8mhz_out_24mhz(void)
rcc_ppre2_frequency = 24000000;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Set System Clock PLL at 72MHz from HSE at 8MHz
*/
@@ -974,10 +981,10 @@ void rcc_clock_setup_in_hse_8mhz_out_72mhz(void)
* Set prescalers for AHB, ADC, ABP1, ABP2.
* Do this before touching the PLL (TODO: why?).
*/
rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */
rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 9MHz Max. 14MHz */
rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */
rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */
rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */
rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 9MHz Max. 14MHz */
rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */
rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */
/*
* Sysclk runs with 72MHz -> 2 waitstates.
@@ -1014,7 +1021,7 @@ void rcc_clock_setup_in_hse_8mhz_out_72mhz(void)
rcc_ppre2_frequency = 72000000;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Set System Clock PLL at 24MHz from HSE at 12MHz
*/
@@ -1037,10 +1044,10 @@ void rcc_clock_setup_in_hse_12mhz_out_72mhz(void)
* Set prescalers for AHB, ADC, ABP1, ABP2.
* Do this before touching the PLL (TODO: why?).
*/
rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */
rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */
rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */
rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */
rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */
rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */
rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */
rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */
/*
* Sysclk runs with 72MHz -> 2 waitstates.
@@ -1077,7 +1084,7 @@ void rcc_clock_setup_in_hse_12mhz_out_72mhz(void)
rcc_ppre2_frequency = 72000000;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Set System Clock PLL at 24MHz from HSE at 16MHz
*/
@@ -1100,10 +1107,10 @@ void rcc_clock_setup_in_hse_16mhz_out_72mhz(void)
* Set prescalers for AHB, ADC, ABP1, ABP2.
* Do this before touching the PLL (TODO: why?).
*/
rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */
rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */
rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */
rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */
rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */
rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */
rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */
rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */
/*
* Sysclk runs with 72MHz -> 2 waitstates.
@@ -1140,7 +1147,7 @@ void rcc_clock_setup_in_hse_16mhz_out_72mhz(void)
rcc_ppre2_frequency = 72000000;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Set System Clock PLL at 72MHz from HSE at 25MHz
*/
@@ -1164,10 +1171,10 @@ void rcc_clock_setup_in_hse_25mhz_out_72mhz(void)
* Set prescalers for AHB, ADC, ABP1, ABP2.
* Do this before touching the PLL (TODO: why?).
*/
rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */
rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */
rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */
rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */
rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */
rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */
rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */
rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */
/* Set pll2 prediv and multiplier */
rcc_set_prediv2(RCC_CFGR2_PREDIV2_DIV5);
@@ -1197,7 +1204,7 @@ void rcc_clock_setup_in_hse_25mhz_out_72mhz(void)
rcc_ppre2_frequency = 72000000;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief RCC Reset the backup domain
The backup domain register is reset to disable all controls.

4
lib/stm32/f1/rtc.c
View File

@@ -290,7 +290,9 @@ void rtc_auto_awake(osc_t clock_source, u32 prescale_val)
/* TODO: Not sure if this is necessary to just read the flag. */
PWR_CR |= PWR_CR_DBP;
if ((reg32 = RCC_BDCR & RCC_BDCR_RTCEN) != 0) {
reg32 = RCC_BDCR & RCC_BDCR_RTCEN;
if (reg32 != 0) {
rtc_awake_from_standby();
} else {
rtc_awake_from_off(clock_source);

8
lib/stm32/f1/timer.c
View File

@@ -46,11 +46,13 @@ in which case this file must be added to the compile list. */
@param[in] pol ::tim_ic_pol. Input Capture polarity.
*/
void timer_ic_set_polarity(u32 timer_peripheral, enum tim_ic_id ic, enum tim_ic_pol pol)
void timer_ic_set_polarity(u32 timer_peripheral, enum tim_ic_id ic,
enum tim_ic_pol pol)
{
if (pol)
if (pol) {
TIM_CCER(timer_peripheral) |= (0x2 << (ic * 4));
else
} else {
TIM_CCER(timer_peripheral) &= ~(0x2 << (ic * 4));
}
}

8
lib/stm32/f2/rcc.c
View File

@@ -27,8 +27,7 @@
u32 rcc_ppre1_frequency = 16000000;
u32 rcc_ppre2_frequency = 16000000;
const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] =
{
const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] = {
{ /* 120MHz */
.pllm = 8,
.plln = 240,
@@ -37,7 +36,8 @@ const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] =
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
FLASH_ACR_LATENCY_3WS,
.apb1_frequency = 30000000,
.apb2_frequency = 60000000,
},
@@ -358,7 +358,7 @@ void rcc_set_main_pll_hse(u32 pllm, u32 plln, u32 pllp, u32 pllq)
u32 rcc_system_clock_source(void)
{
/* Return the clock source which is used as system clock. */
return ((RCC_CFGR & 0x000c) >> 2);
return (RCC_CFGR & 0x000c) >> 2;
}
void rcc_clock_setup_hse_3v3(const clock_scale_t *clock)

357
lib/stm32/f4/adc.c
View File

@@ -4,44 +4,46 @@
@brief <b>libopencm3 STM32F4xx Analog to Digital Converters</b>
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
@author @htmlonly &copy; @endhtmlonly 2012
Ken Sarkies <ksarkies@internode.on.net>
@date 30 August 2012
This library supports the A/D Converter Control System in the STM32 series
of ARM Cortex Microcontrollers by ST Microelectronics.
Devices can have up to three A/D converters each with their own set of registers.
However all the A/D converters share a common clock which is prescaled from the APB2
clock by default by a minimum factor of 2 to a maximum of 8. The ADC resolution
can be set to 12, 10, 8 or 6 bits.
Devices can have up to three A/D converters each with their own set of
registers. However all the A/D converters share a common clock which is
prescaled from the APB2 clock by default by a minimum factor of 2 to a maximum
of 8. The ADC resolution can be set to 12, 10, 8 or 6 bits.
Each A/D converter has up to 19 channels:
@li On ADC1 the analog channels 16 is internally connected to the temperature
sensor, channel 17 to V<sub>REFINT</sub>, and channel 18 to V<sub>BATT</sub>.
@li On ADC2 and ADC3 the analog channels 16 - 18 are not used.
The conversions can occur as a one-off conversion whereby the process stops once
conversion is complete. The conversions can also be continuous wherein a new
conversion starts immediately the previous conversion has ended.
The conversions can occur as a one-off conversion whereby the process stops
once conversion is complete. The conversions can also be continuous wherein a
new conversion starts immediately the previous conversion has ended.
Conversion can occur as a single channel conversion or a scan of a group of
channels in either continuous or one-off mode. If more than one channel is converted
in a scan group, DMA must be used to transfer the data as there is only one
result register available. An interrupt can be set to occur at the end of
conversion, which occurs after all channels have been scanned.
channels in either continuous or one-off mode. If more than one channel is
converted in a scan group, DMA must be used to transfer the data as there is
only one result register available. An interrupt can be set to occur at the end
of conversion, which occurs after all channels have been scanned.
A discontinuous mode allows a subgroup of group of a channels to be converted in
bursts of a given length.
A discontinuous mode allows a subgroup of group of a channels to be converted
in bursts of a given length.
Injected conversions allow a second group of channels to be converted separately
from the regular group. An interrupt can be set to occur at the end of
conversion, which occurs after all channels have been scanned.
Injected conversions allow a second group of channels to be converted
separately from the regular group. An interrupt can be set to occur at the end
of conversion, which occurs after all channels have been scanned.
@section adc_f4_api_ex Basic ADC Handling API.
Example 1: Simple single channel conversion polled. Enable the peripheral clock
and ADC, reset ADC and set the prescaler divider. Set multiple mode to independent.
and ADC, reset ADC and set the prescaler divider. Set multiple mode to
independent.
@code
gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO1);
@@ -84,7 +86,7 @@ LGPL License Terms @ref lgpl_license
/**@{*/
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Off
Turn off the ADC to reduce power consumption to a few microamps.
@@ -97,12 +99,12 @@ void adc_off(u32 adc)
ADC_CR2(adc) &= ~ADC_CR2_ADON;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Analog Watchdog for Regular Conversions
The analog watchdog allows the monitoring of an analog signal between two threshold
levels. The thresholds must be preset. Comparison is done before data alignment
takes place, so the thresholds are left-aligned.
The analog watchdog allows the monitoring of an analog signal between two
threshold levels. The thresholds must be preset. Comparison is done before data
alignment takes place, so the thresholds are left-aligned.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
@@ -112,7 +114,7 @@ void adc_enable_analog_watchdog_regular(u32 adc)
ADC_CR1(adc) |= ADC_CR1_AWDEN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable Analog Watchdog for Regular Conversions
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -123,12 +125,12 @@ void adc_disable_analog_watchdog_regular(u32 adc)
ADC_CR1(adc) &= ~ADC_CR1_AWDEN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Analog Watchdog for Injected Conversions
The analog watchdog allows the monitoring of an analog signal between two threshold
levels. The thresholds must be preset. Comparison is done before data alignment
takes place, so the thresholds are left-aligned.
The analog watchdog allows the monitoring of an analog signal between two
threshold levels. The thresholds must be preset. Comparison is done before data
alignment takes place, so the thresholds are left-aligned.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
@@ -138,7 +140,7 @@ void adc_enable_analog_watchdog_injected(u32 adc)
ADC_CR1(adc) |= ADC_CR1_JAWDEN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable Analog Watchdog for Injected Conversions
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -149,7 +151,7 @@ void adc_disable_analog_watchdog_injected(u32 adc)
ADC_CR1(adc) &= ~ADC_CR1_JAWDEN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Discontinuous Mode for Regular Conversions
In this mode the ADC converts, on each trigger, a subgroup of up to 8 of the
@@ -161,17 +163,20 @@ the whole group has been converted, the next trigger will restart conversion
of the subgroup at the beginning of the whole group.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@param[in] length Unsigned int8. Number of channels in the group @ref adc_cr1_discnum
@param[in] length Unsigned int8. Number of channels in the group @ref
adc_cr1_discnum
*/
void adc_enable_discontinuous_mode_regular(u32 adc, u8 length)
{
if ( (length-1) > 7 ) return;
ADC_CR1(adc) |= ADC_CR1_DISCEN;
ADC_CR1(adc) |= ((length-1) << ADC_CR1_DISCNUM_SHIFT);
if ((length-1) > 7) {
return;
}
ADC_CR1(adc) |= ADC_CR1_DISCEN;
ADC_CR1(adc) |= ((length-1) << ADC_CR1_DISCNUM_SHIFT);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable Discontinuous Mode for Regular Conversions
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -182,7 +187,7 @@ void adc_disable_discontinuous_mode_regular(u32 adc)
ADC_CR1(adc) &= ~ADC_CR1_DISCEN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Discontinuous Mode for Injected Conversions
In this mode the ADC converts sequentially one channel of the defined group of
@@ -197,7 +202,7 @@ void adc_enable_discontinuous_mode_injected(u32 adc)
ADC_CR1(adc) |= ADC_CR1_JDISCEN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable Discontinuous Mode for Injected Conversions
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -208,7 +213,7 @@ void adc_disable_discontinuous_mode_injected(u32 adc)
ADC_CR1(adc) &= ~ADC_CR1_JDISCEN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Automatic Injected Conversions
The ADC converts a defined injected group of channels immediately after the
@@ -220,11 +225,11 @@ channels is disabled as required.
void adc_enable_automatic_injected_group_conversion(u32 adc)
{
adc_disable_external_trigger_injected(adc);
adc_disable_external_trigger_injected(adc);
ADC_CR1(adc) |= ADC_CR1_JAUTO;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable Automatic Injected Conversions
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -235,17 +240,18 @@ void adc_disable_automatic_injected_group_conversion(u32 adc)
ADC_CR1(adc) &= ~ADC_CR1_JAUTO;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Analog Watchdog for All Regular and/or Injected Channels
The analog watchdog allows the monitoring of an analog signal between two threshold
levels. The thresholds must be preset. Comparison is done before data alignment
takes place, so the thresholds are left-aligned.
The analog watchdog allows the monitoring of an analog signal between two
threshold levels. The thresholds must be preset. Comparison is done before data
alignment takes place, so the thresholds are left-aligned.
@note The analog watchdog must be enabled for either or both of the regular or
injected channels. If neither are enabled, the analog watchdog feature will be
disabled.
@ref adc_enable_analog_watchdog_injected, @ref adc_enable_analog_watchdog_regular.
@ref adc_enable_analog_watchdog_injected, @ref
adc_enable_analog_watchdog_regular.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
@@ -255,17 +261,18 @@ void adc_enable_analog_watchdog_on_all_channels(u32 adc)
ADC_CR1(adc) &= ~ADC_CR1_AWDSGL;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Analog Watchdog for a Selected Channel
The analog watchdog allows the monitoring of an analog signal between two threshold
levels. The thresholds must be preset. Comparison is done before data alignment
takes place, so the thresholds are left-aligned.
The analog watchdog allows the monitoring of an analog signal between two
threshold levels. The thresholds must be preset. Comparison is done before data
alignment takes place, so the thresholds are left-aligned.
@note The analog watchdog must be enabled for either or both of the regular or
injected channels. If neither are enabled, the analog watchdog feature will be
disabled. If both are enabled, the same channel number is monitored.
@ref adc_enable_analog_watchdog_injected, @ref adc_enable_analog_watchdog_regular.
@ref adc_enable_analog_watchdog_injected, @ref
adc_enable_analog_watchdog_regular.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@param[in] channel Unsigned int8. ADC channel number @ref adc_watchdog_channel
@@ -276,13 +283,14 @@ void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel)
u32 reg32;
reg32 = (ADC_CR1(adc) & ~ADC_CR1_AWDCH_MASK); /* Clear bits [4:0]. */
if (channel < 18)
if (channel < 18) {
reg32 |= channel;
}
ADC_CR1(adc) = reg32;
ADC_CR1(adc) |= ADC_CR1_AWDSGL;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Set Scan Mode
In this mode a conversion consists of a scan of the predefined set of channels,
@@ -297,7 +305,7 @@ void adc_enable_scan_mode(u32 adc)
ADC_CR1(adc) |= ADC_CR1_SCAN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable Scan Mode
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -308,7 +316,7 @@ void adc_disable_scan_mode(u32 adc)
ADC_CR1(adc) &= ~ADC_CR1_SCAN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Injected End-Of-Conversion Interrupt
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -319,7 +327,7 @@ void adc_enable_eoc_interrupt_injected(u32 adc)
ADC_CR1(adc) |= ADC_CR1_JEOCIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable Injected End-Of-Conversion Interrupt
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -330,7 +338,7 @@ void adc_disable_eoc_interrupt_injected(u32 adc)
ADC_CR1(adc) &= ~ADC_CR1_JEOCIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Analog Watchdog Interrupt
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -341,7 +349,7 @@ void adc_enable_awd_interrupt(u32 adc)
ADC_CR1(adc) |= ADC_CR1_AWDIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable Analog Watchdog Interrupt
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -352,7 +360,7 @@ void adc_disable_awd_interrupt(u32 adc)
ADC_CR1(adc) &= ~ADC_CR1_AWDIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Regular End-Of-Conversion Interrupt
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -363,7 +371,7 @@ void adc_enable_eoc_interrupt(u32 adc)
ADC_CR1(adc) |= ADC_CR1_EOCIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable Regular End-Of-Conversion Interrupt
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -374,7 +382,7 @@ void adc_disable_eoc_interrupt(u32 adc)
ADC_CR1(adc) &= ~ADC_CR1_EOCIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Software Triggered Conversion on Regular Channels
This starts conversion on a set of defined regular channels. It is cleared by
@@ -392,7 +400,7 @@ void adc_start_conversion_regular(u32 adc)
while (ADC_CR2(adc) & ADC_CR2_SWSTART);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Software Triggered Conversion on Injected Channels
This starts conversion on a set of defined injected channels. It is cleared by
@@ -410,7 +418,7 @@ void adc_start_conversion_injected(u32 adc)
while (ADC_CR2(adc) & ADC_CR2_JSWSTART);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Set the Data as Left Aligned
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -421,7 +429,7 @@ void adc_set_left_aligned(u32 adc)
ADC_CR2(adc) |= ADC_CR2_ALIGN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Set the Data as Right Aligned
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -432,7 +440,7 @@ void adc_set_right_aligned(u32 adc)
ADC_CR2(adc) &= ~ADC_CR2_ALIGN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable DMA Transfers
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -440,10 +448,10 @@ void adc_set_right_aligned(u32 adc)
void adc_enable_dma(u32 adc)
{
ADC_CR2(adc) |= ADC_CR2_DMA;
ADC_CR2(adc) |= ADC_CR2_DMA;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable DMA Transfers
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -451,10 +459,10 @@ void adc_enable_dma(u32 adc)
void adc_disable_dma(u32 adc)
{
ADC_CR2(adc) &= ~ADC_CR2_DMA;
ADC_CR2(adc) &= ~ADC_CR2_DMA;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Continuous Conversion Mode
In this mode the ADC starts a new conversion of a single channel or a channel
@@ -468,7 +476,7 @@ void adc_set_continuous_conversion_mode(u32 adc)
ADC_CR2(adc) |= ADC_CR2_CONT;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Single Conversion Mode
In this mode the ADC performs a conversion of one channel or a channel group
@@ -482,13 +490,14 @@ void adc_set_single_conversion_mode(u32 adc)
ADC_CR2(adc) &= ~ADC_CR2_CONT;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Set the Sample Time for a Single Channel
The sampling time can be selected in ADC clock cycles from 1.5 to 239.5.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@param[in] channel Unsigned int8. ADC Channel integer 0..18 or from @ref adc_channel
@param[in] channel Unsigned int8. ADC Channel integer 0..18 or from @ref
adc_channel
@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg
*/
@@ -509,11 +518,11 @@ void adc_set_sample_time(u32 adc, u8 channel, u8 time)
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Set the Sample Time for All Channels
The sampling time can be selected in ADC clock cycles from 1.5 to 239.5, same for
all channels.
The sampling time can be selected in ADC clock cycles from 1.5 to 239.5, same
for all channels.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg
@@ -524,16 +533,18 @@ void adc_set_sample_time_on_all_channels(u32 adc, u8 time)
u8 i;
u32 reg32 = 0;
for (i = 0; i <= 9; i++)
for (i = 0; i <= 9; i++) {
reg32 |= (time << (i * 3));
}
ADC_SMPR2(adc) = reg32;
for (i = 10; i <= 17; i++)
for (i = 10; i <= 17; i++) {
reg32 |= (time << ((i - 10) * 3));
}
ADC_SMPR1(adc) = reg32;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Set Analog Watchdog Upper Threshold
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -549,7 +560,7 @@ void adc_set_watchdog_high_threshold(u32 adc, u16 threshold)
ADC_HTR(adc) = reg32;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Set Analog Watchdog Lower Threshold
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -565,12 +576,12 @@ void adc_set_watchdog_low_threshold(u32 adc, u16 threshold)
ADC_LTR(adc) = reg32;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Set a Regular Channel Conversion Sequence
Define a sequence of channels to be converted as a regular group with a length
from 1 to 16 channels. If this is called during conversion, the current conversion
is reset and conversion begins again with the newly defined group.
from 1 to 16 channels. If this is called during conversion, the current
conversion is reset and conversion begins again with the newly defined group.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@param[in] length Unsigned int8. Number of channels in the group.
@@ -583,30 +594,34 @@ void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[])
u8 i = 0;
/* Maximum sequence length is 16 channels. */
if (length > 16)
if (length > 16) {
return;
}
for (i = 1; i <= length; i++) {
if (i <= 6)
if (i <= 6) {
reg32_3 |= (channel[i - 1] << ((i - 1) * 5));
if ((i > 6) & (i <= 12))
}
if ((i > 6) & (i <= 12)) {
reg32_2 |= (channel[i - 1] << ((i - 6 - 1) * 5));
if ((i > 12) & (i <= 16))
}
if ((i > 12) & (i <= 16)) {
reg32_1 |= (channel[i - 1] << ((i - 12 - 1) * 5));
}
}
reg32_1 |= ((length -1) << ADC_SQR1_L_LSB);
reg32_1 |= ((length - 1) << ADC_SQR1_L_LSB);
ADC_SQR1(adc) = reg32_1;
ADC_SQR2(adc) = reg32_2;
ADC_SQR3(adc) = reg32_3;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Set an Injected Channel Conversion Sequence
Defines a sequence of channels to be converted as an injected group with a length
from 1 to 4 channels. If this is called during conversion, the current conversion
is reset and conversion begins again with the newly defined group.
Defines a sequence of channels to be converted as an injected group with a
length from 1 to 4 channels. If this is called during conversion, the current
conversion is reset and conversion begins again with the newly defined group.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@param[in] length Unsigned int8. Number of channels in the group.
@@ -619,18 +634,20 @@ void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[])
u8 i = 0;
/* Maximum sequence length is 4 channels. */
if ((length-1) > 3)
if ((length-1) > 3) {
return;
}
for (i = 1; i <= length; i++)
for (i = 1; i <= length; i++) {
reg32 |= (channel[4 - i] << ((4 - i) * 5));
}
reg32 |= ((length - 1) << ADC_JSQR_JL_LSB);
ADC_JSQR(adc) = reg32;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Read the End-of-Conversion Flag
This flag is set after all channels of a regular or injected group have been
@@ -642,10 +659,10 @@ converted.
bool adc_eoc(u32 adc)
{
return ((ADC_SR(adc) & ADC_SR_EOC) != 0);
return (ADC_SR(adc) & ADC_SR_EOC) != 0;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Read the End-of-Conversion Flag for Injected Conversion
This flag is set after all channels of an injected group have been converted.
@@ -656,10 +673,10 @@ This flag is set after all channels of an injected group have been converted.
bool adc_eoc_injected(u32 adc)
{
return ((ADC_SR(adc) & ADC_SR_JEOC) != 0);
return (ADC_SR(adc) & ADC_SR_JEOC) != 0;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Read from the Regular Conversion Result Register
The result read back is 12 bits, right or left aligned within the first 16 bits.
@@ -672,15 +689,16 @@ an appropriate dual mode has been set @see adc_set_dual_mode.
u32 adc_read_regular(u32 adc)
{
return ADC_DR(adc);
return ADC_DR(adc);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Read from an Injected Conversion Result Register
The result read back from the selected injected result register (one of four) is
12 bits, right or left aligned within the first 16 bits. The result can have a
negative value if the injected channel offset has been set @see adc_set_injected_offset.
The result read back from the selected injected result register (one of four)
is 12 bits, right or left aligned within the first 16 bits. The result can have
a negative value if the injected channel offset has been set @see
adc_set_injected_offset.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@param[in] reg Unsigned int8. Register number (1 ... 4).
@@ -689,24 +707,24 @@ negative value if the injected channel offset has been set @see adc_set_injected
u32 adc_read_injected(u32 adc, u8 reg)
{
switch (reg) {
case 1:
return ADC_JDR1(adc);
case 2:
return ADC_JDR2(adc);
case 3:
return ADC_JDR3(adc);
case 4:
return ADC_JDR4(adc);
}
switch (reg) {
case 1:
return ADC_JDR1(adc);
case 2:
return ADC_JDR2(adc);
case 3:
return ADC_JDR3(adc);
case 4:
return ADC_JDR4(adc);
}
return 0;
}
/*-----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------*/
/** @brief ADC Set the Injected Channel Data Offset
This value is subtracted from the injected channel results after conversion
is complete, and can result in negative results. A separate value can be specified
This value is subtracted from the injected channel results after conversion is
complete, and can result in negative results. A separate value can be specified
for each injected data register.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -716,23 +734,23 @@ for each injected data register.
void adc_set_injected_offset(u32 adc, u8 reg, u32 offset)
{
switch (reg) {
case 1:
ADC_JOFR1(adc) = offset;
break;
case 2:
ADC_JOFR2(adc) = offset;
break;
case 3:
ADC_JOFR3(adc) = offset;
break;
case 4:
ADC_JOFR4(adc) = offset;
break;
}
switch (reg) {
case 1:
ADC_JOFR1(adc) = offset;
break;
case 2:
ADC_JOFR2(adc) = offset;
break;
case 3:
ADC_JOFR3(adc) = offset;
break;
case 4:
ADC_JOFR4(adc) = offset;
break;
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Power On
If the ADC is in power-down mode then it is powered up. The application needs
@@ -747,12 +765,13 @@ void adc_power_on(u32 adc)
ADC_CR2(adc) |= ADC_CR2_ADON;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Set Clock Prescale
The ADC clock taken from the APB2 clock can be scaled down by 2, 4, 6 or 8.
@param[in] prescale Unsigned int32. Prescale value for ADC Clock @ref adc_ccr_adcpre
@param[in] prescale Unsigned int32. Prescale value for ADC Clock @ref
adc_ccr_adcpre
*/
void adc_set_clk_prescale(u32 prescale)
@@ -761,7 +780,7 @@ void adc_set_clk_prescale(u32 prescale)
ADC_CCR = reg32;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Set Dual/Triple Mode
The multiple mode uses ADC1 as master, ADC2 and optionally ADC3 in a slave
@@ -777,16 +796,17 @@ void adc_set_multi_mode(u32 mode)
ADC_CCR |= mode;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable an External Trigger for Regular Channels
This enables an external trigger for set of defined regular channels, and sets the
polarity of the trigger event: rising or falling edge or both. Note that if the
trigger polarity is zero, triggering is disabled.
This enables an external trigger for set of defined regular channels, and sets
the polarity of the trigger event: rising or falling edge or both. Note that if
the trigger polarity is zero, triggering is disabled.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@param[in] trigger Unsigned int32. Trigger identifier @ref adc_trigger_regular
@param[in] polarity Unsigned int32. Trigger polarity @ref adc_trigger_polarity_regular
@param[in] polarity Unsigned int32. Trigger polarity @ref
adc_trigger_polarity_regular
*/
void adc_enable_external_trigger_regular(u32 adc, u32 trigger, u32 polarity)
@@ -798,7 +818,7 @@ void adc_enable_external_trigger_regular(u32 adc, u32 trigger, u32 polarity)
ADC_CR2(adc) = reg32;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable an External Trigger for Regular Channels
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -809,15 +829,16 @@ void adc_disable_external_trigger_regular(u32 adc)
ADC_CR2(adc) &= ~ADC_CR2_EXTEN_MASK;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable an External Trigger for Injected Channels
This enables an external trigger for set of defined injected channels, and sets the
polarity of the trigger event: rising or falling edge or both.
This enables an external trigger for set of defined injected channels, and sets
the polarity of the trigger event: rising or falling edge or both.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@param[in] trigger Unsigned int8. Trigger identifier @ref adc_trigger_injected
@param[in] polarity Unsigned int32. Trigger polarity @ref adc_trigger_polarity_injected
@param[in] polarity Unsigned int32. Trigger polarity @ref
adc_trigger_polarity_injected
*/
void adc_enable_external_trigger_injected(u32 adc, u32 trigger, u32 polarity)
@@ -829,7 +850,7 @@ void adc_enable_external_trigger_injected(u32 adc, u32 trigger, u32 polarity)
ADC_CR2(adc) = reg32;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable an External Trigger for Injected Channels
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -840,11 +861,11 @@ void adc_disable_external_trigger_injected(u32 adc)
ADC_CR2(adc) &= ~ADC_CR2_JEXTEN_MASK;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Set Resolution
ADC Resolution can be reduced from 12 bits to 10, 8 or 6 bits for a corresponding
reduction in conversion time (resolution + 3 ADC clock cycles).
ADC Resolution can be reduced from 12 bits to 10, 8 or 6 bits for a
corresponding reduction in conversion time (resolution + 3 ADC clock cycles).
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@param[in] resolution Unsigned int8. Resolution value @ref adc_cr1_res
@@ -859,7 +880,7 @@ void adc_set_resolution(u32 adc, u16 resolution)
ADC_CR1(adc) = reg32;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable the Overrun Interrupt
The overrun interrupt is generated when data is not read from a result register
@@ -874,7 +895,7 @@ void adc_enable_overrun_interrupt(u32 adc)
ADC_CR1(adc) |= ADC_CR1_OVRIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable the Overrun Interrupt
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@@ -885,12 +906,12 @@ void adc_disable_overrun_interrupt(u32 adc)
ADC_CR1(adc) &= ~ADC_CR1_OVRIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Read the Overrun Flag
The overrun flag is set when data is not read from a result register before the next
conversion is written. If DMA is enabled, all transfers are terminated and any
conversion sequence is aborted.
The overrun flag is set when data is not read from a result register before the
next conversion is written. If DMA is enabled, all transfers are terminated and
any conversion sequence is aborted.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
@returns Unsigned int32 conversion result.
@@ -898,10 +919,10 @@ conversion sequence is aborted.
bool adc_get_overrun_flag(u32 adc)
{
return (ADC_SR(adc) & ADC_SR_OVR);
return ADC_SR(adc) & ADC_SR_OVR;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Clear Overrun Flags
The overrun flag is cleared. Note that if an overrun occurs, DMA is terminated.
@@ -918,7 +939,7 @@ void adc_clear_overrun_flag(u32 adc)
ADC_SR(adc) &= ~ADC_SR_OVR;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable an EOC for Each Conversion
The EOC is set after each conversion in a sequence rather than at the end of the
@@ -932,11 +953,11 @@ void adc_eoc_after_each(u32 adc)
ADC_CR2(adc) |= ADC_CR2_EOCS;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable the EOC for Each Conversion
The EOC is set at the end of each sequence rather than after each conversion in the
sequence. Overrun detection is enabled always.
The EOC is set at the end of each sequence rather than after each conversion in
the sequence. Overrun detection is enabled always.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
@@ -946,11 +967,11 @@ void adc_eoc_after_group(u32 adc)
ADC_CR2(adc) &= ~ADC_CR2_EOCS;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Set DMA to Continue
This must be set to allow DMA to continue to operate after the last conversion in
the DMA sequence. This allows DMA to be used in continuous circular mode.
This must be set to allow DMA to continue to operate after the last conversion
in the DMA sequence. This allows DMA to be used in continuous circular mode.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
@@ -960,7 +981,7 @@ void adc_set_dma_continue(u32 adc)
ADC_CR2(adc) |= ADC_CR2_DDS;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Set DMA to Terminate
This must be set to allow DMA to terminate after the last conversion in the DMA
@@ -973,7 +994,7 @@ void adc_set_dma_terminate(u32 adc)
{
ADC_CR2(adc) &= ~ADC_CR2_DDS;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Read the Analog Watchdog Flag
This flag is set when the converted voltage crosses the high or low thresholds.
@@ -984,10 +1005,10 @@ This flag is set when the converted voltage crosses the high or low thresholds.
bool adc_awd(u32 adc)
{
return (ADC_SR(adc) & ADC_SR_AWD);
return ADC_SR(adc) & ADC_SR_AWD;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable The Temperature Sensor
This enables both the sensor and the reference voltage measurements on channels
@@ -1001,7 +1022,7 @@ void adc_enable_temperature_sensor()
ADC_CCR |= ADC_CCR_TSVREFE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable The Temperature Sensor
Disabling this will reduce power consumption from the sensor and the reference
@@ -1015,7 +1036,7 @@ void adc_disable_temperature_sensor()
ADC_CCR &= ~ADC_CCR_TSVREFE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/**@}*/

5
lib/stm32/f4/pwr.c
View File

@@ -38,8 +38,9 @@ LGPL License Terms @ref lgpl_license
void pwr_set_vos_scale(vos_scale_t scale)
{
if (scale == SCALE1)
if (scale == SCALE1) {
PWR_CR |= PWR_CR_VOS;
else if (scale == SCALE2)
} else if (scale == SCALE2) {
PWR_CR &= PWR_CR_VOS;
}
}

733
lib/stm32/f4/rcc.c
View File

@@ -28,506 +28,513 @@
u32 rcc_ppre1_frequency = 16000000;
u32 rcc_ppre2_frequency = 16000000;
const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] =
{
{ /* 48MHz */
.pllm = 8,
.plln = 96,
.pllp = 2,
.pllq = 2,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.power_save = 1,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS,
.apb1_frequency = 12000000,
.apb2_frequency = 24000000,
},
{ /* 120MHz */
.pllm = 8,
.plln = 240,
.pllp = 2,
.pllq = 5,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.power_save = 1,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS,
.apb1_frequency = 30000000,
.apb2_frequency = 60000000,
},
{ /* 168MHz */
.pllm = 8,
.plln = 336,
.pllp = 2,
.pllq = 7,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_5WS,
.apb1_frequency = 42000000,
.apb2_frequency = 84000000,
},
const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] = {
{ /* 48MHz */
.pllm = 8,
.plln = 96,
.pllp = 2,
.pllq = 2,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.power_save = 1,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
FLASH_ACR_LATENCY_3WS,
.apb1_frequency = 12000000,
.apb2_frequency = 24000000,
},
{ /* 120MHz */
.pllm = 8,
.plln = 240,
.pllp = 2,
.pllq = 5,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.power_save = 1,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
FLASH_ACR_LATENCY_3WS,
.apb1_frequency = 30000000,
.apb2_frequency = 60000000,
},
{ /* 168MHz */
.pllm = 8,
.plln = 336,
.pllp = 2,
.pllq = 7,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
FLASH_ACR_LATENCY_5WS,
.apb1_frequency = 42000000,
.apb2_frequency = 84000000,
},
};
const clock_scale_t hse_12mhz_3v3[CLOCK_3V3_END] =
{
{ /* 48MHz */
.pllm = 12,
.plln = 96,
.pllp = 2,
.pllq = 2,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.power_save = 1,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS,
.apb1_frequency = 12000000,
.apb2_frequency = 24000000,
},
{ /* 120MHz */
.pllm = 12,
.plln = 240,
.pllp = 2,
.pllq = 5,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.power_save = 1,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS,
.apb1_frequency = 30000000,
.apb2_frequency = 60000000,
},
{ /* 168MHz */
.pllm = 12,
.plln = 336,
.pllp = 2,
.pllq = 7,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_5WS,
.apb1_frequency = 42000000,
.apb2_frequency = 84000000,
},
const clock_scale_t hse_12mhz_3v3[CLOCK_3V3_END] = {
{ /* 48MHz */
.pllm = 12,
.plln = 96,
.pllp = 2,
.pllq = 2,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.power_save = 1,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
FLASH_ACR_LATENCY_3WS,
.apb1_frequency = 12000000,
.apb2_frequency = 24000000,
},
{ /* 120MHz */
.pllm = 12,
.plln = 240,
.pllp = 2,
.pllq = 5,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.power_save = 1,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
FLASH_ACR_LATENCY_3WS,
.apb1_frequency = 30000000,
.apb2_frequency = 60000000,
},
{ /* 168MHz */
.pllm = 12,
.plln = 336,
.pllp = 2,
.pllq = 7,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
FLASH_ACR_LATENCY_5WS,
.apb1_frequency = 42000000,
.apb2_frequency = 84000000,
},
};
const clock_scale_t hse_16mhz_3v3[CLOCK_3V3_END] =
{
{ /* 48MHz */
.pllm = 16,
.plln = 96,
.pllp = 2,
.pllq = 2,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.power_save = 1,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS,
.apb1_frequency = 12000000,
.apb2_frequency = 24000000,
},
{ /* 120MHz */
.pllm = 16,
.plln = 240,
.pllp = 2,
.pllq = 5,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.power_save = 1,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS,
.apb1_frequency = 30000000,
.apb2_frequency = 60000000,
},
{ /* 168MHz */
.pllm = 16,
.plln = 336,
.pllp = 2,
.pllq = 7,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_5WS,
.apb1_frequency = 42000000,
.apb2_frequency = 84000000,
},
const clock_scale_t hse_16mhz_3v3[CLOCK_3V3_END] = {
{ /* 48MHz */
.pllm = 16,
.plln = 96,
.pllp = 2,
.pllq = 2,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.power_save = 1,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
FLASH_ACR_LATENCY_3WS,
.apb1_frequency = 12000000,
.apb2_frequency = 24000000,
},
{ /* 120MHz */
.pllm = 16,
.plln = 240,
.pllp = 2,
.pllq = 5,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.power_save = 1,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
FLASH_ACR_LATENCY_3WS,
.apb1_frequency = 30000000,
.apb2_frequency = 60000000,
},
{ /* 168MHz */
.pllm = 16,
.plln = 336,
.pllp = 2,
.pllq = 7,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
FLASH_ACR_LATENCY_5WS,
.apb1_frequency = 42000000,
.apb2_frequency = 84000000,
},
};
void rcc_osc_ready_int_clear(osc_t osc)
{
switch (osc) {
case PLL:
RCC_CIR |= RCC_CIR_PLLRDYC;
break;
case HSE:
RCC_CIR |= RCC_CIR_HSERDYC;
break;
case HSI:
RCC_CIR |= RCC_CIR_HSIRDYC;
break;
case LSE:
RCC_CIR |= RCC_CIR_LSERDYC;
break;
case LSI:
RCC_CIR |= RCC_CIR_LSIRDYC;
break;
}
switch (osc) {
case PLL:
RCC_CIR |= RCC_CIR_PLLRDYC;
break;
case HSE:
RCC_CIR |= RCC_CIR_HSERDYC;
break;
case HSI:
RCC_CIR |= RCC_CIR_HSIRDYC;
break;
case LSE:
RCC_CIR |= RCC_CIR_LSERDYC;
break;
case LSI:
RCC_CIR |= RCC_CIR_LSIRDYC;
break;
}
}
void rcc_osc_ready_int_enable(osc_t osc)
{
switch (osc) {
case PLL:
RCC_CIR |= RCC_CIR_PLLRDYIE;
break;
case HSE:
RCC_CIR |= RCC_CIR_HSERDYIE;
break;
case HSI:
RCC_CIR |= RCC_CIR_HSIRDYIE;
break;
case LSE:
RCC_CIR |= RCC_CIR_LSERDYIE;
break;
case LSI:
RCC_CIR |= RCC_CIR_LSIRDYIE;
break;
}
switch (osc) {
case PLL:
RCC_CIR |= RCC_CIR_PLLRDYIE;
break;
case HSE:
RCC_CIR |= RCC_CIR_HSERDYIE;
break;
case HSI:
RCC_CIR |= RCC_CIR_HSIRDYIE;
break;
case LSE:
RCC_CIR |= RCC_CIR_LSERDYIE;
break;
case LSI:
RCC_CIR |= RCC_CIR_LSIRDYIE;
break;
}
}
void rcc_osc_ready_int_disable(osc_t osc)
{
switch (osc) {
case PLL:
RCC_CIR &= ~RCC_CIR_PLLRDYIE;
break;
case HSE:
RCC_CIR &= ~RCC_CIR_HSERDYIE;
break;
case HSI:
RCC_CIR &= ~RCC_CIR_HSIRDYIE;
break;
case LSE:
RCC_CIR &= ~RCC_CIR_LSERDYIE;
break;
case LSI:
RCC_CIR &= ~RCC_CIR_LSIRDYIE;
break;
}
switch (osc) {
case PLL:
RCC_CIR &= ~RCC_CIR_PLLRDYIE;
break;
case HSE:
RCC_CIR &= ~RCC_CIR_HSERDYIE;
break;
case HSI:
RCC_CIR &= ~RCC_CIR_HSIRDYIE;
break;
case LSE:
RCC_CIR &= ~RCC_CIR_LSERDYIE;
break;
case LSI:
RCC_CIR &= ~RCC_CIR_LSIRDYIE;
break;
}
}
int rcc_osc_ready_int_flag(osc_t osc)
{
switch (osc) {
case PLL:
return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0);
break;
case HSE:
return ((RCC_CIR & RCC_CIR_HSERDYF) != 0);
break;
case HSI:
return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0);
break;
case LSE:
return ((RCC_CIR & RCC_CIR_LSERDYF) != 0);
break;
case LSI:
return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0);
break;
}
switch (osc) {
case PLL:
return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0);
break;
case HSE:
return ((RCC_CIR & RCC_CIR_HSERDYF) != 0);
break;
case HSI:
return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0);
break;
case LSE:
return ((RCC_CIR & RCC_CIR_LSERDYF) != 0);
break;
case LSI:
return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0);
break;
}
cm3_assert_not_reached();
cm3_assert_not_reached();
}
void rcc_css_int_clear(void)
{
RCC_CIR |= RCC_CIR_CSSC;
RCC_CIR |= RCC_CIR_CSSC;
}
int rcc_css_int_flag(void)
{
return ((RCC_CIR & RCC_CIR_CSSF) != 0);
return ((RCC_CIR & RCC_CIR_CSSF) != 0);
}
void rcc_wait_for_osc_ready(osc_t osc)
{
switch (osc) {
case PLL:
while ((RCC_CR & RCC_CR_PLLRDY) == 0);
break;
case HSE:
while ((RCC_CR & RCC_CR_HSERDY) == 0);
break;
case HSI:
while ((RCC_CR & RCC_CR_HSIRDY) == 0);
break;
case LSE:
while ((RCC_BDCR & RCC_BDCR_LSERDY) == 0);
break;
case LSI:
while ((RCC_CSR & RCC_CSR_LSIRDY) == 0);
break;
}
switch (osc) {
case PLL:
while ((RCC_CR & RCC_CR_PLLRDY) == 0);
break;
case HSE:
while ((RCC_CR & RCC_CR_HSERDY) == 0);
break;
case HSI:
while ((RCC_CR & RCC_CR_HSIRDY) == 0);
break;
case LSE:
while ((RCC_BDCR & RCC_BDCR_LSERDY) == 0);
break;
case LSI:
while ((RCC_CSR & RCC_CSR_LSIRDY) == 0);
break;
}
}
void rcc_wait_for_sysclk_status(osc_t osc)
{
switch (osc) {
case PLL:
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_PLL);
break;
case HSE:
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSE);
break;
case HSI:
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSI);
break;
default:
/* Shouldn't be reached. */
break;
}
switch (osc) {
case PLL:
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_PLL);
break;
case HSE:
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSE);
break;
case HSI:
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSI);
break;
default:
/* Shouldn't be reached. */
break;
}
}
void rcc_osc_on(osc_t osc)
{
switch (osc) {
case PLL:
RCC_CR |= RCC_CR_PLLON;
break;
case HSE:
RCC_CR |= RCC_CR_HSEON;
break;
case HSI:
RCC_CR |= RCC_CR_HSION;
break;
case LSE:
RCC_BDCR |= RCC_BDCR_LSEON;
break;
case LSI:
RCC_CSR |= RCC_CSR_LSION;
break;
}
switch (osc) {
case PLL:
RCC_CR |= RCC_CR_PLLON;
break;
case HSE:
RCC_CR |= RCC_CR_HSEON;
break;
case HSI:
RCC_CR |= RCC_CR_HSION;
break;
case LSE:
RCC_BDCR |= RCC_BDCR_LSEON;
break;
case LSI:
RCC_CSR |= RCC_CSR_LSION;
break;
}
}
void rcc_osc_off(osc_t osc)
{
switch (osc) {
case PLL:
RCC_CR &= ~RCC_CR_PLLON;
break;
case HSE:
RCC_CR &= ~RCC_CR_HSEON;
break;
case HSI:
RCC_CR &= ~RCC_CR_HSION;
break;
case LSE:
RCC_BDCR &= ~RCC_BDCR_LSEON;
break;
case LSI:
RCC_CSR &= ~RCC_CSR_LSION;
break;
}
switch (osc) {
case PLL:
RCC_CR &= ~RCC_CR_PLLON;
break;
case HSE:
RCC_CR &= ~RCC_CR_HSEON;
break;
case HSI:
RCC_CR &= ~RCC_CR_HSION;
break;
case LSE:
RCC_BDCR &= ~RCC_BDCR_LSEON;
break;
case LSI:
RCC_CSR &= ~RCC_CSR_LSION;
break;
}
}
void rcc_css_enable(void)
{
RCC_CR |= RCC_CR_CSSON;
RCC_CR |= RCC_CR_CSSON;
}
void rcc_css_disable(void)
{
RCC_CR &= ~RCC_CR_CSSON;
RCC_CR &= ~RCC_CR_CSSON;
}
void rcc_osc_bypass_enable(osc_t osc)
{
switch (osc) {
case HSE:
RCC_CR |= RCC_CR_HSEBYP;
break;
case LSE:
RCC_BDCR |= RCC_BDCR_LSEBYP;
break;
case PLL:
case HSI:
case LSI:
/* Do nothing, only HSE/LSE allowed here. */
break;
}
switch (osc) {
case HSE:
RCC_CR |= RCC_CR_HSEBYP;
break;
case LSE:
RCC_BDCR |= RCC_BDCR_LSEBYP;
break;
case PLL:
case HSI:
case LSI:
/* Do nothing, only HSE/LSE allowed here. */
break;
}
}
void rcc_osc_bypass_disable(osc_t osc)
{
switch (osc) {
case HSE:
RCC_CR &= ~RCC_CR_HSEBYP;
break;
case LSE:
RCC_BDCR &= ~RCC_BDCR_LSEBYP;
break;
case PLL:
case HSI:
case LSI:
/* Do nothing, only HSE/LSE allowed here. */
break;
}
switch (osc) {
case HSE:
RCC_CR &= ~RCC_CR_HSEBYP;
break;
case LSE:
RCC_BDCR &= ~RCC_BDCR_LSEBYP;
break;
case PLL:
case HSI:
case LSI:
/* Do nothing, only HSE/LSE allowed here. */
break;
}
}
void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en)
{
*reg |= en;
*reg |= en;
}
void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en)
{
*reg &= ~en;
*reg &= ~en;
}
void rcc_peripheral_reset(volatile u32 *reg, u32 reset)
{
*reg |= reset;
*reg |= reset;
}
void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset)
{
*reg &= ~clear_reset;
*reg &= ~clear_reset;
}
void rcc_set_sysclk_source(u32 clk)
{
u32 reg32;
u32 reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 1) | (1 << 0));
RCC_CFGR = (reg32 | clk);
reg32 = RCC_CFGR;
reg32 &= ~((1 << 1) | (1 << 0));
RCC_CFGR = (reg32 | clk);
}
void rcc_set_pll_source(u32 pllsrc)
{
u32 reg32;
u32 reg32;
reg32 = RCC_PLLCFGR;
reg32 &= ~(1 << 22);
RCC_PLLCFGR = (reg32 | (pllsrc << 22));
reg32 = RCC_PLLCFGR;
reg32 &= ~(1 << 22);
RCC_PLLCFGR = (reg32 | (pllsrc << 22));
}
void rcc_set_ppre2(u32 ppre2)
{
u32 reg32;
u32 reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 13) | (1 << 14) | (1 << 15));
RCC_CFGR = (reg32 | (ppre2 << 13));
reg32 = RCC_CFGR;
reg32 &= ~((1 << 13) | (1 << 14) | (1 << 15));
RCC_CFGR = (reg32 | (ppre2 << 13));
}
void rcc_set_ppre1(u32 ppre1)
{
u32 reg32;
u32 reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 10) | (1 << 11) | (1 << 12));
RCC_CFGR = (reg32 | (ppre1 << 10));
reg32 = RCC_CFGR;
reg32 &= ~((1 << 10) | (1 << 11) | (1 << 12));
RCC_CFGR = (reg32 | (ppre1 << 10));
}
void rcc_set_hpre(u32 hpre)
{
u32 reg32;
u32 reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7));
RCC_CFGR = (reg32 | (hpre << 4));
reg32 = RCC_CFGR;
reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7));
RCC_CFGR = (reg32 | (hpre << 4));
}
void rcc_set_rtcpre(u32 rtcpre)
{
u32 reg32;
u32 reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 16) | (1 << 17) | (1 << 18) | (1 << 19) | (1 << 20));
RCC_CFGR = (reg32 | (rtcpre << 16));
reg32 = RCC_CFGR;
reg32 &= ~((1 << 16) | (1 << 17) | (1 << 18) | (1 << 19) | (1 << 20));
RCC_CFGR = (reg32 | (rtcpre << 16));
}
void rcc_set_main_pll_hsi(u32 pllm, u32 plln, u32 pllp, u32 pllq)
{
RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
(plln << RCC_PLLCFGR_PLLN_SHIFT) |
(((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) |
(pllq << RCC_PLLCFGR_PLLQ_SHIFT);
RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
(plln << RCC_PLLCFGR_PLLN_SHIFT) |
(((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) |
(pllq << RCC_PLLCFGR_PLLQ_SHIFT);
}
void rcc_set_main_pll_hse(u32 pllm, u32 plln, u32 pllp, u32 pllq)
{
RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
(plln << RCC_PLLCFGR_PLLN_SHIFT) |
(((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) |
RCC_PLLCFGR_PLLSRC |
(pllq << RCC_PLLCFGR_PLLQ_SHIFT);
RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
(plln << RCC_PLLCFGR_PLLN_SHIFT) |
(((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) |
RCC_PLLCFGR_PLLSRC |
(pllq << RCC_PLLCFGR_PLLQ_SHIFT);
}
u32 rcc_system_clock_source(void)
{
/* Return the clock source which is used as system clock. */
return ((RCC_CFGR & 0x000c) >> 2);
/* Return the clock source which is used as system clock. */
return (RCC_CFGR & 0x000c) >> 2;
}
void rcc_clock_setup_hse_3v3(const clock_scale_t *clock)
{
/* Enable internal high-speed oscillator. */
rcc_osc_on(HSI);
rcc_wait_for_osc_ready(HSI);
/* Enable internal high-speed oscillator. */
rcc_osc_on(HSI);
rcc_wait_for_osc_ready(HSI);
/* Select HSI as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_HSI);
/* Select HSI as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_HSI);
/* Enable external high-speed oscillator 8MHz. */
rcc_osc_on(HSE);
rcc_wait_for_osc_ready(HSE);
/* Enable external high-speed oscillator 8MHz. */
rcc_osc_on(HSE);
rcc_wait_for_osc_ready(HSE);
/* Enable/disable high performance mode */
if (!clock->power_save)
pwr_set_vos_scale(SCALE1);
else
pwr_set_vos_scale(SCALE2);
/* Enable/disable high performance mode */
if (!clock->power_save) {
pwr_set_vos_scale(SCALE1);
} else {
pwr_set_vos_scale(SCALE2);
}
/*
* Set prescalers for AHB, ADC, ABP1, ABP2.
* Do this before touching the PLL (TODO: why?).
*/
rcc_set_hpre(clock->hpre);
rcc_set_ppre1(clock->ppre1);
rcc_set_ppre2(clock->ppre2);
/*
* Set prescalers for AHB, ADC, ABP1, ABP2.
* Do this before touching the PLL (TODO: why?).
*/
rcc_set_hpre(clock->hpre);
rcc_set_ppre1(clock->ppre1);
rcc_set_ppre2(clock->ppre2);
rcc_set_main_pll_hse(clock->pllm, clock->plln,
clock->pllp, clock->pllq);
rcc_set_main_pll_hse(clock->pllm, clock->plln,
clock->pllp, clock->pllq);
/* Enable PLL oscillator and wait for it to stabilize. */
rcc_osc_on(PLL);
rcc_wait_for_osc_ready(PLL);
/* Enable PLL oscillator and wait for it to stabilize. */
rcc_osc_on(PLL);
rcc_wait_for_osc_ready(PLL);
/* Configure flash settings. */
flash_set_ws(clock->flash_config);
/* Configure flash settings. */
flash_set_ws(clock->flash_config);
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
/* Wait for PLL clock to be selected. */
rcc_wait_for_sysclk_status(PLL);
/* Wait for PLL clock to be selected. */
rcc_wait_for_sysclk_status(PLL);
/* Set the peripheral clock frequencies used. */
rcc_ppre1_frequency = clock->apb1_frequency;
rcc_ppre2_frequency = clock->apb2_frequency;
/* Set the peripheral clock frequencies used. */
rcc_ppre1_frequency = clock->apb1_frequency;
rcc_ppre2_frequency = clock->apb2_frequency;
/* Disable internal high-speed oscillator. */
rcc_osc_off(HSI);
/* Disable internal high-speed oscillator. */
rcc_osc_off(HSI);
}
void rcc_backupdomain_reset(void)
{
/* Set the backup domain software reset. */
RCC_BDCR |= RCC_BDCR_BDRST;
/* Set the backup domain software reset. */
RCC_BDCR |= RCC_BDCR_BDRST;
/* Clear the backup domain software reset. */
RCC_BDCR &= ~RCC_BDCR_BDRST;
/* Clear the backup domain software reset. */
RCC_BDCR &= ~RCC_BDCR_BDRST;
}

56
lib/stm32/f4/rtc.c
View File

@@ -39,9 +39,10 @@ LGPL License Terms @ref lgpl_license
@warning You must unlock the registers before using this function
*/
void rtc_enable_wakeup_timer(void) {
RTC_CR |= RTC_CR_WUTE | (RTC_CR_OSEL_WAKEUP << RTC_CR_OSEL_SHIFT);
rtc_enable_wakeup_timer_interrupt();
void rtc_enable_wakeup_timer(void)
{
RTC_CR |= RTC_CR_WUTE | (RTC_CR_OSEL_WAKEUP << RTC_CR_OSEL_SHIFT);
rtc_enable_wakeup_timer_interrupt();
}
/*---------------------------------------------------------------------------*/
@@ -49,9 +50,10 @@ void rtc_enable_wakeup_timer(void) {
@warning You must unlock the registers before using this function
*/
void rtc_disable_wakeup_timer(void) {
RTC_CR &= ~RTC_CR_WUTE;
rtc_disable_wakeup_timer_interrupt();
void rtc_disable_wakeup_timer(void)
{
RTC_CR &= ~RTC_CR_WUTE;
rtc_disable_wakeup_timer_interrupt();
}
/*---------------------------------------------------------------------------*/
@@ -59,20 +61,23 @@ void rtc_disable_wakeup_timer(void) {
@warning You must unlock the registers before using this function
*/
void rtc_enable_wakeup_timer_interrupt(void) {
// FTFM:
// To enable the RTC Wakeup interrupt, the following sequence is required:
// 1. Configure and enable the EXTI Line 22 in interrupt mode and select the
// rising edge sensitivity.
exti_enable_request(EXTI22);
exti_set_trigger(EXTI22, EXTI_TRIGGER_RISING);
void rtc_enable_wakeup_timer_interrupt(void)
{
/* FTFM:
* To enable the RTC Wakeup interrupt, the following sequence is
* required:
* 1. Configure and enable the EXTI Line 22 in interrupt mode and
* select the rising edge sensitivity.
*/
exti_enable_request(EXTI22);
exti_set_trigger(EXTI22, EXTI_TRIGGER_RISING);
// 2. Configure and enable the RTC_WKUP IRQ channel in the NVIC.
nvic_enable_irq(NVIC_RTC_WKUP_IRQ);
nvic_set_priority(NVIC_RTC_WKUP_IRQ, 1);
/* 2. Configure and enable the RTC_WKUP IRQ channel in the NVIC. */
nvic_enable_irq(NVIC_RTC_WKUP_IRQ);
nvic_set_priority(NVIC_RTC_WKUP_IRQ, 1);
// 3. Configure the RTC to generate the RTC wakeup timer event.
RTC_CR |= RTC_CR_WUTIE; // Enable the interrupt
/* 3. Configure the RTC to generate the RTC wakeup timer event. */
RTC_CR |= RTC_CR_WUTIE; /* Enable the interrupt */
}
/*---------------------------------------------------------------------------*/
@@ -80,13 +85,14 @@ void rtc_enable_wakeup_timer_interrupt(void) {
@warning You must unlock the registers before using this function
*/
void rtc_disable_wakeup_timer_interrupt(void) {
// 1. Disable EXTI Line 22
exti_disable_request(EXTI22);
void rtc_disable_wakeup_timer_interrupt(void)
{
/* 1. Disable EXTI Line 22 */
exti_disable_request(EXTI22);
// 2. Disable RTC_WKUP IRQ channel in the NVIC.
nvic_disable_irq(NVIC_RTC_WKUP_IRQ);
/* 2. Disable RTC_WKUP IRQ channel in the NVIC. */
nvic_disable_irq(NVIC_RTC_WKUP_IRQ);
// 3. Disable RTC wakeup timer event.
RTC_CR &= ~RTC_CR_WUTIE;
/* 3. Disable RTC wakeup timer event. */
RTC_CR &= ~RTC_CR_WUTIE;
}

2
lib/stm32/l1/flash.c
View File

@@ -49,4 +49,4 @@ void flash_set_ws(u32 ws)
reg32 &= ~(1 << 0);
reg32 |= ws;
FLASH_ACR = reg32;
}
}

26
lib/stm32/l1/rcc.c
View File

@@ -29,8 +29,7 @@
u32 rcc_ppre1_frequency = 2097000;
u32 rcc_ppre2_frequency = 2097000;
const clock_scale_t clock_config[CLOCK_CONFIG_END] =
{
const clock_scale_t clock_config[CLOCK_CONFIG_END] = {
{ /* 24MHz PLL from HSI */
.pll_source = RCC_CFGR_PLLSRC_HSI_CLK,
.pll_mul = RCC_CFGR_PLLMUL_MUL3,
@@ -232,16 +231,20 @@ void rcc_wait_for_sysclk_status(osc_t osc)
{
switch (osc) {
case PLL:
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_SYSCLKSEL_PLLCLK);
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) !=
RCC_CFGR_SWS_SYSCLKSEL_PLLCLK);
break;
case HSE:
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_SYSCLKSEL_HSECLK);
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) !=
RCC_CFGR_SWS_SYSCLKSEL_HSECLK);
break;
case HSI:
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_SYSCLKSEL_HSICLK);
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) !=
RCC_CFGR_SWS_SYSCLKSEL_HSICLK);
break;
case MSI:
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_SYSCLKSEL_MSICLK);
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) !=
RCC_CFGR_SWS_SYSCLKSEL_MSICLK);
break;
default:
/* Shouldn't be reached. */
@@ -434,7 +437,7 @@ void rcc_set_rtcpre(u32 rtcpre)
u32 rcc_system_clock_source(void)
{
/* Return the clock source which is used as system clock. */
return ((RCC_CFGR & 0x000c) >> 2);
return (RCC_CFGR & 0x000c) >> 2;
}
void rcc_rtc_select_clock(u32 clock)
@@ -469,7 +472,7 @@ void rcc_clock_setup_msi(const clock_scale_t *clock)
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_PWREN);
pwr_set_vos_scale(clock->voltage_scale);
// I guess this should be in the settings?
/* I guess this should be in the settings? */
flash_64bit_enable();
flash_prefetch_enable();
/* Configure flash settings. */
@@ -500,7 +503,7 @@ void rcc_clock_setup_hsi(const clock_scale_t *clock)
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_PWREN);
pwr_set_vos_scale(clock->voltage_scale);
// I guess this should be in the settings?
/* I guess this should be in the settings? */
flash_64bit_enable();
flash_prefetch_enable();
/* Configure flash settings. */
@@ -528,13 +531,14 @@ void rcc_clock_setup_pll(const clock_scale_t *clock)
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_PWREN);
pwr_set_vos_scale(clock->voltage_scale);
// I guess this should be in the settings?
/* I guess this should be in the settings? */
flash_64bit_enable();
flash_prefetch_enable();
/* Configure flash settings. */
flash_set_ws(clock->flash_config);
rcc_set_pll_configuration(clock->pll_source, clock->pll_mul, clock->pll_div);
rcc_set_pll_configuration(clock->pll_source, clock->pll_mul,
clock->pll_div);
/* Enable PLL oscillator and wait for it to stabilize. */
rcc_osc_on(PLL);

3
lib/stm32/l1/timer.c
View File

@@ -41,7 +41,8 @@
Set timer options register on TIM2 or TIM3, used for trigger remapping.
@param[in] timer_peripheral Unsigned int32. Timer register address base
@returns Unsigned int32. Option flags TIM2: @ref tim2_opt_trigger_remap, TIM3: @ref tim3_opt_trigger_remap.
@returns Unsigned int32. Option flags TIM2: @ref tim2_opt_trigger_remap, TIM3:
@ref tim3_opt_trigger_remap.
*/
void timer_set_option(u32 timer_peripheral, u32 option)