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First coarse run to fix coding style in locm3.

Browse Source 
Added --terse and --mailback options to the make stylecheck target. It
also does continue even if it enounters a possible error.

We decided on two exceptions from the linux kernel coding standard:
- Empty wait while loops may end with ; on the same line.
- All blocks after while, if, for have to be in brackets even if they
  only contain one statement. Otherwise it is easy to introduce an
  error.

Checkpatch needs to be adapted to reflect those changes.
This commit is contained in:
Piotr Esden-Tempski
2013-06-12 17:44:07 -07:00
parent 48e0f3326b
commit 7df63fcae0
147 changed files with 3323 additions and 2565 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
lib/lpc43xx/i2c.c
View File

@@ -81,8 +81,9 @@ void i2c0_tx_start(void)
/* transmit data byte */
void i2c0_tx_byte(u8 byte)
{
if (I2C0_CONSET & I2C_CONSET_STA)
if (I2C0_CONSET & I2C_CONSET_STA) {
I2C0_CONCLR = I2C_CONCLR_STAC;
}
I2C0_DAT = byte;
I2C0_CONCLR = I2C_CONCLR_SIC;
while (!(I2C0_CONSET & I2C_CONSET_SI));
@@ -91,8 +92,9 @@ void i2c0_tx_byte(u8 byte)
/* receive data byte */
u8 i2c0_rx_byte(void)
{
if (I2C0_CONSET & I2C_CONSET_STA)
if (I2C0_CONSET & I2C_CONSET_STA) {
I2C0_CONCLR = I2C_CONCLR_STAC;
}
I2C0_CONCLR = I2C_CONCLR_SIC;
while (!(I2C0_CONSET & I2C_CONSET_SI));
return I2C0_DAT;
@@ -101,8 +103,9 @@ u8 i2c0_rx_byte(void)
/* transmit stop bit */
void i2c0_stop(void)
{
if (I2C0_CONSET & I2C_CONSET_STA)
if (I2C0_CONSET & I2C_CONSET_STA) {
I2C0_CONCLR = I2C_CONCLR_STAC;
}
I2C0_CONSET = I2C_CONSET_STO;
I2C0_CONCLR = I2C_CONCLR_SIC;
}

8
lib/lpc43xx/scu.c
View File

@@ -34,13 +34,17 @@ LGPL License Terms @ref lgpl_license
#include <libopencm3/lpc43xx/scu.h>
/* For pin_conf_normal value see scu.h define SCU_CONF_XXX or Configuration for different I/O pins types */
/* For pin_conf_normal value see scu.h define SCU_CONF_XXX or Configuration for
* different I/O pins types
*/
void scu_pinmux(scu_grp_pin_t group_pin, u32 scu_conf)
{
MMIO32(group_pin) = scu_conf;
}
/* For other special SCU register USB1, I2C0, ADC0/1, DAC, EMC clock delay See scu.h */
/* For other special SCU register USB1, I2C0, ADC0/1, DAC, EMC clock delay See
* scu.h
*/
/* For Pin interrupt select register see scu.h SCU_PINTSEL0 & SCU_PINTSEL1 */

47
lib/lpc43xx/ssp.c
View File

@@ -61,11 +61,9 @@ void ssp_disable(ssp_num_t ssp_num)
{
u32 ssp_port;
if(ssp_num == SSP0_NUM)
{
if (ssp_num == SSP0_NUM) {
ssp_port = SSP0;
}else
{
} else {
ssp_port = SSP1;
}
/* Disable SSP */
@@ -88,16 +86,15 @@ void ssp_init(ssp_num_t ssp_num,
u32 ssp_port;
u32 clock;
if(ssp_num == SSP0_NUM)
{
if (ssp_num == SSP0_NUM) {
ssp_port = SSP0;
}else
{
} else {
ssp_port = SSP1;
}
/* use PLL1 as clock source for SSP1 */
CGU_BASE_SSP1_CLK = (CGU_SRC_PLL1<<CGU_BASE_CLK_SEL_SHIFT) | (1<<CGU_AUTOBLOCK_CLOCK_BIT);
CGU_BASE_SSP1_CLK = (CGU_SRC_PLL1<<CGU_BASE_CLK_SEL_SHIFT) |
(1<<CGU_AUTOBLOCK_CLOCK_BIT);
/* Disable SSP before to configure it */
SSP_CR1(ssp_port) = 0x0;
@@ -105,7 +102,8 @@ void ssp_init(ssp_num_t ssp_num,
/* Configure SSP */
clock = serial_clock_rate;
SSP_CPSR(ssp_port) = clk_prescale;
SSP_CR0(ssp_port) = (data_size | frame_format | cpol_cpha_format | (clock<<8) );
SSP_CR0(ssp_port) =
(data_size | frame_format | cpol_cpha_format | (clock<<8));
/* Enable SSP */
SSP_CR1(ssp_port) = (SSP_ENABLE | mode | master_slave | slave_option);
@@ -118,15 +116,14 @@ u16 ssp_read(ssp_num_t ssp_num)
{
u32 ssp_port;
if(ssp_num == SSP0_NUM)
{
if (ssp_num == SSP0_NUM) {
ssp_port = SSP0;
}else
{
} else {
ssp_port = SSP1;
}
/* Wait Until Data Received (Rx FIFO not Empty) */
while( (SSP_SR(ssp_port) & SSP_SR_RNE) == 0);
while ((SSP_SR(ssp_port) & SSP_SR_RNE) == 0);
return SSP_DR(ssp_port);
}
@@ -134,16 +131,14 @@ u16 ssp_read(ssp_num_t ssp_num)
void ssp_wait_until_not_busy(ssp_num_t ssp_num)
{
u32 ssp_port;
if(ssp_num == SSP0_NUM)
{
if (ssp_num == SSP0_NUM) {
ssp_port = SSP0;
}else
{
} else {
ssp_port = SSP1;
}
while( (SSP_SR(ssp_port) & SSP_SR_BSY) );
while ((SSP_SR(ssp_port) & SSP_SR_BSY));
}
/* This Function Wait Data TX Ready, and Write Data to SSP */
@@ -151,19 +146,17 @@ void ssp_write(ssp_num_t ssp_num, u16 data)
{
u32 ssp_port;
if(ssp_num == SSP0_NUM)
{
if (ssp_num == SSP0_NUM) {
ssp_port = SSP0;
}else
{
} else {
ssp_port = SSP1;
}
/* Wait Until FIFO not full */
while( (SSP_SR(ssp_port) & SSP_SR_TNF) == 0);
while ((SSP_SR(ssp_port) & SSP_SR_TNF) == 0);
SSP_DR(ssp_port) = data;
/* Wait for not busy, since we're controlling CS# of
* devices manually and need to wait for the data to
* be sent. It may also be important to wait here

12
lib/lpc43xx/vector_chipset.c
View File

@@ -22,21 +22,21 @@
extern unsigned _etext_ram, _text_ram, _etext_rom;
#define CREG_M4MEMMAP MMIO32( (0x40043000 + 0x100) )
#define CREG_M4MEMMAP MMIO32((0x40043000 + 0x100))
static void pre_main(void)
{
volatile unsigned *src, *dest;
/* Copy the code from ROM to Real RAM (if enabled) */
if( (&_etext_ram-&_text_ram) > 0 )
{
if ((&_etext_ram-&_text_ram) > 0) {
src = &_etext_rom-(&_etext_ram-&_text_ram);
/* Change Shadow memory to ROM (for Debug Purpose in case Boot has not set correctly the M4MEMMAP because of debug) */
/* Change Shadow memory to ROM (for Debug Purpose in case Boot
* has not set correctly the M4MEMMAP because of debug)
*/
CREG_M4MEMMAP = (unsigned long)src;
for(dest = &_text_ram; dest < &_etext_ram; )
{
for (dest = &_text_ram; dest < &_etext_ram; ) {
*dest++ = *src++;
}