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First coarse run to fix coding style in locm3.

Browse Source 
Added --terse and --mailback options to the make stylecheck target. It
also does continue even if it enounters a possible error.

We decided on two exceptions from the linux kernel coding standard:
- Empty wait while loops may end with ; on the same line.
- All blocks after while, if, for have to be in brackets even if they
  only contain one statement. Otherwise it is easy to introduce an
  error.

Checkpatch needs to be adapted to reflect those changes.
This commit is contained in:
Piotr Esden-Tempski
2013-06-12 17:44:07 -07:00
parent 48e0f3326b
commit 7df63fcae0
147 changed files with 3323 additions and 2565 deletions
Download Patch File Download Diff File Expand all files Collapse all files

23
lib/lm4f/gpio.c
View File

@@ -25,8 +25,10 @@
*
* @version 1.0.0
*
* @author @htmlonly &copy; @endhtmlonly 2011 Gareth McMullin <gareth@blacksphere.co.nz>
* @author @htmlonly &copy; @endhtmlonly 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com>
* @author @htmlonly &copy; @endhtmlonly 2011
* Gareth McMullin <gareth@blacksphere.co.nz>
* @author @htmlonly &copy; @endhtmlonly 2013
* Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* @date 16 March 2013
*
@@ -268,17 +270,17 @@ void gpio_mode_setup(u32 gpioport, enum gpio_mode mode, enum gpio_pullup pullup,
void gpio_set_output_config(u32 gpioport, enum gpio_output_type otype,
enum gpio_drive_strength drive, u8 gpios)
{
if (otype == GPIO_OTYPE_OD)
if (otype == GPIO_OTYPE_OD) {
GPIO_ODR(gpioport) |= gpios;
else
} else {
GPIO_ODR(gpioport) &= ~gpios;
}
/*
* Setting a bit in the GPIO_DRxR register clears the corresponding bit
* in the other GPIO_DRyR registers, and vice-versa.
*/
switch (drive)
{
switch (drive) {
case GPIO_DRIVE_8MA_SLEW_CTL:
GPIO_DR8R(gpioport) |= gpios;
GPIO_SLR(gpioport) |= gpios;
@@ -312,7 +314,7 @@ void gpio_set_output_config(u32 gpioport, enum gpio_output_type otype,
*
* @param[in] gpioport GPIO block register address base @ref gpio_reg_base
* @param[in] alt_func_num Pin alternate function number or 0 to disable the
* alternate function multiplexing.
* alternate function multiplexing.
* @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified
* by OR'ing then together
*/
@@ -327,7 +329,7 @@ void gpio_set_af(u32 gpioport, u8 alt_func_num, u8 gpios)
GPIO_AFSEL(gpioport) &= ~gpios;
return;
}
/* Enable the alternate function */
GPIO_AFSEL(gpioport) |= gpios;
/* Alternate functions are digital */
@@ -338,11 +340,12 @@ void gpio_set_af(u32 gpioport, u8 alt_func_num, u8 gpios)
for (i = 0; i < 8; i++) {
pin_mask = (1 << i);
if (!(gpios & pin_mask))
if (!(gpios & pin_mask)) {
continue;
}
pctl32 &= ~PCTL_MASK(i);
pctl32 |= PCTL_AF( i, (alt_func_num & 0xf) );
pctl32 |= PCTL_AF(i, (alt_func_num & 0xf));
}
GPIO_PCTL(gpioport) = pctl32;

20
lib/lm4f/rcc.c
View File

@@ -23,7 +23,8 @@
*
* @ingroup LM4Fxx
*
@author @htmlonly &copy; @endhtmlonly 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
@author @htmlonly &copy; @endhtmlonly 2012
Alexandru Gagniuc <mr.nuke.me@gmail.com>
* \brief <b>libopencm3 LM4F Clock control API</b>
*
@@ -93,13 +94,13 @@
* High-level routines update the system clock automatically.
* For read access, it is recommended to acces this variable via
* @code
* rcc_get_system_clock_frequency();
* rcc_get_system_clock_frequency();
* @endcode
*
* If write access is desired (i.e. when changing the system clock via the
* fine-grained mechanisms), then include the following line in your code:
* @code
* extern u32 lm4f_rcc_sysclk_freq;
* extern u32 lm4f_rcc_sysclk_freq;
* @endcode
*/
u32 lm4f_rcc_sysclk_freq = 16000000;
@@ -266,8 +267,8 @@ void rcc_pll_bypass_enable(void)
* function.
*
* @param[in] div clock divisor to apply to the 400MHz PLL clock. It is the
* caller's responsibility to ensure that the divisor will not create
* a system clock that is out of spec.
* caller's responsibility to ensure that the divisor will not create
* a system clock that is out of spec.
*/
void rcc_set_pll_divisor(u8 div400)
{
@@ -334,7 +335,7 @@ void rcc_usb_pll_on(void)
*/
void rcc_wait_for_pll_ready(void)
{
while(!(SYSCTL_PLLSTAT & SYSCTL_PLLSTAT_LOCK));
while (!(SYSCTL_PLLSTAT & SYSCTL_PLLSTAT_LOCK));
}
/**
@@ -434,8 +435,8 @@ static u32 xtal_to_freq(xtal_t xtal)
* @param [in] osc_src Oscillator from where to derive the system clock.
* @param [in] xtal Type of crystal connected to the OSCO/OSCI pins
* @param [in] pll_div400 The clock divisor to apply to the 400MHz PLL clock.
* If 0, then the PLL is disabled, and the system runs
* off a "raw" clock.
* If 0, then the PLL is disabled, and the system runs
* off a "raw" clock.
*
* @return System clock frequency in Hz
*/
@@ -448,8 +449,9 @@ void rcc_sysclk_config(osc_src_t osc_src, xtal_t xtal, u8 pll_div400)
rcc_pll_bypass_enable();
/* Enable the main oscillator, if needed */
if (osc_src == OSCSRC_MOSC)
if (osc_src == OSCSRC_MOSC) {
rcc_enable_main_osc();
}
/* Make RCC2 override RCC */
rcc_enable_rcc2();

32
lib/lm4f/uart.c
View File

@@ -116,10 +116,11 @@ void uart_set_baudrate(u32 uart, u32 baud)
u32 clock;
/* Are we running off the internal clock or system clock? */
if (UART_CC(uart) == UART_CC_CS_PIOSC)
if (UART_CC(uart) == UART_CC_CS_PIOSC) {
clock = 16000000;
else
} else {
clock = rcc_get_system_clock_frequency();
}
/* Find the baudrate divisor */
u32 div = (((clock * 8) / baud) + 1) / 2;
@@ -143,7 +144,7 @@ void uart_set_databits(u32 uart, u8 databits)
bits32 = (databits - 5) << 5;
/* TODO: What about 9 data bits? */
reg32 = UART_LCRH(uart);
reg32 &= ~UART_LCRH_WLEN_MASK;
reg32 |= bits32;
@@ -158,10 +159,11 @@ void uart_set_databits(u32 uart, u8 databits)
*/
void uart_set_stopbits(u32 uart, u8 stopbits)
{
if (stopbits == 2)
if (stopbits == 2) {
UART_LCRH(uart) |= UART_LCRH_STP2;
else
} else {
UART_LCRH(uart) &= ~UART_LCRH_STP2;
}
}
/**
@@ -178,8 +180,7 @@ void uart_set_parity(u32 uart, enum uart_parity parity)
reg32 |= UART_LCRH_PEN;
reg32 &= ~(UART_LCRH_SPS | UART_LCRH_EPS);
switch (parity)
{
switch (parity) {
case UART_PARITY_NONE:
/* Once we disable parity the other bits are meaningless */
UART_LCRH(uart) &= ~UART_LCRH_PEN;
@@ -218,12 +219,13 @@ void uart_set_flow_control(u32 uart, enum uart_flowctl flow)
reg32 &= ~(UART_CTL_RTSEN | UART_CTL_CTSEN);
if (flow == UART_FLOWCTL_RTS)
reg32 |= UART_CTL_RTSEN;
else if (flow == UART_FLOWCTL_CTS)
if (flow == UART_FLOWCTL_RTS) {
reg32 |= UART_CTL_RTSEN;
} else if (flow == UART_FLOWCTL_CTS) {
reg32 |= UART_CTL_CTSEN;
else if (flow == UART_FLOWCTL_RTS_CTS)
} else if (flow == UART_FLOWCTL_RTS_CTS) {
reg32 |= (UART_CTL_RTSEN | UART_CTL_CTSEN);
}
UART_CTL(uart) = reg32;
}
@@ -301,7 +303,7 @@ u16 uart_recv(u32 uart)
void uart_wait_send_ready(u32 uart)
{
/* Wait until the Tx FIFO is no longer full */
while(UART_FR(uart) & UART_FR_TXFF);
while (UART_FR(uart) & UART_FR_TXFF);
}
/**
@@ -314,7 +316,7 @@ void uart_wait_send_ready(u32 uart)
void uart_wait_recv_ready(u32 uart)
{
/* Wait until the Tx FIFO is no longer empty */
while(UART_FR(uart) & UART_FR_RXFE);
while (UART_FR(uart) & UART_FR_RXFE);
}
/**
@@ -438,8 +440,8 @@ void uart_enable_interrupts(u32 uart, enum uart_interrupt_flag ints)
* interrupts, pass (UART_INT_RX | UART_INT_CTS)
*
* @param[in] uart UART block register address base @ref uart_reg_base
* @param[in] ints Interrupts which to disable. Any combination of interrupts may
* be specified by OR'ing then together
* @param[in] ints Interrupts which to disable. Any combination of interrupts
* may be specified by OR'ing then together
*/
void uart_disable_interrupts(u32 uart, enum uart_interrupt_flag ints)
{

121
lib/lm4f/usb_lm4f.c
View File

@@ -232,8 +232,9 @@ static void lm4f_ep_setup(usbd_device *usbd_dev, u8 addr, u8 type, u16 max_size,
if (addr == 0) {
USB_EPIDX = 0;
if (reg8 > USB_FIFOSZ_SIZE_64)
if (reg8 > USB_FIFOSZ_SIZE_64) {
reg8 = USB_FIFOSZ_SIZE_64;
}
/* The RX and TX FIFOs are shared for EP0 */
USB_RXFIFOSZ = reg8;
@@ -248,8 +249,9 @@ static void lm4f_ep_setup(usbd_device *usbd_dev, u8 addr, u8 type, u16 max_size,
}
/* Are we out of FIFO space? */
if (usbd_dev->fifo_mem_top + fifo_size > MAX_FIFO_RAM)
if (usbd_dev->fifo_mem_top + fifo_size > MAX_FIFO_RAM) {
return;
}
USB_EPIDX = addr & USB_EPIDX_MASK;
@@ -262,12 +264,12 @@ static void lm4f_ep_setup(usbd_device *usbd_dev, u8 addr, u8 type, u16 max_size,
usbd_dev->user_callback_ctr[ep][USB_TRANSACTION_IN] =
(void *)callback;
}
if (type == USB_ENDPOINT_ATTR_ISOCHRONOUS)
if (type == USB_ENDPOINT_ATTR_ISOCHRONOUS) {
USB_TXCSRH(ep) |= USB_TXCSRH_ISO;
else
} else {
USB_TXCSRH(ep) &= ~USB_TXCSRH_ISO;
}
else {
}
} else {
USB_RXMAXP(ep) = max_size;
USB_RXFIFOSZ = reg8;
USB_RXFIFOADD = ((usbd_dev->fifo_mem_top) >> 3);
@@ -275,10 +277,11 @@ static void lm4f_ep_setup(usbd_device *usbd_dev, u8 addr, u8 type, u16 max_size,
usbd_dev->user_callback_ctr[ep][USB_TRANSACTION_OUT] =
(void *)callback;
}
if (type == USB_ENDPOINT_ATTR_ISOCHRONOUS)
if (type == USB_ENDPOINT_ATTR_ISOCHRONOUS) {
USB_RXCSRH(ep) |= USB_RXCSRH_ISO;
else
} else {
USB_RXCSRH(ep) &= ~USB_RXCSRH_ISO;
}
}
usbd_dev->fifo_mem_top += fifo_size;
@@ -301,24 +304,27 @@ static void lm4f_ep_stall_set(usbd_device *usbd_dev, u8 addr, u8 stall)
const bool dir_tx = addr & 0x80;
if (ep == 0) {
if (stall)
if (stall) {
USB_CSRL0 |= USB_CSRL0_STALL;
else
} else {
USB_CSRL0 &= ~USB_CSRL0_STALL;
}
return;
}
if (dir_tx) {
if (stall)
if (stall) {
(USB_TXCSRL(ep)) |= USB_TXCSRL_STALL;
else
} else {
(USB_TXCSRL(ep)) &= ~USB_TXCSRL_STALL;
}
}
else {
if (stall)
if (stall) {
(USB_RXCSRL(ep)) |= USB_RXCSRL_STALL;
else
} else {
(USB_RXCSRL(ep)) &= ~USB_RXCSRL_STALL;
}
}
}
@@ -330,13 +336,14 @@ static u8 lm4f_ep_stall_get(usbd_device *usbd_dev, u8 addr)
const bool dir_tx = addr & 0x80;
if (ep == 0) {
return (USB_CSRL0 & USB_CSRL0_STALLED);
return USB_CSRL0 & USB_CSRL0_STALLED;
}
if (dir_tx)
return (USB_TXCSRL(ep) & USB_TXCSRL_STALLED);
else
return (USB_RXCSRL(ep) & USB_RXCSRL_STALLED);
if (dir_tx) {
return USB_TXCSRL(ep) & USB_TXCSRL_STALLED;
} else {
return USB_RXCSRL(ep) & USB_RXCSRL_STALLED;
}
}
static void lm4f_ep_nak_set(usbd_device *usbd_dev, u8 addr, u8 nak)
@@ -368,14 +375,16 @@ static u16 lm4f_ep_write_packet(usbd_device *usbd_dev, u8 addr,
* the reads are downgraded to 8-bit in hardware. We lose a bit of
* performance, but we don't crash.
*/
for (i = 0; i < (len & ~0x3); i += 4)
for (i = 0; i < (len & ~0x3); i += 4) {
USB_FIFO32(ep) = *((u32 *)(buf + i));
}
if (len & 0x2) {
USB_FIFO16(ep) = *((u16 *)(buf + i));
i += 2;
}
if (len & 0x1)
if (len & 0x1) {
USB_FIFO8(ep) = *((u8 *)(buf + i));
}
if (ep == 0) {
/*
@@ -384,11 +393,11 @@ static u16 lm4f_ep_write_packet(usbd_device *usbd_dev, u8 addr,
* that is a multiple of 64 bytes will end with a zero-length
* packet, so our check is sane.
*/
if (len != 64)
if (len != 64) {
USB_CSRL0 |= USB_CSRL0_TXRDY | USB_CSRL0_DATAEND;
else
} else {
USB_CSRL0 |= USB_CSRL0_TXRDY;
}
} else {
USB_TXCSRL(ep) |= USB_TXCSRL_TXRDY;
}
@@ -396,7 +405,8 @@ static u16 lm4f_ep_write_packet(usbd_device *usbd_dev, u8 addr,
return i;
}
static u16 lm4f_ep_read_packet(usbd_device *usbd_dev, u8 addr, void *buf, u16 len)
static u16 lm4f_ep_read_packet(usbd_device *usbd_dev, u8 addr, void *buf,
u16 len)
{
(void)usbd_dev;
@@ -412,14 +422,16 @@ static u16 lm4f_ep_read_packet(usbd_device *usbd_dev, u8 addr, void *buf, u16 le
* the writes are downgraded to 8-bit in hardware. We lose a bit of
* performance, but we don't crash.
*/
for (len = 0; len < (rlen & ~0x3); len += 4)
for (len = 0; len < (rlen & ~0x3); len += 4) {
*((u32 *)(buf + len)) = USB_FIFO32(ep);
}
if (rlen & 0x2) {
*((u16 *)(buf + len)) = USB_FIFO16(ep);
len += 2;
}
if (rlen & 0x1)
if (rlen & 0x1) {
*((u8 *)(buf + len)) = USB_FIFO8(ep);
}
if (ep == 0) {
/*
@@ -456,17 +468,21 @@ static void lm4f_poll(usbd_device *usbd_dev)
const u8 usb_txis = USB_TXIS;
const u8 usb_csrl0 = USB_CSRL0;
if ((usb_is & USB_IM_SUSPEND) && (usbd_dev->user_callback_suspend))
if ((usb_is & USB_IM_SUSPEND) && (usbd_dev->user_callback_suspend)) {
usbd_dev->user_callback_suspend();
if ((usb_is & USB_IM_RESUME) && (usbd_dev->user_callback_resume))
usbd_dev->user_callback_resume();
}
if (usb_is & USB_IM_RESET)
if ((usb_is & USB_IM_RESUME) && (usbd_dev->user_callback_resume)) {
usbd_dev->user_callback_resume();
}
if (usb_is & USB_IM_RESET) {
_usbd_reset(usbd_dev);
if ((usb_is & USB_IM_SOF) && (usbd_dev->user_callback_sof))
}
if ((usb_is & USB_IM_SOF) && (usbd_dev->user_callback_sof)) {
usbd_dev->user_callback_sof();
}
if (usb_txis & USB_EP0) {
/*
@@ -483,14 +499,17 @@ static void lm4f_poll(usbd_device *usbd_dev)
type = (usbd_dev->control_state.state != DATA_OUT &&
usbd_dev->control_state.state != LAST_DATA_OUT)
? USB_TRANSACTION_SETUP :
USB_TRANSACTION_OUT ;
USB_TRANSACTION_OUT;
if (usbd_dev->user_callback_ctr[0][type])
usbd_dev->user_callback_ctr[0][type] (usbd_dev, 0);
if (usbd_dev->user_callback_ctr[0][type]) {
usbd_dev->
user_callback_ctr[0][type](usbd_dev, 0);
}
} else {
tx_cb = usbd_dev->user_callback_ctr[0][USB_TRANSACTION_IN];
tx_cb = usbd_dev->user_callback_ctr[0]
[USB_TRANSACTION_IN];
/*
* EP0 bit in TXIS is set not only when a packet is
@@ -508,11 +527,13 @@ static void lm4f_poll(usbd_device *usbd_dev)
*/
if ((usbd_dev->control_state.state != DATA_IN) &&
(usbd_dev->control_state.state != LAST_DATA_IN) &&
(usbd_dev->control_state.state != STATUS_IN))
(usbd_dev->control_state.state != STATUS_IN)) {
return;
}
if (tx_cb)
tx_cb (usbd_dev, 0);
if (tx_cb) {
tx_cb(usbd_dev, 0);
}
}
}
@@ -521,11 +542,13 @@ static void lm4f_poll(usbd_device *usbd_dev)
tx_cb = usbd_dev->user_callback_ctr[i][USB_TRANSACTION_IN];
rx_cb = usbd_dev->user_callback_ctr[i][USB_TRANSACTION_OUT];
if ( (usb_txis & (1 << i)) && tx_cb)
if ((usb_txis & (1 << i)) && tx_cb) {
tx_cb(usbd_dev, i);
}
if ( (usb_rxis & (1 << i)) && rx_cb)
if ((usb_rxis & (1 << i)) && rx_cb) {
rx_cb(usbd_dev, i);
}
}
@@ -540,10 +563,11 @@ static void lm4f_disconnect(usbd_device *usbd_dev, bool disconnected)
* usbd_disconnect(dev, 1) followed by usbd_disconnect(dev, 0)
* causes the device to re-enumerate and re-configure properly.
*/
if (disconnected)
if (disconnected) {
lm4f_usb_soft_disconnect();
else
} else {
lm4f_usb_soft_connect();
}
}
/*
@@ -568,8 +592,9 @@ static usbd_device *lm4f_usbd_init(void)
/* Software reset USB */
SYSCTL_SRUSB = 1;
for (i = 0; i < 1000; i++)
for (i = 0; i < 1000; i++) {
__asm__("nop");
}
SYSCTL_SRUSB = 0;
/*
@@ -579,8 +604,8 @@ static usbd_device *lm4f_usbd_init(void)
*/
/* Wait for it */
i = 0;
while ( (SYSCTL_RIS & SYSCTL_RIS_USBPLLLRIS) == 0) {
i ++;
while ((SYSCTL_RIS & SYSCTL_RIS_USBPLLLRIS) == 0) {
i++;
if (i > 0xffff) {
return 0;
}