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First coarse run to fix coding style in locm3.

Browse Source 
Added --terse and --mailback options to the make stylecheck target. It
also does continue even if it enounters a possible error.

We decided on two exceptions from the linux kernel coding standard:
- Empty wait while loops may end with ; on the same line.
- All blocks after while, if, for have to be in brackets even if they
  only contain one statement. Otherwise it is easy to introduce an
  error.

Checkpatch needs to be adapted to reflect those changes.
This commit is contained in:
Piotr Esden-Tempski
2013-06-12 17:44:07 -07:00
parent 48e0f3326b
commit 7df63fcae0
147 changed files with 3323 additions and 2565 deletions
Download Patch File Download Diff File Expand all files Collapse all files

39
lib/cm3/nvic.c
View File

@@ -45,7 +45,7 @@ LGPL License Terms @ref lgpl_license
#include <libopencm3/cm3/nvic.h>
#include <libopencm3/cm3/scs.h>
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief NVIC Enable Interrupt
Enables a user interrupt.
@@ -58,7 +58,7 @@ void nvic_enable_irq(u8 irqn)
NVIC_ISER(irqn / 32) = (1 << (irqn % 32));
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief NVIC Disable Interrupt
Disables a user interrupt.
@@ -71,7 +71,7 @@ void nvic_disable_irq(u8 irqn)
NVIC_ICER(irqn / 32) = (1 << (irqn % 32));
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief NVIC Return Pending Interrupt
True if the interrupt has occurred and is waiting for service.
@@ -85,7 +85,7 @@ u8 nvic_get_pending_irq(u8 irqn)
return NVIC_ISPR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief NVIC Set Pending Interrupt
Force a user interrupt to a pending state. This has no effect if the interrupt
@@ -99,7 +99,7 @@ void nvic_set_pending_irq(u8 irqn)
NVIC_ISPR(irqn / 32) = (1 << (irqn % 32));
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief NVIC Clear Pending Interrupt
Force remove a user interrupt from a pending state. This has no effect if the
@@ -113,7 +113,7 @@ void nvic_clear_pending_irq(u8 irqn)
NVIC_ICPR(irqn / 32) = (1 << (irqn % 32));
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief NVIC Return Active Interrupt
Interrupt has occurred and is currently being serviced.
@@ -127,7 +127,7 @@ u8 nvic_get_active_irq(u8 irqn)
return NVIC_IABR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief NVIC Return Enabled Interrupt
@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint
@@ -139,13 +139,14 @@ u8 nvic_get_irq_enabled(u8 irqn)
return NVIC_ISER(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief NVIC Set Interrupt Priority
There are 16 priority levels only, given by the upper four bits of the priority
byte, as required by ARM standards. The priority levels are interpreted according
to the pre-emptive priority grouping set in the SCB Application Interrupt and Reset
Control Register (SCB_AIRCR), as done in @ref scb_set_priority_grouping.
byte, as required by ARM standards. The priority levels are interpreted
according to the pre-emptive priority grouping set in the SCB Application
Interrupt and Reset Control Register (SCB_AIRCR), as done in @ref
scb_set_priority_grouping.
@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint
@param[in] priority Unsigned int8. Interrupt priority (0 ... 255 in steps of 16)
@@ -156,29 +157,29 @@ void nvic_set_priority(u8 irqn, u8 priority)
/* code from lpc43xx/nvic.c -- this is quite a hack and alludes to the
* negative interrupt numbers assigned to the system interrupts. better
* handling would mean signed integers. */
if(irqn>=NVIC_IRQ_COUNT)
{
if (irqn >= NVIC_IRQ_COUNT) {
/* Cortex-M system interrupts */
SCS_SHPR( (irqn&0xF)-4 ) = priority;
}else
{
SCS_SHPR((irqn & 0xF) - 4) = priority;
} else {
/* Device specific interrupts */
NVIC_IPR(irqn) = priority;
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief NVIC Software Trigger Interrupt
Generate an interrupt from software. This has no effect for unprivileged access
unless the privilege level has been elevated through the System Control Registers.
unless the privilege level has been elevated through the System Control
Registers.
@param[in] irqn Unsigned int16. Interrupt number (0 ... 239)
*/
void nvic_generate_software_interrupt(u16 irqn)
{
if (irqn <= 239)
if (irqn <= 239) {
NVIC_STIR |= irqn;
}
}
/**@}*/