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First coarse run to fix coding style in locm3.

Browse Source 
Added --terse and --mailback options to the make stylecheck target. It
also does continue even if it enounters a possible error.

We decided on two exceptions from the linux kernel coding standard:
- Empty wait while loops may end with ; on the same line.
- All blocks after while, if, for have to be in brackets even if they
  only contain one statement. Otherwise it is easy to introduce an
  error.

Checkpatch needs to be adapted to reflect those changes.
This commit is contained in:
Piotr Esden-Tempski
2013-06-12 17:44:07 -07:00
parent 48e0f3326b
commit 7df63fcae0
147 changed files with 3323 additions and 2565 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
include/libopencm3/stm32/can.h
View File

@@ -159,8 +159,10 @@ LGPL License Terms @ref lgpl_license
* Connectivity line devices have 28 banks so the bank ID spans 0..27
* all other devices have 14 banks so the bank ID spans 0..13.
*/
#define CAN_FiR1(can_base, bank) MMIO32(can_base + 0x240 + (bank * 0x8) + 0x0)
#define CAN_FiR2(can_base, bank) MMIO32(can_base + 0x240 + (bank * 0x8) + 0x4)
#define CAN_FiR1(can_base, bank) MMIO32(can_base + 0x240 + \
(bank * 0x8) + 0x0)
#define CAN_FiR2(can_base, bank) MMIO32(can_base + 0x240 + \
(bank * 0x8) + 0x4)
/* --- CAN_MCR values ------------------------------------------------------ */

2
include/libopencm3/stm32/common/crc_common_all.h
View File

@@ -23,7 +23,7 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA CRC.H
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA CRC.H
The order of header inclusion is important. crc.h includes the device
specific memorymap.h header before including this header file.*/

5
include/libopencm3/stm32/common/dac_common_all.h
View File

@@ -1,6 +1,7 @@
/** @addtogroup dac_defines
@author @htmlonly &copy; @endhtmlonly 2012 Felix Held <felix-libopencm3@felixheld.de>
@author @htmlonly &copy; @endhtmlonly 2012
Felix Held <felix-libopencm3@felixheld.de>
*/
@@ -25,7 +26,7 @@
/**@{*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DAC.H
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DAC.H
The order of header inclusion is important. dac.h includes the device
specific memorymap.h header before including this header file.*/

79
include/libopencm3/stm32/common/dma_common_f13.h
View File

@@ -1,7 +1,9 @@
/** @addtogroup dma_defines
/** @addtogroup dma_defines
@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
@author @htmlonly &copy; @endhtmlonly 2012 Piotr Esden-Tempski <piotr@esden.net>
@author @htmlonly &copy; @endhtmlonly 2010
Thomas Otto <tommi@viadmin.org>
@author @htmlonly &copy; @endhtmlonly 2012
Piotr Esden-Tempski <piotr@esden.net>
*/
@@ -27,7 +29,7 @@
/**@{*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DMA.H
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DMA.H
The order of header inclusion is important. dma.h includes the device
specific memorymap.h header before including this header file.*/
@@ -141,29 +143,36 @@ specific memorymap.h header before including this header file.*/
/* --- DMA_ISR values ------------------------------------------------------ */
/* --- DMA Interrupt Flag offset values ------------------------------------- */
/* These are based on every interrupt flag and flag clear being at the same relative location */
/** @defgroup dma_if_offset DMA Interrupt Flag Offsets within channel flag group.
/* These are based on every interrupt flag and flag clear being at the same
* relative location
*/
/** @defgroup dma_if_offset DMA Interrupt Flag Offsets within channel flag
group.
@ingroup dma_defines
@{*/
/** Transfer Error Interrupt Flag */
#define DMA_TEIF (1 << 3)
#define DMA_TEIF (1 << 3)
/** Half Transfer Interrupt Flag */
#define DMA_HTIF (1 << 2)
#define DMA_HTIF (1 << 2)
/** Transfer Complete Interrupt Flag */
#define DMA_TCIF (1 << 1)
#define DMA_TCIF (1 << 1)
/** Global Interrupt Flag */
#define DMA_GIF (1 << 0)
#define DMA_GIF (1 << 0)
/**@}*/
/* Offset within interrupt status register to start of channel interrupt flag field */
#define DMA_FLAG_OFFSET(channel) (4*(channel - 1))
#define DMA_FLAGS (DMA_TEIF | DMA_TCIF | DMA_HTIF | DMA_GIF)
#define DMA_ISR_MASK(channel) DMA_FLAGS << DMA_FLAG_OFFSET(channel)
/* Offset within interrupt status register to start of channel interrupt flag
* field
*/
#define DMA_FLAG_OFFSET(channel) (4*(channel - 1))
#define DMA_FLAGS (DMA_TEIF | DMA_TCIF | DMA_HTIF | \
DMA_GIF)
#define DMA_ISR_MASK(channel) (DMA_FLAGS << DMA_FLAG_OFFSET(channel))
/* TEIF: Transfer error interrupt flag */
#define DMA_ISR_TEIF_BIT DMA_TEIF
#define DMA_ISR_TEIF(channel) (DMA_ISR_TEIF_BIT << (DMA_FLAG_OFFSET(channel)))
#define DMA_ISR_TEIF_BIT DMA_TEIF
#define DMA_ISR_TEIF(channel) (DMA_ISR_TEIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_ISR_TEIF1 DMA_ISR_TEIF(DMA_CHANNEL1)
#define DMA_ISR_TEIF2 DMA_ISR_TEIF(DMA_CHANNEL2)
@@ -174,8 +183,9 @@ specific memorymap.h header before including this header file.*/
#define DMA_ISR_TEIF7 DMA_ISR_TEIF(DMA_CHANNEL7)
/* HTIF: Half transfer interrupt flag */
#define DMA_ISR_HTIF_BIT DMA_HTIF
#define DMA_ISR_HTIF(channel) (DMA_ISR_HTIF_BIT << (DMA_FLAG_OFFSET(channel)))
#define DMA_ISR_HTIF_BIT DMA_HTIF
#define DMA_ISR_HTIF(channel) (DMA_ISR_HTIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_ISR_HTIF1 DMA_ISR_HTIF(DMA_CHANNEL1)
#define DMA_ISR_HTIF2 DMA_ISR_HTIF(DMA_CHANNEL2)
@@ -186,8 +196,9 @@ specific memorymap.h header before including this header file.*/
#define DMA_ISR_HTIF7 DMA_ISR_HTIF(DMA_CHANNEL7)
/* TCIF: Transfer complete interrupt flag */
#define DMA_ISR_TCIF_BIT DMA_TCIF
#define DMA_ISR_TCIF(channel) (DMA_ISR_TCIF_BIT << (DMA_FLAG_OFFSET(channel)))
#define DMA_ISR_TCIF_BIT DMA_TCIF
#define DMA_ISR_TCIF(channel) (DMA_ISR_TCIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_ISR_TCIF1 DMA_ISR_TCIF(DMA_CHANNEL1)
#define DMA_ISR_TCIF2 DMA_ISR_TCIF(DMA_CHANNEL2)
@@ -199,7 +210,8 @@ specific memorymap.h header before including this header file.*/
/* GIF: Global interrupt flag */
#define DMA_ISR_GIF_BIT DMA_GIF
#define DMA_ISR_GIF(channel) (DMA_ISR_GIF_BIT << (DMA_FLAG_OFFSET(channel)))
#define DMA_ISR_GIF(channel) (DMA_ISR_GIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_ISR_GIF1 DMA_ISR_GIF(DMA_CHANNEL1)
#define DMA_ISR_GIF2 DMA_ISR_GIF(DMA_CHANNEL2)
@@ -212,8 +224,9 @@ specific memorymap.h header before including this header file.*/
/* --- DMA_IFCR values ----------------------------------------------------- */
/* CTEIF: Transfer error clear */
#define DMA_IFCR_CTEIF_BIT DMA_TEIF
#define DMA_IFCR_CTEIF(channel) (DMA_IFCR_CTEIF_BIT << (DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CTEIF_BIT DMA_TEIF
#define DMA_IFCR_CTEIF(channel) (DMA_IFCR_CTEIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF(DMA_CHANNEL1)
#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF(DMA_CHANNEL2)
@@ -224,8 +237,9 @@ specific memorymap.h header before including this header file.*/
#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF(DMA_CHANNEL7)
/* CHTIF: Half transfer clear */
#define DMA_IFCR_CHTIF_BIT DMA_HTIF
#define DMA_IFCR_CHTIF(channel) (DMA_IFCR_CHTIF_BIT << (DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CHTIF_BIT DMA_HTIF
#define DMA_IFCR_CHTIF(channel) (DMA_IFCR_CHTIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF(DMA_CHANNEL1)
#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF(DMA_CHANNEL2)
@@ -236,8 +250,9 @@ specific memorymap.h header before including this header file.*/
#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF(DMA_CHANNEL7)
/* CTCIF: Transfer complete clear */
#define DMA_IFCR_CTCIF_BIT DMA_TCIF
#define DMA_IFCR_CTCIF(channel) (DMA_IFCR_CTCIF_BIT << (DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CTCIF_BIT DMA_TCIF
#define DMA_IFCR_CTCIF(channel) (DMA_IFCR_CTCIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF(DMA_CHANNEL1)
#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF(DMA_CHANNEL2)
@@ -248,8 +263,9 @@ specific memorymap.h header before including this header file.*/
#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF(DMA_CHANNEL7)
/* CGIF: Global interrupt clear */
#define DMA_IFCR_CGIF_BIT DMA_GIF
#define DMA_IFCR_CGIF(channel) (DMA_IFCR_CGIF_BIT << (DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CGIF_BIT DMA_GIF
#define DMA_IFCR_CGIF(channel) (DMA_IFCR_CGIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF(DMA_CHANNEL1)
#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF(DMA_CHANNEL2)
@@ -260,8 +276,9 @@ specific memorymap.h header before including this header file.*/
#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF(DMA_CHANNEL7)
/* Clear interrupts mask */
#define DMA_IFCR_CIF_BIT 0xF
#define DMA_IFCR_CIF(channel) (DMA_IFCR_CIF_BIT << (DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CIF_BIT 0xF
#define DMA_IFCR_CIF(channel) (DMA_IFCR_CIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CIF1 DMA_IFCR_CIF(DMA_CHANNEL1)
#define DMA_IFCR_CIF2 DMA_IFCR_CIF(DMA_CHANNEL2)

42
include/libopencm3/stm32/common/dma_common_f24.h
View File

@@ -1,7 +1,9 @@
/** @addtogroup dma_defines
@author @htmlonly &copy; @endhtmlonly 2011 Fergus Noble <fergusnoble@gmail.com>
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
@author @htmlonly &copy; @endhtmlonly 2011
Fergus Noble <fergusnoble@gmail.com>
@author @htmlonly &copy; @endhtmlonly 2012
Ken Sarkies <ksarkies@internode.on.net>
*/
/*
@@ -24,7 +26,7 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DMA.H
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DMA.H
The order of header inclusion is important. dma.h includes the device
specific memorymap.h header before including this header file.*/
@@ -152,7 +154,8 @@ specific memorymap.h header before including this header file.*/
#define DMA2_S7NDTR DMA2_SNDTR(7)
/* DMA Stream x peripheral address register (DMA_SxPAR) */
#define DMA_SPAR(port, n) *(volatile void **)(DMA_STREAM(port, n) + 0x08)
#define DMA_SPAR(port, n) (*(volatile void **)\
(DMA_STREAM(port, n) + 0x08))
#define DMA1_SPAR(n) DMA_SPAR(DMA1, n)
#define DMA2_SPAR(n) DMA_SPAR(DMA2, n)
@@ -175,7 +178,8 @@ specific memorymap.h header before including this header file.*/
#define DMA2_S7PAR DMA2_SPAR(7)
/* DMA Stream x memory address 0 register (DMA_SxM0AR) */
#define DMA_SM0AR(port, n) *(volatile void **)(DMA_STREAM(port, n) + 0x0c)
#define DMA_SM0AR(port, n) (*(volatile void **) \
(DMA_STREAM(port, n) + 0x0c))
#define DMA1_SM0AR(n) DMA_SM0AR(DMA1, n)
#define DMA2_SM0AR(n) DMA_SM0AR(DMA2, n)
@@ -198,7 +202,8 @@ specific memorymap.h header before including this header file.*/
#define DMA2_S7M0AR DMA2_SM0AR(7)
/* DMA Stream x memory address 1 register (DMA_SxM1AR) */
#define DMA_SM1AR(port, n) *(volatile void **)(DMA_STREAM(port, n) + 0x10)
#define DMA_SM1AR(port, n) (*(volatile void **)\
(DMA_STREAM(port, n) + 0x10))
#define DMA1_SM1AR(n) DMA_SM1AR(DMA1, n)
#define DMA2_SM1AR(n) DMA_SM1AR(DMA2, n)
@@ -252,21 +257,24 @@ being at the same relative location */
@{*/
/** Transfer Complete Interrupt Flag */
#define DMA_TCIF (1 << 5)
#define DMA_TCIF (1 << 5)
/** Half Transfer Interrupt Flag */
#define DMA_HTIF (1 << 4)
#define DMA_HTIF (1 << 4)
/** Transfer Error Interrupt Flag */
#define DMA_TEIF (1 << 3)
#define DMA_TEIF (1 << 3)
/** Direct Mode Error Interrupt Flag */
#define DMA_DMEIF (1 << 2)
#define DMA_DMEIF (1 << 2)
/** FIFO Error Interrupt Flag */
#define DMA_FEIF (1 << 0)
#define DMA_FEIF (1 << 0)
/**@}*/
/* Offset within interrupt status register to start of stream interrupt flag field */
#define DMA_ISR_OFFSET(stream) (6*(stream & 0x01)+16*((stream & 0x02) >> 1))
#define DMA_ISR_FLAGS (DMA_TCIF | DMA_HTIF | DMA_TEIF | DMA_DMEIF | DMA_FEIF)
#define DMA_ISR_MASK(stream) DMA_ISR_FLAGS << DMA_ISR_OFFSET(stream)
/* Offset within interrupt status register to start of stream interrupt flag
* field
*/
#define DMA_ISR_OFFSET(stream) (6*(stream & 0x01)+16*((stream & 0x02) >> 1))
#define DMA_ISR_FLAGS (DMA_TCIF | DMA_HTIF | DMA_TEIF | DMA_DMEIF | \
DMA_FEIF)
#define DMA_ISR_MASK(stream) (DMA_ISR_FLAGS << DMA_ISR_OFFSET(stream))
/* --- DMA_LISR values ----------------------------------------------------- */
@@ -560,8 +568,8 @@ being at the same relative location */
BEGIN_DECLS
/*
* Note: The F2 and F4 series have a completely new DMA peripheral with different
* configuration options.
* Note: The F2 and F4 series have a completely new DMA peripheral with
* different configuration options.
*/
void dma_stream_reset(u32 dma, u8 stream);

6
include/libopencm3/stm32/common/flash_common_f24.h
View File

@@ -22,7 +22,7 @@
* For details see:
* PM0081 Programming manual: STM32F40xxx and STM32F41xxx Flash programming
* September 2011, Doc ID 018520 Rev 1
* http://www.st.com/st-web-ui/static/active/en/resource/technical/document/programming_manual/DM00023388.pdf
* http://goo.gl/3ylKe
*/
/** @cond */
@@ -145,7 +145,7 @@ void flash_program_double_word(u32 address, u64 data);
void flash_program_word(u32 address, u32 data);
void flash_program_half_word(u32 address, u16 data);
void flash_program_byte(u32 address, u8 data);
void flash_program(u32 address, u8* data, u32 len);
void flash_program(u32 address, u8 *data, u32 len);
void flash_wait_for_last_operation(void);
void flash_program_option_bytes(u32 data);
@@ -154,7 +154,7 @@ END_DECLS
#endif
/** @cond */
#else
#warning "flash_common_f24.h should not be included explicitly, only via flash.h"
#warning "flash_common_f24.h should not be included direcitly, only via flash.h"
#endif
/** @endcond */

10
include/libopencm3/stm32/common/gpio_common_all.h
View File

@@ -1,7 +1,9 @@
/** @addtogroup gpio_defines
@author @htmlonly &copy; @endhtmlonly 2011 Fergus Noble <fergusnoble@gmail.com>
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
@author @htmlonly &copy; @endhtmlonly 2011
Fergus Noble <fergusnoble@gmail.com>
@author @htmlonly &copy; @endhtmlonly 2012
Ken Sarkies <ksarkies@internode.on.net>
*/
@@ -25,12 +27,12 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA GPIO.H
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA GPIO.H
The order of header inclusion is important. gpio.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#if defined (LIBOPENCM3_GPIO_H) || defined (LIBOPENCM3_GPIO_COMMON_F24_H)
#if defined(LIBOPENCM3_GPIO_H) || defined(LIBOPENCM3_GPIO_COMMON_F24_H)
/** @endcond */
#ifndef LIBOPENCM3_GPIO_COMMON_ALL_H
#define LIBOPENCM3_GPIO_COMMON_ALL_H

16
include/libopencm3/stm32/common/gpio_common_f24.h
View File

@@ -1,7 +1,9 @@
/** @addtogroup gpio_defines
@author @htmlonly &copy; @endhtmlonly 2011 Fergus Noble <fergusnoble@gmail.com>
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
@author @htmlonly &copy; @endhtmlonly 2011
Fergus Noble <fergusnoble@gmail.com>
@author @htmlonly &copy; @endhtmlonly 2012
Ken Sarkies <ksarkies@internode.on.net>
*/
/*
@@ -24,7 +26,7 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA GPIO.H
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA GPIO.H
The order of header inclusion is important. gpio.h includes the device
specific memorymap.h header before including this header file.*/
@@ -278,10 +280,10 @@ specific memorymap.h header before including this header file.*/
BEGIN_DECLS
/*
* Note: The F2 and F4 series have a completely new GPIO peripheral with different
* configuration options. Here we implement a different API partly to more
* closely match the peripheral capabilities and also to deliberately break
* compatibility with old F1 code so there is no confusion with similar
* Note: The F2 and F4 series have a completely new GPIO peripheral with
* different configuration options. Here we implement a different API partly to
* more closely match the peripheral capabilities and also to deliberately
* break compatibility with old F1 code so there is no confusion with similar
* sounding functions that have very different functionality.
*/

24
include/libopencm3/stm32/common/hash_common_f24.h
View File

@@ -1,6 +1,7 @@
/** @addtogroup hash_defines
@author @htmlonly &copy; @endhtmlonly 2013 Mikhail Avkhimenia <mikhail@avkhimenia.net>
@author @htmlonly &copy; @endhtmlonly 2013
Mikhail Avkhimenia <mikhail@avkhimenia.net>
*/
@@ -38,32 +39,32 @@
@ingroup STM32F_hash_defines
@{*/
#define HASH_BASE (PERIPH_BASE_AHB2 + 0x60400)
#define HASH_BASE (PERIPH_BASE_AHB2 + 0x60400)
#define HASH HASH_BASE
/**@}*/
/* --- HASH registers ------------------------------------------------------ */
/* HASH control register (HASH_CR) */
#define HASH_CR MMIO32(HASH + 0x00)
#define HASH_CR MMIO32(HASH + 0x00)
/* HASH data input register (HASH_DIR) */
#define HASH_DIN MMIO32(HASH + 0x04)
#define HASH_DIN MMIO32(HASH + 0x04)
/* HASH start register (HASH_STR) */
#define HASH_STR MMIO32(HASH + 0x08)
#define HASH_STR MMIO32(HASH + 0x08)
/* HASH digest registers (HASH_HR[5]) */
#define HASH_HR ((volatile uint32_t*)(HASH + 0x0C)) //x5
#define HASH_HR ((volatile uint32_t*)(HASH + 0x0C)) /* x5 */
/* HASH interrupt enable register (HASH_IMR) */
#define HASH_IMR MMIO32(HASH + 0x20)
#define HASH_IMR MMIO32(HASH + 0x20)
/* HASH status register (HASH_SR) */
#define HASH_SR MMIO32(HASH + 0x28)
#define HASH_SR MMIO32(HASH + 0x28)
/* HASH context swap registers (HASH_CSR[51]) */
#define HASH_CSR ((volatile uint32_t*)(HASH + 0xF8)) //x51
#define HASH_CSR ((volatile uint32_t*)(HASH + 0xF8)) /* x51 */
/* --- HASH_CR values ------------------------------------------------------ */
@@ -127,7 +128,8 @@
/* --- HASH_STR values ----------------------------------------------------- */
/* NBLW: Number of valid bits in the last word of the message in the bit string */
/* NBLW: Number of valid bits in the last word of the message in the bit string
*/
#define HASH_STR_NBW (31 << 0)
/* DCAL: Digest calculation */
@@ -155,7 +157,7 @@
/* BUSY: Busy bit */
#define HASH_SR_BUSY (1 << 3)
/* --- HASH function prototypes ------------------------------------------------------- */
/* --- HASH function prototypes -------------------------------------------- */
BEGIN_DECLS

4
include/libopencm3/stm32/common/i2c_common_all.h
View File

@@ -23,12 +23,12 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA I2C.H
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA I2C.H
The order of header inclusion is important. i2c.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#if defined (LIBOPENCM3_I2C_H) || defined (LIBOPENCM3_I2C_COMMON_F24_H)
#if defined(LIBOPENCM3_I2C_H) || defined(LIBOPENCM3_I2C_COMMON_F24_H)
/** @endcond */
#ifndef LIBOPENCM3_I2C_COMMON_ALL_H
#define LIBOPENCM3_I2C_COMMON_ALL_H

5
include/libopencm3/stm32/common/i2c_common_f24.h
View File

@@ -1,6 +1,7 @@
/** @addtogroup i2c_defines
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
@author @htmlonly &copy; @endhtmlonly 2012
Ken Sarkies <ksarkies@internode.on.net>
*/
@@ -23,7 +24,7 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA I2C.H
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA I2C.H
The order of header inclusion is important. i2c.h includes the device
specific memorymap.h header before including this header file.*/

2
include/libopencm3/stm32/common/iwdg_common_all.h
View File

@@ -22,7 +22,7 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA IWDG.H
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA IWDG.H
The order of header inclusion is important. iwdg.h includes the device
specific memorymap.h header before including this header file.*/

2
include/libopencm3/stm32/common/pwr_common_all.h
View File

@@ -23,7 +23,7 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA PWR.H
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA PWR.H
The order of header inclusion is important. pwr.h includes the device
specific memorymap.h header before including this header file.*/

4
include/libopencm3/stm32/common/rng_common_f24.h
View File

@@ -16,7 +16,7 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA RNG.H
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA RNG.H
The order of header inclusion is important. rng.h includes the device
specific memorymap.h header before including this header file.*/
@@ -32,7 +32,7 @@ specific memorymap.h header before including this header file.*/
/* --- Random number generator registers ----------------------------------- */
/* Control register */
#define RNG_CR MMIO32(RNG_BASE + 0x00)
#define RNG_CR MMIO32(RNG_BASE + 0x00)
/* Status register */
#define RNG_SR MMIO32(RNG_BASE + 0x04)

78
include/libopencm3/stm32/common/rtc_common_bcd.h
View File

@@ -30,7 +30,7 @@
* only support a subset.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA RTC.H
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA RTC.H
The order of header inclusion is important. rtc.h includes the device
specific memorymap.h header before including this header file.*/
@@ -102,7 +102,8 @@ specific memorymap.h header before including this header file.*/
/* RTC time register (RTC_TR) ----------------------------------- */
/* Note: Bits [31:23], 15, and 7 are reserved, and must be kept at reset value. */
/* Note: Bits [31:23], 15, and 7 are reserved, and must be kept at reset value.
*/
#define RTC_TR_PM (1 << 22) /* AM/PM notation */
#define RTC_TR_HT_SHIFT (20) /* Hour tens in BCD format shift */
#define RTC_TR_HT_MASK (0x3) /* Hour tens in BCD format mask */
@@ -118,7 +119,8 @@ specific memorymap.h header before including this header file.*/
#define RTC_TR_SU_MASK (0xf) /* Second units in BCD format mask */
/* RTC date register (RTC_DR) ----------------------------------- */
/* Note: Bits [31:24] and [7:6] are reserved, and must be kept at reset value. */
/* Note: Bits [31:24] and [7:6] are reserved, and must be kept at reset value.
*/
#define RTC_DR_YT_SHIFT (20) /* Year tens in BCD format shift */
#define RTC_DR_YT_MASK (0xf) /* Year tens in BCD format mask */
#define RTC_DR_YU_SHIFT (16) /* Year units in BCD format shift */
@@ -136,12 +138,18 @@ specific memorymap.h header before including this header file.*/
/* RTC control register (RTC_CR) -------------------------------- */
/* Note: Bits [31:24] are reserved, and must be kept at reset value. */
/* Note: Bits 7, 6 and 4 of this register can be written in initialization mode only (RTC_ISR/INITF = 1). */
/* Note: Bits 2 to 0 of this register can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1. */
/* Note: Bits 7, 6 and 4 of this register can be written in initialization mode
* only (RTC_ISR/INITF = 1).
*/
/* Note: Bits 2 to 0 of this register can be written only when RTC_CR WUTE bit
* = 0 and RTC_ISR WUTWF bit = 1.
*/
#define RTC_CR_COE (1<<23) /* RTC_CR_COE: Calibration output enable */
/* RTC_CR_OSEL: Output selection values */
/* Note: These bits are used to select the flag to be routed to AFO_ALARM RTC output */
/* Note: These bits are used to select the flag to be routed to AFO_ALARM RTC
* output
*/
#define RTC_CR_OSEL_SHIFT 21
#define RTC_CR_OSEL_MASK (0x3)
#define RTC_CR_OSEL_DISABLED (0x0)
@@ -150,23 +158,34 @@ specific memorymap.h header before including this header file.*/
#define RTC_CR_OSEL_WAKEUP (0x3)
#define RTC_CR_POL (1<<20) /* RTC_CR_POL: Output polarity */
#define RTC_CR_COSEL (1<<19) /* RTC_CR_COSEL: Calibration output selection */
#define RTC_CR_COSEL (1<<19) /* RTC_CR_COSEL: Calibration output
selection */
#define RTC_CR_BKP (1<<18) /* RTC_CR_BKP: Backup */
#define RTC_CR_SUB1H (1<<17) /* RTC_CR_SUB1H: Subtract 1 hour (winter time change) */
#define RTC_CR_ADD1H (1<<16) /* RTC_CR_ADD1H: Add 1 hour (summer time change) */
#define RTC_CR_TSIE (1<<15) /* RTC_CR_TSIE: Timestamp interrupt enable */
#define RTC_CR_WUTIE (1<<14) /* RTC_CR_WUTIE: Wakeup timer interrupt enable */
#define RTC_CR_ALRBIE (1<<13) /* RTC_CR_ALRBIE: Alarm B interrupt enable */
#define RTC_CR_ALRAIE (1<<12) /* RTC_CR_ALRAIE: Alarm A interrupt enable */
#define RTC_CR_SUB1H (1<<17) /* RTC_CR_SUB1H: Subtract 1 hour
(winter time change) */
#define RTC_CR_ADD1H (1<<16) /* RTC_CR_ADD1H: Add 1 hour (summer
time change) */
#define RTC_CR_TSIE (1<<15) /* RTC_CR_TSIE: Timestamp interrupt
enable */
#define RTC_CR_WUTIE (1<<14) /* RTC_CR_WUTIE: Wakeup timer
interrupt enable */
#define RTC_CR_ALRBIE (1<<13) /* RTC_CR_ALRBIE: Alarm B interrupt
enable */
#define RTC_CR_ALRAIE (1<<12) /* RTC_CR_ALRAIE: Alarm A interrupt
enable */
#define RTC_CR_TSE (1<<11) /* RTC_CR_TSE: Time stamp enable */
#define RTC_CR_WUTE (1<<10) /* RTC_CR_WUTE: Wakeup timer enable */
#define RTC_CR_ALRBE (1<<9) /* RTC_CR_ALRBIE: Alarm B enable */
#define RTC_CR_ALRAE (1<<8) /* RTC_CR_ALRAE: Alarm A enable */
#define RTC_CR_DCE (1<<7) /* RTC_CR_DCE: Course digital calibration enable */
#define RTC_CR_DCE (1<<7) /* RTC_CR_DCE: Course digital
calibration enable */
#define RTC_CR_FMT (1<<6) /* RTC_CR_FMT: Hour format */
#define RTC_CR_BYPSHAD (1<<5) /* RTC_CR_BYPSHAD: Bypass the shadow registers */
#define RTC_CR_REFCKON (1<<4) /* RTC_CR_REFCKON: Reference clock detection enable */
#define RTC_CR_TSEDGE (1<<3) /* RTC_CR_TSEDGE: Timestamp event active edge */
#define RTC_CR_BYPSHAD (1<<5) /* RTC_CR_BYPSHAD: Bypass the shadow
registers */
#define RTC_CR_REFCKON (1<<4) /* RTC_CR_REFCKON: Reference clock
detection enable */
#define RTC_CR_TSEDGE (1<<3) /* RTC_CR_TSEDGE: Timestamp event
active edge */
/* RTC_CR_WUCKSEL: Wakeup clock selection */
#define RTC_CR_WUCLKSEL_SHIFT (0)
@@ -181,8 +200,9 @@ specific memorymap.h header before including this header file.*/
/* RTC initialization and status register (RTC_ISR) ------------- */
/* Note: Bits [31:17] and [15] are reserved, and must be kept at reset value. */
/* Note: This register is write protected (except for RTC_ISR[13:8] bits). */
#define RTC_ISR_RECALPF (1<<16) /* RECALPF: Recalibration pending flag */
#define RTC_ISR_TAMP3F (1<<15) /* TAMP3F: TAMPER3 detection flag (not available on F4)*/
#define RTC_ISR_RECALPF (1<<16) /* RECALPF: Recalib pending flag */
#define RTC_ISR_TAMP3F (1<<15) /* TAMP3F: TAMPER3 detection flag
(not on F4)*/
#define RTC_ISR_TAMP2F (1<<14) /* TAMP2F: TAMPER2 detection flag */
#define RTC_ISR_TAMP1F (1<<13) /* TAMP1F: TAMPER detection flag */
#define RTC_ISR_TSOVF (1<<12) /* TSOVF: Timestamp overflow flag */
@@ -192,21 +212,21 @@ specific memorymap.h header before including this header file.*/
#define RTC_ISR_ALRAF (1<<8) /* ALRAF: Alarm A flag */
#define RTC_ISR_INIT (1<<7) /* INIT: Initialization mode */
#define RTC_ISR_INITF (1<<6) /* INITF: Initialization flag */
#define RTC_ISR_RSF (1<<5) /* RSF: Registers synchronization flag */
#define RTC_ISR_INITS (1<<4) /* INITS: Initialization status flag */
#define RTC_ISR_RSF (1<<5) /* RSF: Registers sync flag */
#define RTC_ISR_INITS (1<<4) /* INITS: Init status flag */
#define RTC_ISR_SHPF (1<<3) /* SHPF: Shift operation pending */
#define RTC_ISR_WUTWF (1<<2) /* WUTWF: Wakeup timer write flag */
#define RTC_ISR_ALRBWF (1<<1) /* ALRBWF: Alarm B write flag */
#define RTC_ISR_ALRAWF (1<<0) /* ALRAWF: Alarm A write flag */
/* RTC prescaler register (RTC_PRER) ---------------------------- */
#define RTC_PRER_PREDIV_A_SHIFT (16) /* Asynchronous prescaler factor shift */
#define RTC_PRER_PREDIV_A_MASK (0x7f) /* Asynchronous prescaler factor mask */
#define RTC_PRER_PREDIV_S_SHIFT (0) /* Synchronous prescaler factor shift */
#define RTC_PRER_PREDIV_S_MASK (0x7fff) /* Synchronous prescaler factor mask */
#define RTC_PRER_PREDIV_A_SHIFT (16) /* Async prescaler factor shift */
#define RTC_PRER_PREDIV_A_MASK (0x7f) /* Async prescaler factor mask */
#define RTC_PRER_PREDIV_S_SHIFT (0) /* Sync prescaler factor shift */
#define RTC_PRER_PREDIV_S_MASK (0x7fff) /* Sync prescaler factor mask */
/* RTC calibration register (RTC_CALIBR) ------------------------ */
// FIXME - TODO
/* FIXME - TODO */
/* RTC Alarm register ------------------------------------------- */
/* Note: Applies to RTC_ALRMAR and RTC_ALRMBR */
@@ -234,7 +254,7 @@ specific memorymap.h header before including this header file.*/
#define RTC_ALRMXR_SU_MASK (0xf)
/* RTC shift control register (RTC_SHIFTR) */
// FIXME - TODO
/* FIXME - TODO */
/* RTC time stamp time register (RTC_TSTR) ---------------------- */
#define RTC_TSTR_PM (1<<22)
@@ -263,7 +283,7 @@ specific memorymap.h header before including this header file.*/
#define RTC_TSDR_DU_MASK (0xf)
/* RTC calibration register (RTC_CALR) -------------------------- */
// FIXME - TODO
/* FIXME - TODO */
/* RTC tamper and alternate function configuration register (RTC_TAFCR) --- */
#define RTC_TAFCR_ALARMOUTTYPE (1<<18)
@@ -304,7 +324,7 @@ specific memorymap.h header before including this header file.*/
#define RTC_TAFCR_TAMP1E (1<<0)
/* RTC alarm X sub second register */
// FIXME - TODO
/* FIXME - TODO */

4
include/libopencm3/stm32/common/spi_common_all.h
View File

@@ -23,12 +23,12 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H
The order of header inclusion is important. spi.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#if defined (LIBOPENCM3_SPI_H) || defined (LIBOPENCM3_SPI_COMMON_F24_H)
#if defined(LIBOPENCM3_SPI_H) || defined(LIBOPENCM3_SPI_COMMON_F24_H)
/** @endcond */
#ifndef LIBOPENCM3_SPI_COMMON_ALL_H
#define LIBOPENCM3_SPI_COMMON_ALL_H

2
include/libopencm3/stm32/common/spi_common_f24.h
View File

@@ -22,7 +22,7 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H
The order of header inclusion is important. spi.h includes the device
specific memorymap.h header before including this header file.*/

30
include/libopencm3/stm32/common/timer_common_all.h
View File

@@ -25,12 +25,12 @@
/**@{*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA TIMER.H
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA TIMER.H
The order of header inclusion is important. timer.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#if defined (LIBOPENCM3_TIMER_H) || defined (LIBOPENCM3_TIMER_COMMON_F24_H)
#if defined(LIBOPENCM3_TIMER_H) || defined(LIBOPENCM3_TIMER_COMMON_F24_H)
/** @endcond */
#ifndef LIBOPENCM3_TIMER_COMMON_H
#define LIBOPENCM3_TIMER_COMMON_H
@@ -434,14 +434,19 @@ level. */
/** Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges
depending on the level of the complementary input. */
#define TIM_SMCR_SMS_EM3 (0x3 << 0)
/** Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
and generates an update of the registers. */
/** Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes
* the counter and generates an update of the registers.
*/
#define TIM_SMCR_SMS_RM (0x4 << 0)
/** Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. */
/** Gated Mode - The counter clock is enabled when the trigger input (TRGI) is
* high.
*/
#define TIM_SMCR_SMS_GM (0x5 << 0)
/** Trigger Mode - The counter starts at a rising edge of the trigger TRGI. */
#define TIM_SMCR_SMS_TM (0x6 << 0)
/** External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. */
/** External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock
* the counter.
*/
#define TIM_SMCR_SMS_ECM1 (0x7 << 0)
#define TIM_SMCR_SMS_MASK (0x7 << 0)
/**@}*/
@@ -936,7 +941,7 @@ and generates an update of the registers. */
/** Output Compare channel designators */
enum tim_oc_id {
TIM_OC1=0,
TIM_OC1 = 0,
TIM_OC1N,
TIM_OC2,
TIM_OC2N,
@@ -968,8 +973,8 @@ enum tim_ic_id {
/** Input Capture input filter. The frequency used to sample the
input and the number of events needed to validate an output transition.
TIM_IC_CK_INT_N_x No division from the Deadtime and Sampling Clock frequency (DTF),
filter length x
TIM_IC_CK_INT_N_x No division from the Deadtime and Sampling Clock frequency
(DTF), filter length x
TIM_IC_DTF_DIV_y_N_x Division by y from the DTF, filter length x
*/
enum tim_ic_filter {
@@ -1020,7 +1025,7 @@ enum tim_et_pol {
TIM_ET_FALLING,
};
/* --- TIM function prototypes ------------------------------------------------------- */
/* --- TIM function prototypes --------------------------------------------- */
BEGIN_DECLS
@@ -1064,7 +1069,8 @@ void timer_enable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id);
void timer_disable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_fast_mode(u32 timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_slow_mode(u32 timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id, enum tim_oc_mode oc_mode);
void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id,
enum tim_oc_mode oc_mode);
void timer_enable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id);
void timer_disable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_polarity_high(u32 timer_peripheral, enum tim_oc_id oc_id);
@@ -1109,7 +1115,7 @@ END_DECLS
#endif
/** @cond */
#else
#warning "timer_common_all.h should not be included explicitly, only via timer.h"
#warning "timer_common_all.h should not be included directly, only via timer.h"
#endif
/** @endcond */
/**@}*/

4
include/libopencm3/stm32/common/timer_common_f24.h
View File

@@ -23,7 +23,7 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA TIMER.H
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA TIMER.H
The order of header inclusion is important. timer.h includes the device
specific memorymap.h header before including this header file.*/
@@ -106,7 +106,7 @@ END_DECLS
#endif
/** @cond */
#else
#warning "timer_common_f24.h should not be included explicitly, only via timer.h"
#warning "timer_common_f24.h should not be included directly, only via timer.h"
#endif
/** @endcond */

10
include/libopencm3/stm32/common/usart_common_all.h
View File

@@ -25,12 +25,12 @@
/**@{*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA USART.H
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA USART.H
The order of header inclusion is important. usart.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#if defined (LIBOPENCM3_USART_H) || defined (LIBOPENCM3_USART_COMMON_F24_H)
#if defined(LIBOPENCM3_USART_H) || defined(LIBOPENCM3_USART_COMMON_F24_H)
/** @endcond */
#ifndef LIBOPENCM3_USART_COMMON_ALL_H
#define LIBOPENCM3_USART_COMMON_ALL_H
@@ -324,9 +324,9 @@ specific memorymap.h header before including this header file.*/
@{*/
#define USART_STOPBITS_1 USART_CR2_STOPBITS_1 /* 1 stop bit */
#define USART_STOPBITS_0_5 USART_CR2_STOPBITS_0_5 /* 0.5 stop bits */
#define USART_STOPBITS_0_5 USART_CR2_STOPBITS_0_5 /* .5 stop bit */
#define USART_STOPBITS_2 USART_CR2_STOPBITS_2 /* 2 stop bits */
#define USART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5 /* 1.5 stop bits */
#define USART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5 /* 1.5 stop bit*/
/**@}*/
/* CR3_CTSE/CR3_RTSE combined values */
@@ -378,7 +378,7 @@ END_DECLS
#endif
/** @cond */
#else
#warning "usart_common_all.h should not be included explicitly, only via usart.h"
#warning "usart_common_all.h should not be included directly, only via usart.h"
#endif
/** @endcond */
/**@}*/

4
include/libopencm3/stm32/common/usart_common_f24.h
View File

@@ -24,7 +24,7 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA USART.H
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA USART.H
The order of header inclusion is important. usart.h includes the device
specific memorymap.h header before including this header file.*/
@@ -76,7 +76,7 @@ specific memorymap.h header before including this header file.*/
#endif
/** @cond */
#else
#warning "usart_common_f24.h should not be included explicitly, only via usart.h"
#warning "usart_common_f24.h should not be included directly, only via usart.h"
#endif
/** @endcond */

27
include/libopencm3/stm32/f1/adc.h
View File

@@ -1,12 +1,14 @@
/** @defgroup adc_defines ADC Defines
@brief <b>Defined Constants and Types for the STM32F1xx Analog to Digital Converters</b>
@brief <b>Defined Constants and Types for the STM32F1xx Analog to Digital
Converters</b>
@ingroup STM32F1xx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2009 Edward Cheeseman <evbuilder@users.sourceforge.net>
@author @htmlonly &copy; @endhtmlonly 2009
Edward Cheeseman <evbuilder@users.sourceforge.net>
@date 18 August 2012
@@ -404,7 +406,8 @@ LGPL License Terms @ref lgpl_license
/* The following are only valid for ADC1 and ADC2. */
/****************************************************************************/
/* ADC_CR2 JEXTSEL[2:0] ADC Injected Trigger Identifier for ADC1 and ADC2 */
/** @defgroup adc_trigger_injected_12 ADC Injected Trigger Identifier for ADC1 and ADC2
/** @defgroup adc_trigger_injected_12 ADC Injected Trigger Identifier for ADC1
and ADC2
@ingroup adc_defines
@{*/
@@ -677,7 +680,8 @@ void adc_reset_calibration(u32 adc);
void adc_calibration(u32 adc);
void adc_set_continuous_conversion_mode(u32 adc);
void adc_set_single_conversion_mode(u32 adc);
void adc_on(u32 adc) LIBOPENCM3_DEPRECATED("will be removed in the first release");
void adc_on(u32 adc)
LIBOPENCM3_DEPRECATED("will be removed in the first release");
void adc_off(u32 adc);
void adc_set_sample_time(u32 adc, u8 channel, u8 time);
void adc_set_sample_time_on_all_channels(u32 adc, u8 time);
@@ -686,11 +690,16 @@ void adc_set_watchdog_low_threshold(u32 adc, u16 threshold);
void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]);
void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]);
void adc_set_continous_conversion_mode(u32 adc) LIBOPENCM3_DEPRECATED("change to adc_set_continuous_conversion_mode");
void adc_set_conversion_time(u32 adc, u8 channel, u8 time) LIBOPENCM3_DEPRECATED("change to adc_set_sample_time");
void adc_set_conversion_time_on_all_channels(u32 adc, u8 time) LIBOPENCM3_DEPRECATED("change to adc_set_sample_time_on_all_channels");
void adc_enable_jeoc_interrupt(u32 adc) LIBOPENCM3_DEPRECATED("change to adc_enable_eoc_interrupt_injected");
void adc_disable_jeoc_interrupt(u32 adc) LIBOPENCM3_DEPRECATED("change to adc_disable_eoc_interrupt_injected");
void adc_set_continous_conversion_mode(u32 adc)
LIBOPENCM3_DEPRECATED("change to adc_set_continuous_conversion_mode");
void adc_set_conversion_time(u32 adc, u8 channel, u8 time)
LIBOPENCM3_DEPRECATED("change to adc_set_sample_time");
void adc_set_conversion_time_on_all_channels(u32 adc, u8 time)
LIBOPENCM3_DEPRECATED("change to adc_set_sample_time_on_all_channels");
void adc_enable_jeoc_interrupt(u32 adc)
LIBOPENCM3_DEPRECATED("change to adc_enable_eoc_interrupt_injected");
void adc_disable_jeoc_interrupt(u32 adc)
LIBOPENCM3_DEPRECATED("change to adc_disable_eoc_interrupt_injected");
END_DECLS
#endif

3
include/libopencm3/stm32/f1/crc.h
View File

@@ -1,6 +1,7 @@
/** @defgroup crc_defines CRC Defines
@brief <b>libopencm3 Defined Constants and Types for the STM32F1xx CRC Generator </b>
@brief <b>libopencm3 Defined Constants and Types for the STM32F1xx CRC
Generator </b>
@ingroup STM32F1xx_defines

2
include/libopencm3/stm32/f1/flash.h
View File

@@ -22,7 +22,7 @@
* For details see:
* PM0075 programming manual: STM32F10xxx Flash programming
* August 2010, Doc ID 17863 Rev 1
* http://www.st.com/st-web-ui/static/active/en/resource/technical/document/programming_manual/CD00283419.pdf
* http://goo.gl/MuTiU
*/
#ifndef LIBOPENCM3_FLASH_H

105
include/libopencm3/stm32/f1/gpio.h
View File

@@ -497,26 +497,26 @@ LGPL License Terms @ref lgpl_license
/* ETH GPIO */
#define GPIO_ETH_RX_DV_CRS_DV GPIO7 /* PA7 */
#define GPIO_ETH_RXD0 GPIO4 /* PC4 */
#define GPIO_ETH_RXD0 GPIO4 /* PC4 */
#define GPIO_ETH_RXD1 GPIO5 /* PC5 */
#define GPIO_ETH_RXD2 GPIO0 /* PB0 */
#define GPIO_ETH_RXD3 GPIO1 /* PB1 */
#define GPIO_ETH_RE_RX_DV_CRS_DV GPIO8 /* PD8 */
#define GPIO_ETH_RE_RXD0 GPIO9 /* PD9 */
#define GPIO_ETH_RE_RXD0 GPIO9 /* PD9 */
#define GPIO_ETH_RE_RXD1 GPIO10 /* PD10 */
#define GPIO_ETH_RE_RXD2 GPIO11 /* PD11 */
#define GPIO_ETH_RE_RXD3 GPIO12 /* PD12 */
/* ETH BANK */
#define GPIO_BANK_ETH_RX_DV_CRS_DV GPIOA /* PA7 */
#define GPIO_BANK_ETH_RXD0 GPIOC /* PC4 */
#define GPIO_BANK_ETH_RXD0 GPIOC /* PC4 */
#define GPIO_BANK_ETH_RXD1 GPIOC /* PC5 */
#define GPIO_BANK_ETH_RXD2 GPIOB /* PB0 */
#define GPIO_BANK_ETH_RXD3 GPIOB /* PB1 */
#define GPIO_BANK_ETH_RE_RX_DV_CRS_DV GPIOD /* PD8 */
#define GPIO_BANK_ETH_RE_RXD0 GPIOD /* PD9 */
#define GPIO_BANK_ETH_RE_RXD0 GPIOD /* PD9 */
#define GPIO_BANK_ETH_RE_RXD1 GPIOD /* PD10 */
#define GPIO_BANK_ETH_RE_RXD2 GPIOD /* PD11 */
#define GPIO_BANK_ETH_RE_RXD3 GPIOD /* PD12 */
@@ -729,28 +729,28 @@ Line Devices only
@ingroup gpio_defines
@{*/
/* PTP_PPS_REMAP: *//** Ethernet PTP PPS remapping
* (only connectivity line devices) */
/* PTP_PPS_REMAP: */
/** Ethernet PTP PPS remapping (only connectivity line devices) */
#define AFIO_MAPR_PTP_PPS_REMAP (1 << 30)
/* TIM2ITR1_IREMAP: *//** TIM2 internal trigger 1 remapping
* (only connectivity line devices) */
/* TIM2ITR1_IREMAP: */
/** TIM2 internal trigger 1 remapping (only connectivity line devices) */
#define AFIO_MAPR_TIM2ITR1_IREMAP (1 << 29)
/* SPI3_REMAP: *//** SPI3/I2S3 remapping
* (only connectivity line devices) */
/* SPI3_REMAP: */
/** SPI3/I2S3 remapping (only connectivity line devices) */
#define AFIO_MAPR_SPI3_REMAP (1 << 28)
/* MII_REMAP: */ /** MII or RMII selection
* (only connectivity line devices) */
/* MII_REMAP: */
/** MII or RMII selection (only connectivity line devices) */
#define AFIO_MAPR_MII_RMII_SEL (1 << 23)
/* CAN2_REMAP: */ /** CAN2 I/O remapping
* (only connectivity line devices) */
/* CAN2_REMAP: */
/** CAN2 I/O remapping (only connectivity line devices) */
#define AFIO_MAPR_CAN2_REMAP (1 << 22)
/* ETH_REMAP: */ /** Ethernet MAC I/O remapping
* (only connectivity line devices) */
/* ETH_REMAP: */
/** Ethernet MAC I/O remapping (only connectivity line devices) */
#define AFIO_MAPR_ETH_REMAP (1 << 21)
/**@}*/
@@ -763,9 +763,9 @@ Line Devices only
@{*/
#define AFIO_MAPR_SWJ_MASK (0x7 << 24)
/** Full Serial Wire JTAG capability */
/** Full Serial Wire JTAG capability */
#define AFIO_MAPR_SWJ_CFG_FULL_SWJ (0x0 << 24)
/** Full Serial Wire JTAG capability without JNTRST */
/** Full Serial Wire JTAG capability without JNTRST */
#define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_JNTRST (0x1 << 24)
/** JTAG-DP disabled with SW-DP enabled */
#define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON (0x2 << 24)
@@ -777,41 +777,60 @@ Line Devices only
@ingroup gpio_defines
@{*/
/* ADC2_ETRGREG_REMAP: */ /** ADC2 external trigger regulator conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) */
/* ADC2_ETRGREG_REMAP: */
/**
* ADC2 external trigger regulator conversion remapping
* (only low-, medium-, high- and XL-densitiy devices)
*/
#define AFIO_MAPR_ADC2_ETRGREG_REMAP (1 << 20)
/* ADC2_ETRGINJ_REMAP: */ /** ADC2 external trigger injected conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) */
/* ADC2_ETRGINJ_REMAP: */
/**
* ADC2 external trigger injected conversion remapping
* (only low-, medium-, high- and XL-densitiy devices)
*/
#define AFIO_MAPR_ADC2_ETRGINJ_REMAP (1 << 19)
/* ADC1_ETRGREG_REMAP: */ /** ADC1 external trigger regulator conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) */
/* ADC1_ETRGREG_REMAP: */
/**
* ADC1 external trigger regulator conversion remapping
* (only low-, medium-, high- and XL-densitiy devices)
*/
#define AFIO_MAPR_ADC1_ETRGREG_REMAP (1 << 18)
/* ADC1_ETRGINJ_REMAP: */ /** ADC1 external trigger injected conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) */
/* ADC1_ETRGINJ_REMAP: */
/**
* ADC1 external trigger injected conversion remapping
* (only low-, medium-, high- and XL-densitiy devices)
*/
#define AFIO_MAPR_ADC1_ETRGINJ_REMAP (1 << 17)
/* TIM5CH4_IREMAP: */ /** TIM5 channel4 internal remap */
/* TIM5CH4_IREMAP: */
/** TIM5 channel4 internal remap */
#define AFIO_MAPR_TIM5CH4_IREMAP (1 << 16)
/* PD01_REMAP: */ /** Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
/* PD01_REMAP: */
/** Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
#define AFIO_MAPR_PD01_REMAP (1 << 15)
/* TIM4_REMAP: */ /** TIM4 remapping */
/* TIM4_REMAP: */
/** TIM4 remapping */
#define AFIO_MAPR_TIM4_REMAP (1 << 12)
/* USART2_REMAP[1:0]: */ /** USART2 remapping */
/* USART2_REMAP[1:0]: */
/** USART2 remapping */
#define AFIO_MAPR_USART2_REMAP (1 << 3)
/* USART1_REMAP[1:0]: */ /** USART1 remapping */
/* USART1_REMAP[1:0]: */
/** USART1 remapping */
#define AFIO_MAPR_USART1_REMAP (1 << 2)
/* I2C1_REMAP[1:0]: */ /** I2C1 remapping */
/* I2C1_REMAP[1:0]: */
/** I2C1 remapping */
#define AFIO_MAPR_I2C1_REMAP (1 << 1)
/* SPI1_REMAP[1:0]: */ /** SPI1 remapping */
/* SPI1_REMAP[1:0]: */
/** SPI1 remapping */
#define AFIO_MAPR_SPI1_REMAP (1 << 0)
/**@}*/
@@ -821,7 +840,7 @@ Line Devices only
@{*/
#define AFIO_MAPR_CAN1_REMAP_PORTA (0x0 << 13)
#define AFIO_MAPR_CAN1_REMAP_PORTB (0x2 << 13) /* Not on 36pin pkg */
#define AFIO_MAPR_CAN1_REMAP_PORTB (0x2 << 13) /* Not 36pin pkg */
#define AFIO_MAPR_CAN1_REMAP_PORTD (0x3 << 13)
/**@}*/
@@ -870,22 +889,28 @@ Line Devices only
@ingroup gpio_defines
@{*/
/* FSMC_NADV_DISCONNECT: */ /** The NADV is disconnected from its allocated pin */
/* FSMC_NADV_DISCONNECT: */
/** The NADV is disconnected from its allocated pin */
#define AFIO_MAPR2_FSMC_NADV_DISCONNECT (1 << 10)
/* TIM14_REMAP: */ /** TIM14 remapping */
/* TIM14_REMAP: */
/** TIM14 remapping */
#define AFIO_MAPR2_TIM14_REMAP (1 << 9)
/* TIM13_REMAP: */ /** TIM13 remapping */
/* TIM13_REMAP: */
/** TIM13 remapping */
#define AFIO_MAPR2_TIM13_REMAP (1 << 8)
/* TIM11_REMAP: */ /** TIM11 remapping */
/* TIM11_REMAP: */
/** TIM11 remapping */
#define AFIO_MAPR2_TIM11_REMAP (1 << 7)
/* TIM10_REMAP: */ /** TIM10 remapping */
/* TIM10_REMAP: */
/** TIM10 remapping */
#define AFIO_MAPR2_TIM10_REMAP (1 << 6)
/* TIM9_REMAP: */ /** TIM9 remapping */
/* TIM9_REMAP: */
/** TIM9 remapping */
#define AFIO_MAPR2_TIM9_REMAP (1 << 5)
/**@}*/

3
include/libopencm3/stm32/f1/iwdg.h
View File

@@ -1,6 +1,7 @@
/** @defgroup iwdg_defines IWDG Defines
@brief <b>Defined Constants and Types for the STM32F1xx Independent Watchdog Timer</b>
@brief <b>Defined Constants and Types for the STM32F1xx Independent Watchdog
Timer</b>
@ingroup STM32F1xx_defines

21
include/libopencm3/stm32/f1/rcc.h
View File

@@ -6,8 +6,10 @@
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2009 Federico Ruiz-Ugalde \<memeruiz at gmail dot com\>
@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
@author @htmlonly &copy; @endhtmlonly 2009
Federico Ruiz-Ugalde \<memeruiz at gmail dot com\>
@author @htmlonly &copy; @endhtmlonly 2009
Uwe Hermann <uwe@hermann-uwe.de>
@date 18 August 2012
@@ -55,8 +57,8 @@ LGPL License Terms @ref lgpl_license
#define RCC_APB1ENR MMIO32(RCC_BASE + 0x1c)
#define RCC_BDCR MMIO32(RCC_BASE + 0x20)
#define RCC_CSR MMIO32(RCC_BASE + 0x24)
#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28) /* (**) */
#define RCC_CFGR2 MMIO32(RCC_BASE + 0x2c) /* (**) */
#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28) /*(**)*/
#define RCC_CFGR2 MMIO32(RCC_BASE + 0x2c) /*(**)*/
/* --- RCC_CR values ------------------------------------------------------- */
@@ -125,9 +127,10 @@ LGPL License Terms @ref lgpl_license
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL13 0xb /* (XX) */
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL14 0xc /* (XX) */
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL15 0xd /* 0xd: PLL x 15 */
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL6_5 0xd /* 0xd: PLL x 6.5 for conn. line */
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL6_5 0xd /* 0xd: PLL x 6.5 for conn.
line */
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL16 0xe /* (XX) */
// #define PLLMUL_PLL_CLK_MUL16 0xf /* (XX) */ /* Errata? 17? */
/* #define PLLMUL_PLL_CLK_MUL16 0xf */ /* (XX) */ /* Errata? 17? */
/**@}*/
/* TODO: conn. line differs. */
@@ -286,7 +289,8 @@ LGPL License Terms @ref lgpl_license
#define RCC_APB1RSTR_BKPRST (1 << 27)
#define RCC_APB1RSTR_CAN2RST (1 << 26) /* (**) */
#define RCC_APB1RSTR_CAN1RST (1 << 25) /* (**) */
#define RCC_APB1RSTR_CANRST (1 << 25) /* (XX) Alias for CAN1RST */
#define RCC_APB1RSTR_CANRST (1 << 25) /* (XX) Alias for
CAN1RST */
#define RCC_APB1RSTR_USBRST (1 << 23) /* (XX) */
#define RCC_APB1RSTR_I2C2RST (1 << 22)
#define RCC_APB1RSTR_I2C1RST (1 << 21)
@@ -358,7 +362,8 @@ LGPL License Terms @ref lgpl_license
#define RCC_APB1ENR_BKPEN (1 << 27)
#define RCC_APB1ENR_CAN2EN (1 << 26) /* (**) */
#define RCC_APB1ENR_CAN1EN (1 << 25) /* (**) */
#define RCC_APB1ENR_CANEN (1 << 25) /* (XX) Alias for CAN1EN */
#define RCC_APB1ENR_CANEN (1 << 25) /* (XX) Alias for
CAN1EN */
#define RCC_APB1ENR_USBEN (1 << 23) /* (XX) */
#define RCC_APB1ENR_I2C2EN (1 << 22)
#define RCC_APB1ENR_I2C1EN (1 << 21)

9
include/libopencm3/stm32/f1/usb.h
View File

@@ -6,7 +6,8 @@
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2009 Piotr Esden-Tempski <piotr@esden.net>
@author @htmlonly &copy; @endhtmlonly 2009
Piotr Esden-Tempski <piotr@esden.net>
@date 11 March 2013
@@ -131,9 +132,9 @@ LGPL License Terms @ref lgpl_license
#define USB_EP_SETUP 0x0800 /* Setup transaction completed */
#define USB_EP_TYPE 0x0600 /* Endpoint type */
#define USB_EP_KIND 0x0100 /* Endpoint kind.
* When set and type=bulk -> double buffer
* When set and type=control -> status out
*/
* When set and type=bulk -> double buffer
* When set and type=control -> status out
*/
#define USB_EP_TX_CTR 0x0080 /* Correct transfer TX */
#define USB_EP_TX_DTOG 0x0040 /* Data toggle TX */

3
include/libopencm3/stm32/f2/crc.h
View File

@@ -1,6 +1,7 @@
/** @defgroup crc_defines CRC Defines
@brief <b>libopencm3 Defined Constants and Types for the STM32F2xx CRC Generator </b>
@brief <b>libopencm3 Defined Constants and Types for the STM32F2xx CRC
Generator </b>
@ingroup STM32F2xx_defines

3
include/libopencm3/stm32/f2/iwdg.h
View File

@@ -1,6 +1,7 @@
/** @defgroup iwdg_defines IWDG Defines
@brief <b>Defined Constants and Types for the STM32F2xx Independent Watchdog Timer</b>
@brief <b>Defined Constants and Types for the STM32F2xx Independent Watchdog
Timer</b>
@ingroup STM32F2xx_defines

2
include/libopencm3/stm32/f2/memorymap.h
View File

@@ -22,7 +22,7 @@
#include <libopencm3/cm3/memorymap.h>
/* --- STM32F20x specific peripheral definitions ------------------------------- */
/* --- STM32F20x specific peripheral definitions --------------------------- */
/* Memory map for all busses */
#define PERIPH_BASE 0x40000000

6
include/libopencm3/stm32/f2/rcc.h
View File

@@ -77,7 +77,7 @@
#define RCC_CR_HSIRDY (1 << 1)
#define RCC_CR_HSION (1 << 0)
/* --- RCC_PLLCFGR values ------------------------------------------------------- */
/* --- RCC_PLLCFGR values -------------------------------------------------- */
/* PLLQ: [27:24] */
#define RCC_PLLCFGR_PLLQ_SHIFT 24
@@ -342,8 +342,8 @@
#define RCC_AHB1LPENR_DMA1LPEN (1 << 21)
#define RCC_AHB1LPENR_BKPSRAMLPEN (1 << 18)
#define RCC_AHB1LPENR_SRAM2LPEN (1 << 17)
#define RCC_AHB1LPENR_SRAM1LPEN (1 << 16)
#define RCC_AHB1LPENR_FLITFLPEN (1 << 15)
#define RCC_AHB1LPENR_SRAM1LPEN (1 << 16)
#define RCC_AHB1LPENR_FLITFLPEN (1 << 15)
#define RCC_AHB1LPENR_CRCLPEN (1 << 12)
#define RCC_AHB1LPENR_IOPILPEN (1 << 8)
#define RCC_AHB1LPENR_IOPHLPEN (1 << 7)

64
include/libopencm3/stm32/f4/adc.h
View File

@@ -1,13 +1,16 @@
/** @defgroup STM32F4xx_adc_defines ADC Defines
@brief <b>Defined Constants and Types for the STM32F4xx Analog to Digital Converters</b>
@brief <b>Defined Constants and Types for the STM32F4xx Analog to Digital
Converters</b>
@ingroup STM32F4xx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2012 Matthew Lai <m@matthewlai.ca>
@author @htmlonly &copy; @endhtmlonly 2009 Edward Cheeseman <evbuilder@users.sourceforge.net>
@author @htmlonly &copy; @endhtmlonly 2012
Matthew Lai <m@matthewlai.ca>
@author @htmlonly &copy; @endhtmlonly 2009
Edward Cheeseman <evbuilder@users.sourceforge.net>
@date 31 August 2012
@@ -164,9 +167,9 @@ LGPL License Terms @ref lgpl_license
/* ADC common (shared) registers */
#define ADC_COMMON_REGISTERS_BASE (ADC1_BASE+0x300)
#define ADC_CSR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x0)
#define ADC_CCR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x4)
#define ADC_CDR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x8)
#define ADC_CSR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x0)
#define ADC_CCR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x4)
#define ADC_CDR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x8)
/* --- ADC Channels ------------------------------------------------------- */
@@ -207,7 +210,7 @@ LGPL License Terms @ref lgpl_license
#define ADC_SR_EOC (1 << 1)
#define ADC_SR_AWD (1 << 0)
/* --- ADC_CR1 values specific to STM32F2,4------------------------------------ */
/* --- ADC_CR1 values specific to STM32F2,4--------------------------------- */
/* OVRIE: Overrun interrupt enable */
#define ADC_CR1_OVRIE (1 << 26)
@@ -281,7 +284,7 @@ LGPL License Terms @ref lgpl_license
/* AWDCH[4:0]: Analog watchdog channel bits. (Up to 17 other values reserved) */
/* Notes:
* ADC1: Analog channel 16 and 17 are internally connected to the temperature
* sensor and V_REFINT, respectively.
* sensor and V_REFINT, respectively.
* ADC2: Analog channel 16 and 17 are internally connected to V_SS.
* ADC3: Analog channel 9, 14, 15, 16 and 17 are internally connected to V_SS.
*/
@@ -567,7 +570,8 @@ LGPL License Terms @ref lgpl_license
/* JL[2:0]: Discontinous mode channel count injected channels. */
/****************************************************************************/
/** @defgroup adc_jsqr_jl ADC Number of channels in discontinuous mode fro injected channels.
/** @defgroup adc_jsqr_jl ADC Number of channels in discontinuous mode fro
injected channels.
@ingroup STM32F4xx_adc_defines
@{*/
@@ -733,33 +737,45 @@ LGPL License Terms @ref lgpl_license
/** All ADCs independent */
#define ADC_CCR_MULTI_INDEPENDENT (0x00 << 0)
/* dual modes (ADC1 + ADC2) */
/** Dual modes (ADC1 + ADC2) Combined regular simultaneous + injected simultaneous mode */
/* Dual modes (ADC1 + ADC2) */
/**
* Dual modes (ADC1 + ADC2) Combined regular simultaneous +
* injected simultaneous mode.
*/
#define ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_INJECTED_SIMUL (0x01 << 0)
/** Dual modes (ADC1 + ADC2) Combined regular simultaneous + alternate trigger mode. */
/**
* Dual modes (ADC1 + ADC2) Combined regular simultaneous +
* alternate trigger mode.
*/
#define ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_ALTERNATE_TRIG (0x02 << 0)
/** Dual modes (ADC1 + ADC2) Injected simultaneous mode only. */
#define ADC_CCR_MULTI_DUAL_INJECTED_SIMUL (0x05 << 0)
#define ADC_CCR_MULTI_DUAL_INJECTED_SIMUL (0x05 << 0)
/** Dual modes (ADC1 + ADC2) Regular simultaneous mode only. */
#define ADC_CCR_MULTI_DUAL_REGULAR_SIMUL (0x06 << 0)
#define ADC_CCR_MULTI_DUAL_REGULAR_SIMUL (0x06 << 0)
/** Dual modes (ADC1 + ADC2) Interleaved mode only. */
#define ADC_CCR_MULTI_DUAL_INTERLEAVED (0x07 << 0)
#define ADC_CCR_MULTI_DUAL_INTERLEAVED (0x07 << 0)
/** Dual modes (ADC1 + ADC2) Alternate trigger mode only. */
#define ADC_CCR_MULTI_DUAL_ALTERNATE_TRIG (0x09 << 0)
#define ADC_CCR_MULTI_DUAL_ALTERNATE_TRIG (0x09 << 0)
/* Triple modes (ADC1 + ADC2 + ADC3) */
/** Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + injected simultaneous mode */
#define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_INJECTED_SIMUL (0x11 << 0)
/** Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + alternate trigger mode. */
#define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_ALTERNATE_TRIG (0x12 << 0)
/**
* Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous +
* injected simultaneous mode.
*/
#define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_INJECTED_SIMUL (0x11 << 0)
/**
* Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous +
* alternate trigger mode.
*/
#define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_ALTERNATE_TRIG (0x12 << 0)
/** Triple modes (ADC1 + ADC2 + ADC3) Injected simultaneous mode only. */
#define ADC_CCR_MULTI_TRIPLE_INJECTED_SIMUL (0x15 << 0)
#define ADC_CCR_MULTI_TRIPLE_INJECTED_SIMUL (0x15 << 0)
/** Triple modes (ADC1 + ADC2 + ADC3) Regular simultaneous mode only. */
#define ADC_CCR_MULTI_TRIPLE_REGULAR_SIMUL (0x16 << 0)
#define ADC_CCR_MULTI_TRIPLE_REGULAR_SIMUL (0x16 << 0)
/** Triple modes (ADC1 + ADC2 + ADC3) Interleaved mode only. */
#define ADC_CCR_MULTI_TRIPLE_INTERLEAVED (0x17 << 0)
#define ADC_CCR_MULTI_TRIPLE_INTERLEAVED (0x17 << 0)
/** Triple modes (ADC1 + ADC2 + ADC3) Alternate trigger mode only. */
#define ADC_CCR_MULTI_TRIPLE_ALTERNATE_TRIG (0x19 << 0)
#define ADC_CCR_MULTI_TRIPLE_ALTERNATE_TRIG (0x19 << 0)
/**@}*/
#define ADC_CCR_MULTI_MASK (0x1f << 0)

3
include/libopencm3/stm32/f4/crc.h
View File

@@ -1,6 +1,7 @@
/** @defgroup crc_defines CRC Defines
@brief <b>libopencm3 Defined Constants and Types for the STM32F4xx CRC Generator </b>
@brief <b>libopencm3 Defined Constants and Types for the STM32F4xx CRC
Generator </b>
@ingroup STM32F4xx_defines

3
include/libopencm3/stm32/f4/iwdg.h
View File

@@ -1,6 +1,7 @@
/** @defgroup iwdg_defines IWDG Defines
@brief <b>Defined Constants and Types for the STM32F4xx Independent Watchdog Timer</b>
@brief <b>Defined Constants and Types for the STM32F4xx Independent Watchdog
Timer</b>
@ingroup STM32F4xx_defines

6
include/libopencm3/stm32/f4/rcc.h
View File

@@ -78,7 +78,7 @@
#define RCC_CR_HSIRDY (1 << 1)
#define RCC_CR_HSION (1 << 0)
/* --- RCC_PLLCFGR values ------------------------------------------------------- */
/* --- RCC_PLLCFGR values -------------------------------------------------- */
/* PLLQ: [27:24] */
#define RCC_PLLCFGR_PLLQ_SHIFT 24
@@ -343,8 +343,8 @@
#define RCC_AHB1LPENR_DMA1LPEN (1 << 21)
#define RCC_AHB1LPENR_BKPSRAMLPEN (1 << 18)
#define RCC_AHB1LPENR_SRAM2LPEN (1 << 17)
#define RCC_AHB1LPENR_SRAM1LPEN (1 << 16)
#define RCC_AHB1LPENR_FLITFLPEN (1 << 15)
#define RCC_AHB1LPENR_SRAM1LPEN (1 << 16)
#define RCC_AHB1LPENR_FLITFLPEN (1 << 15)
#define RCC_AHB1LPENR_CRCLPEN (1 << 12)
#define RCC_AHB1LPENR_IOPILPEN (1 << 8)
#define RCC_AHB1LPENR_IOPHLPEN (1 << 7)

3
include/libopencm3/stm32/hash.h
View File

@@ -22,5 +22,6 @@
#elif defined(STM32F4)
# include <libopencm3/stm32/f4/hash.h>
#else
# error "hash processor is supported only in stm32f21, stm32f41 and stm32f43 families."
# error "hash processor is supported only" \
"in stm32f21, stm32f41 and stm32f43 families."
#endif

3
include/libopencm3/stm32/l1/crc.h
View File

@@ -1,6 +1,7 @@
/** @defgroup crc_defines CRC Defines
@brief <b>libopencm3 Defined Constants and Types for the STM32L1xx CRC Generator </b>
@brief <b>libopencm3 Defined Constants and Types for the STM32L1xx CRC
Generator </b>
@ingroup STM32L1xx_defines

6
include/libopencm3/stm32/l1/dma.h
View File

@@ -6,8 +6,10 @@
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2011 Fergus Noble <fergusnoble@gmail.com>
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
@author @htmlonly &copy; @endhtmlonly 2011
Fergus Noble <fergusnoble@gmail.com>
@author @htmlonly &copy; @endhtmlonly 2012
Ken Sarkies <ksarkies@internode.on.net>
@date 18 October 2012

3
include/libopencm3/stm32/l1/flash.h
View File

@@ -20,7 +20,8 @@
*/
/*
* All extracted from PM0062 rev2, L15xx and L16xx Flash/EEPROM programming manual
* All extracted from PM0062 rev2, L15xx and L16xx Flash/EEPROM programming
* manual.
*/
#ifndef LIBOPENCM3_FLASH_H

2
include/libopencm3/stm32/l1/gpio.h
View File

@@ -171,7 +171,7 @@ LGPL License Terms @ref lgpl_license
#define GPIO_OTYPE_OD 0x1
/**@}*/
/* Output speed values */
/* Output speed values */
#define GPIO_OSPEED(n, speed) (speed << (2 * (n)))
#define GPIO_OSPEED_MASK(n) (0x3 << (2 * (n)))
/** @defgroup gpio_speed GPIO Output Pin Speed

3
include/libopencm3/stm32/l1/iwdg.h
View File

@@ -1,6 +1,7 @@
/** @defgroup iwdg_defines IWDG Defines
@brief <b>Defined Constants and Types for the STM32L1xx Independent Watchdog Timer</b>
@brief <b>Defined Constants and Types for the STM32L1xx Independent Watchdog
Timer</b>
@ingroup STM32L1xx_defines

9
include/libopencm3/stm32/l1/rcc.h
View File

@@ -6,9 +6,12 @@
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2009 Federico Ruiz-Ugalde \<memeruiz at gmail dot com\>
@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
@author @htmlonly &copy; @endhtmlonly 2012 Karl Palsson <karlp@tweak.net.au>
@author @htmlonly &copy; @endhtmlonly 2009
Federico Ruiz-Ugalde \<memeruiz at gmail dot com\>
@author @htmlonly &copy; @endhtmlonly 2009
Uwe Hermann <uwe@hermann-uwe.de>
@author @htmlonly &copy; @endhtmlonly 2012
Karl Palsson <karlp@tweak.net.au>
@date 11 November 2012

3
include/libopencm3/stm32/l1/timer.h
View File

@@ -51,7 +51,8 @@ LGPL License Terms @ref lgpl_license
/* ITR1_RMP */
/****************************************************************************/
/** @defgroup tim2_opt_trigger_remap TIM2_OR Timer 2 Option Register Internal Trigger 1 Remap
/** @defgroup tim2_opt_trigger_remap TIM2_OR Timer 2 Option Register Internal
Trigger 1 Remap
@ingroup timer_defines
@{*/

29
include/libopencm3/stm32/otg_fs.h
View File

@@ -39,7 +39,8 @@
#define OTG_FS_GCCFG MMIO32(USB_OTG_FS_BASE + 0x038)
#define OTG_FS_CID MMIO32(USB_OTG_FS_BASE + 0x03C)
#define OTG_FS_HPTXFSIZ MMIO32(USB_OTG_FS_BASE + 0x100)
#define OTG_FS_DIEPTXF(x) MMIO32(USB_OTG_FS_BASE + 0x104 + 4*(x-1))
#define OTG_FS_DIEPTXF(x) MMIO32(USB_OTG_FS_BASE + 0x104 + \
4*(x-1))
/* Host-mode Control and Status Registers */
#define OTG_FS_HCFG MMIO32(USB_OTG_FS_BASE + 0x400)
@@ -66,28 +67,36 @@
#define OTG_FS_DVBUSPULSE MMIO32(USB_OTG_FS_BASE + 0x82C)
#define OTG_FS_DIEPEMPMSK MMIO32(USB_OTG_FS_BASE + 0x834)
#define OTG_FS_DIEPCTL0 MMIO32(USB_OTG_FS_BASE + 0x900)
#define OTG_FS_DIEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0x900 + 0x20*(x))
#define OTG_FS_DIEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0x900 + \
0x20*(x))
#define OTG_FS_DOEPCTL0 MMIO32(USB_OTG_FS_BASE + 0xB00)
#define OTG_FS_DOEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0xB00 + 0x20*(x))
#define OTG_FS_DIEPINT(x) MMIO32(USB_OTG_FS_BASE + 0x908 + 0x20*(x))
#define OTG_FS_DOEPINT(x) MMIO32(USB_OTG_FS_BASE + 0xB08 + 0x20*(x))
#define OTG_FS_DOEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0xB00 + \
0x20*(x))
#define OTG_FS_DIEPINT(x) MMIO32(USB_OTG_FS_BASE + 0x908 + \
0x20*(x))
#define OTG_FS_DOEPINT(x) MMIO32(USB_OTG_FS_BASE + 0xB08 + \
0x20*(x))
#define OTG_FS_DIEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0x910)
#define OTG_FS_DOEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0xB10)
#define OTG_FS_DIEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0x910 + 0x20*(x))
#define OTG_FS_DTXFSTS(x) MMIO32(USB_OTG_FS_BASE + 0x918 + 0x20*(x))
#define OTG_FS_DOEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0xB10 + 0x20*(x))
#define OTG_FS_DIEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0x910 + \
0x20*(x))
#define OTG_FS_DTXFSTS(x) MMIO32(USB_OTG_FS_BASE + 0x918 + \
0x20*(x))
#define OTG_FS_DOEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0xB10 + \
0x20*(x))
/* Power and clock gating control and status register */
#define OTG_FS_PCGCCTL MMIO32(USB_OTG_FS_BASE + 0xE00)
/* Data FIFO */
#define OTG_FS_FIFO(x) ((volatile u32*)(USB_OTG_FS_BASE + (((x) + 1) << 12)))
#define OTG_FS_FIFO(x) ((volatile u32*)(USB_OTG_FS_BASE + \
(((x) + 1) << 12)))
/* Global CSRs */
/* OTG_FS USB control registers (OTG_HS_GOTGCTL) */
#define OTG_FS_GOTGCTL_BSVLD (1 << 19)
#define OTG_FS_GOTGCTL_ASVLD (1 << 18)
#define OTG_FS_GOTGCTL_DBCT (1 << 17)
#define OTG_FS_GOTGCTL_DBCT (1 << 17)
#define OTG_FS_GOTGCTL_CIDSTS (1 << 16)
#define OTG_FS_GOTGCTL_DHNPEN (1 << 11)
#define OTG_FS_GOTGCTL_HSHNPEN (1 << 10)

11
include/libopencm3/stm32/otg_hs.h
View File

@@ -135,21 +135,24 @@
#define OTG_HS_DOEPINT(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPINT(x))
#define OTG_HS_DIEPTSIZ0 MMIO32(USB_OTG_HS_BASE + OTG_DIEPTSIZ0)
#define OTG_HS_DOEPTSIZ0 MMIO32(USB_OTG_HS_BASE + OTG_DOEPTSIZ0)
#define OTG_HS_DIEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPTSIZ(x)))
#define OTG_HS_DIEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + \
OTG_DIEPTSIZ(x))
#define OTG_HS_DTXFSTS(x) MMIO32(USB_OTG_HS_BASE + OTG_DTXFSTS(x))
#define OTG_HS_DOEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPTSIZ(x))
#define OTG_HS_DOEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + \
OTG_DOEPTSIZ(x))
/* Power and clock gating control and status register */
#define OTG_HS_PCGCCTL MMIO32(USB_OTG_HS_BASE + OTG_PCGCCTL)
/* Data FIFO */
#define OTG_HS_FIFO(x) ((volatile u32*)(USB_OTG_HS_BASE + OTG_FIFO(x)))
#define OTG_HS_FIFO(x) ((volatile u32*)(USB_OTG_HS_BASE + \
OTG_FIFO(x)))
/* Global CSRs */
/* OTG_HS USB control registers (OTG_FS_GOTGCTL) */
#define OTG_HS_GOTGCTL_BSVLD (1 << 19)
#define OTG_HS_GOTGCTL_ASVLD (1 << 18)
#define OTG_HS_GOTGCTL_DBCT (1 << 17)
#define OTG_HS_GOTGCTL_DBCT (1 << 17)
#define OTG_HS_GOTGCTL_CIDSTS (1 << 16)
#define OTG_HS_GOTGCTL_DHNPEN (1 << 11)
#define OTG_HS_GOTGCTL_HSHNPEN (1 << 10)

2
include/libopencm3/stm32/syscfg.h
View File

@@ -22,7 +22,7 @@
#include <libopencm3/stm32/memorymap.h>
/* --- SYSCFG registers ------------------------------------------------------ */
/* --- SYSCFG registers ---------------------------------------------------- */
#define SYSCFG_MEMRM MMIO32(SYSCFG_BASE + 0x00)

2
include/libopencm3/stm32/tools.h
View File

@@ -59,6 +59,6 @@ do { \
toggle_mask ^= bit_selector; \
} \
SET_REG(REG, toggle_mask); \
} while(0)
} while (0)
#endif