First coarse run to fix coding style in locm3.

Added --terse and --mailback options to the make stylecheck target. It also does continue even if it enounters a possible error. We decided on two exceptions from the linux kernel coding standard: - Empty wait while loops may end with ; on the same line. - All blocks after while, if, for have to be in brackets even if they only contain one statement. Otherwise it is easy to introduce an error. Checkpatch needs to be adapted to reflect those changes.
2013-06-12 17:44:07 -07:00
parent 48e0f3326b
commit 7df63fcae0
147 changed files with 3323 additions and 2565 deletions
--- a/include/libopencm3/lpc43xx/creg.h
+++ b/include/libopencm3/lpc43xx/creg.h
@@ -1,6 +1,7 @@
 /** @defgroup creg_defines Configuration Registers Defines

-@brief <b>Defined Constants and Types for the LPC43xx Configuration Registers</b>
+@brief <b>Defined Constants and Types for the LPC43xx Configuration
+Registers</b>

@ingroup LPC43xx_defines

--- a/include/libopencm3/lpc43xx/gima.h
+++ b/include/libopencm3/lpc43xx/gima.h
@@ -1,6 +1,7 @@
 /** @defgroup gima_defines Global Input Multiplexer Array Defines

-@brief <b>Defined Constants and Types for the LPC43xx Global Input Multiplexer Array</b>
+@brief <b>Defined Constants and Types for the LPC43xx Global Input Multiplexer
+Array</b>

@ingroup LPC43xx_defines

--- a/include/libopencm3/lpc43xx/gpio.h
+++ b/include/libopencm3/lpc43xx/gpio.h
@@ -88,7 +88,7 @@ LGPL License Terms @ref lgpl_license

 /* --- GPIO registers ------------------------------------------------------ */

-//TODO byte/word access registers
+/* TODO byte/word access registers */

 /* GPIO data direction register (GPIOn_DIR) */
 #define GPIO_DIR(port)                  MMIO32(port + 0x00)
@@ -167,7 +167,7 @@ LGPL License Terms @ref lgpl_license
 #define GPIO6_NOT                       GPIO_NOT(GPIO6)
 #define GPIO7_NOT                       GPIO_NOT(GPIO7)

-//TODO interrupts
+/* TODO interrupts */

 BEGIN_DECLS

--- a/include/libopencm3/lpc43xx/i2s.h
+++ b/include/libopencm3/lpc43xx/i2s.h
@@ -45,7 +45,6 @@ LGPL License Terms @ref lgpl_license
 #define I2S0                            I2S0_BASE
 #define I2S1                            I2S1_BASE

-
 /* --- I2S registers ------------------------------------------------------- */

 /* I2S Digital Audio Output Register */
--- a/include/libopencm3/lpc43xx/ritimer.h
+++ b/include/libopencm3/lpc43xx/ritimer.h
@@ -1,6 +1,7 @@
 /** @defgroup ritimer_defines Repetitive Interrupt Timer Defines

-@brief <b>Defined Constants and Types for the LPC43xx Repetitive Interrupt Timer</b>
+@brief <b>Defined Constants and Types for the LPC43xx Repetitive Interrupt
+Timer</b>

@ingroup LPC43xx_defines

--- a/include/libopencm3/lpc43xx/scu.h
+++ b/include/libopencm3/lpc43xx/scu.h
@@ -406,12 +406,13 @@ LGPL License Terms @ref lgpl_license
 #define SCU_I2C0_NOMINAL    (SCU_SCL_EZI_EN | SCU_SDA_EZI_EN)

 /* Standard mode for I2C SCL/SDA Fast-mode Plus transmit */
-#define SCU_I2C0_FAST    (SCU_SCL_EFP | SCU_SCL_EHD | SCU_SCL_EZI_EN | SCU_SCL_ZIF_DIS \
-						SCU_SDA_EFP | SCU_SDA_EHD | SCU_SDA_EZI_EN)
+#define SCU_I2C0_FAST    (SCU_SCL_EFP | SCU_SCL_EHD | SCU_SCL_EZI_EN | \
+			  SCU_SCL_ZIF_DIS | SCU_SDA_EFP | SCU_SDA_EHD | \
+			  SCU_SDA_EZI_EN)

 /*
 * SCU PIN Normal Drive:
-* The pin configuration registers for normal-drive pins control the following pins:
+* The configuration registers for normal-drive pins control the following pins:
 *  - P0_0 and P0_1
 *  - P1_0 to P1_16 and P1_18 to P1_20
 *  - P2_0 to P2_2 and P2_6 to P2_13
@@ -429,7 +430,7 @@ LGPL License Terms @ref lgpl_license
 *  - PF_0 to PF_11
 *
 * Pin configuration registers for High-Drive pins.
-* The pin configuration registers for high-drive pins control the following pins:
+* The configuration registers for high-drive pins control the following pins:
 *  - P1_17
 *  - P2_3 to P2_5
 *  - P8_0 to P8_2
@@ -607,7 +608,9 @@ typedef enum {
 	PC_13  = (PIN_GROUPC+PIN13),
 	PC_14  = (PIN_GROUPC+PIN14),

-	/* Group Port D (seems not configurable through SCU, not defined in UM10503.pdf Rev.1, keep it here) */
+	/* Group Port D (seems not configurable through SCU, not defined in
+	 * UM10503.pdf Rev.1, keep it here)
+	 */
 	PD_0   = (PIN_GROUPD+PIN0),
 	PD_1   = (PIN_GROUPD+PIN1),
 	PD_2   = (PIN_GROUPD+PIN2),
@@ -700,21 +703,23 @@ typedef enum {
 /*
 * Select Slew Rate.
 * By Default=0 Slow.
-* Available to normal-drive pins and high-speed pins, reserved for high-drive pins.
+* Available to normal-drive and high-speed pins, reserved for high-drive pins.
 */
 #define SCU_CONF_EHS_FAST                (BIT5)

 /*
 * Input buffer enable.
 * By Default=0 Disable Input Buffer.
-* The input buffer is disabled by default at reset and must be enabled.
-* for receiving(in normal/highspeed-drive) or to transfer data from the I/O buffer to the pad(in high-drive pins).
+* The input buffer is disabled by default at reset and must be enabled for
+* receiving(in normal/highspeed-drive) or to transfer data from the I/O buffer
+* to the pad(in high-drive pins).
 * Available to normal-drive pins, high-drive pins, high-speed pins.
 */
 #define SCU_CONF_EZI_EN_IN_BUFFER        (BIT6)

 /*
-* Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.
+* Input glitch filter. Disable the input glitch filter for clocking signals
+* higher than 30 MHz.
 * Available to normal-drive pins, high-drive pins, high-speed pins.
 */
 #define SCU_CONF_ZIF_DIS_IN_GLITCH_FILT    (BIT7)
@@ -730,16 +735,39 @@ typedef enum {
 /* BIT10 to 31 are Reserved */

 /* Configuration for different I/O pins types */
-#define SCU_EMC_IO      (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER  | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
-#define SCU_LCD         (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER  | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
-#define SCU_CLK_IN      (SCU_CONF_EPD_EN_PULLDOWN  | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER  | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
-#define SCU_CLK_OUT     (SCU_CONF_EPD_EN_PULLDOWN  | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER  | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
+#define SCU_EMC_IO      (SCU_CONF_EPD_EN_PULLDOWN | \
+			 SCU_CONF_EHS_FAST | \
+			 SCU_CONF_EZI_EN_IN_BUFFER | \
+			 SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
+#define SCU_LCD         (SCU_CONF_EPUN_DIS_PULLUP | \
+			 SCU_CONF_EHS_FAST | \
+			 SCU_CONF_EZI_EN_IN_BUFFER | \
+			 SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
+#define SCU_CLK_IN      (SCU_CONF_EPD_EN_PULLDOWN | \
+			 SCU_CONF_EHS_FAST | \
+			 SCU_CONF_EZI_EN_IN_BUFFER | \
+			 SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
+#define SCU_CLK_OUT     (SCU_CONF_EPD_EN_PULLDOWN | \
+			 SCU_CONF_EHS_FAST | \
+			 SCU_CONF_EZI_EN_IN_BUFFER | \
+			 SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
 #define SCU_GPIO_PUP    (SCU_CONF_EZI_EN_IN_BUFFER)
-#define SCU_GPIO_PDN    (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EPD_EN_PULLDOWN  | SCU_CONF_EZI_EN_IN_BUFFER)
-#define SCU_GPIO_NOPULL (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EZI_EN_IN_BUFFER)
-#define SCU_GPIO_FAST   (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
-#define SCU_UART_RX_TX  (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EPD_EN_PULLDOWN  | SCU_CONF_EZI_EN_IN_BUFFER)
-#define SCU_SSP_IO      (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER  | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
+#define SCU_GPIO_PDN    (SCU_CONF_EPUN_DIS_PULLUP | \
+			 SCU_CONF_EPD_EN_PULLDOWN | \
+			 SCU_CONF_EZI_EN_IN_BUFFER)
+#define SCU_GPIO_NOPULL (SCU_CONF_EPUN_DIS_PULLUP | \
+			 SCU_CONF_EZI_EN_IN_BUFFER)
+#define SCU_GPIO_FAST   (SCU_CONF_EPUN_DIS_PULLUP | \
+			 SCU_CONF_EHS_FAST | \
+			 SCU_CONF_EZI_EN_IN_BUFFER | \
+			 SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
+#define SCU_UART_RX_TX  (SCU_CONF_EPUN_DIS_PULLUP | \
+			 SCU_CONF_EPD_EN_PULLDOWN | \
+			 SCU_CONF_EZI_EN_IN_BUFFER)
+#define SCU_SSP_IO      (SCU_CONF_EPUN_DIS_PULLUP | \
+			 SCU_CONF_EHS_FAST | \
+			 SCU_CONF_EZI_EN_IN_BUFFER | \
+			 SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)

 BEGIN_DECLS

--- a/include/libopencm3/lpc43xx/sgpio.h
+++ b/include/libopencm3/lpc43xx/sgpio.h
@@ -1,6 +1,7 @@
 /** @defgroup sgpio_defines Serial General Purpose I/O

-@brief <b>Defined Constants and Types for the LPC43xx Serial General Purpose I/O</b>
+@brief <b>Defined Constants and Types for the LPC43xx Serial General Purpose
+I/O</b>

@ingroup LPC43xx_defines

@@ -76,7 +77,8 @@ LGPL License Terms @ref lgpl_license
 #define SGPIO_OUT_MUX_CFG15             MMIO32(SGPIO_PORT_BASE + 0x3C)

 /* SGPIO multiplexer configuration registers (SGPIO_MUX_CFG0 to 15) */
-#define SGPIO_MUX_CFG(slice)            MMIO32(SGPIO_PORT_BASE + 0x40 + (slice * 0x04))
+#define SGPIO_MUX_CFG(slice)            MMIO32(SGPIO_PORT_BASE + 0x40 + \
+						(slice * 0x04))
 #define SGPIO_MUX_CFG0                  MMIO32(SGPIO_PORT_BASE + 0x40)
 #define SGPIO_MUX_CFG1                  MMIO32(SGPIO_PORT_BASE + 0x44)
 #define SGPIO_MUX_CFG2                  MMIO32(SGPIO_PORT_BASE + 0x48)
@@ -95,7 +97,8 @@ LGPL License Terms @ref lgpl_license
 #define SGPIO_MUX_CFG15                 MMIO32(SGPIO_PORT_BASE + 0x7C)

 /* Slice multiplexer configuration registers (SLICE_MUX_CFG0 to 15) */
-#define SGPIO_SLICE_MUX_CFG(slice)      MMIO32(SGPIO_PORT_BASE + 0x80 + (slice * 0x04))
+#define SGPIO_SLICE_MUX_CFG(slice)      MMIO32(SGPIO_PORT_BASE + 0x80 + \
+						(slice * 0x04))
 #define SGPIO_SLICE_MUX_CFG0            MMIO32(SGPIO_PORT_BASE + 0x80)
 #define SGPIO_SLICE_MUX_CFG1            MMIO32(SGPIO_PORT_BASE + 0x84)
 #define SGPIO_SLICE_MUX_CFG2            MMIO32(SGPIO_PORT_BASE + 0x88)
@@ -114,7 +117,8 @@ LGPL License Terms @ref lgpl_license
 #define SGPIO_SLICE_MUX_CFG15           MMIO32(SGPIO_PORT_BASE + 0xBC)

 /* Slice data registers (REG0 to 15) */
-#define SGPIO_REG(slice)                MMIO32(SGPIO_PORT_BASE + 0xC0 + (slice * 0x04))
+#define SGPIO_REG(slice)                MMIO32(SGPIO_PORT_BASE + 0xC0 + \
+						(slice * 0x04))
 #define SGPIO_REG0                      MMIO32(SGPIO_PORT_BASE + 0xC0)
 #define SGPIO_REG1                      MMIO32(SGPIO_PORT_BASE + 0xC4)
 #define SGPIO_REG2                      MMIO32(SGPIO_PORT_BASE + 0xC8)
@@ -133,7 +137,8 @@ LGPL License Terms @ref lgpl_license
 #define SGPIO_REG15                     MMIO32(SGPIO_PORT_BASE + 0xFC)

 /* Slice data shadow registers (REG_SS0 to 15) */
-#define SGPIO_REG_SS(slice)             MMIO32(SGPIO_PORT_BASE + 0x100 + (slice * 0x04))
+#define SGPIO_REG_SS(slice)             MMIO32(SGPIO_PORT_BASE + 0x100 + \
+						(slice * 0x04))
 #define SGPIO_REG_SS0                   MMIO32(SGPIO_PORT_BASE + 0x100)
 #define SGPIO_REG_SS1                   MMIO32(SGPIO_PORT_BASE + 0x104)
 #define SGPIO_REG_SS2                   MMIO32(SGPIO_PORT_BASE + 0x108)
@@ -152,7 +157,8 @@ LGPL License Terms @ref lgpl_license
 #define SGPIO_REG_SS15                  MMIO32(SGPIO_PORT_BASE + 0x13C)

 /* Reload registers (PRESET0 to 15) */
-#define SGPIO_PRESET(slice)             MMIO32(SGPIO_PORT_BASE + 0x140 + (slice * 0x04))
+#define SGPIO_PRESET(slice)             MMIO32(SGPIO_PORT_BASE + 0x140 + \
+						(slice * 0x04))
 #define SGPIO_PRESET0                   MMIO32(SGPIO_PORT_BASE + 0x140)
 #define SGPIO_PRESET1                   MMIO32(SGPIO_PORT_BASE + 0x144)
 #define SGPIO_PRESET2                   MMIO32(SGPIO_PORT_BASE + 0x148)
@@ -171,7 +177,8 @@ LGPL License Terms @ref lgpl_license
 #define SGPIO_PRESET15                  MMIO32(SGPIO_PORT_BASE + 0x17C)

 /* Down counter registers (COUNT0 to 15) */
-#define SGPIO_COUNT(slice)              MMIO32(SGPIO_PORT_BASE + 0x180 + (slice * 0x04))
+#define SGPIO_COUNT(slice)              MMIO32(SGPIO_PORT_BASE + 0x180 + \
+						(slice * 0x04))
 #define SGPIO_COUNT0                    MMIO32(SGPIO_PORT_BASE + 0x180)
 #define SGPIO_COUNT1                    MMIO32(SGPIO_PORT_BASE + 0x184)
 #define SGPIO_COUNT2                    MMIO32(SGPIO_PORT_BASE + 0x188)
@@ -190,7 +197,8 @@ LGPL License Terms @ref lgpl_license
 #define SGPIO_COUNT15                   MMIO32(SGPIO_PORT_BASE + 0x1BC)

 /* Position registers (POS0 to 15) */
-#define SGPIO_POS(slice)                MMIO32(SGPIO_PORT_BASE + 0x1C0 + (slice * 0x04))
+#define SGPIO_POS(slice)                MMIO32(SGPIO_PORT_BASE + 0x1C0 + \
+						(slice * 0x04))
 #define SGPIO_POS0                      MMIO32(SGPIO_PORT_BASE + 0x1C0)
 #define SGPIO_POS1                      MMIO32(SGPIO_PORT_BASE + 0x1C4)
 #define SGPIO_POS2                      MMIO32(SGPIO_PORT_BASE + 0x1C8)
--- a/include/libopencm3/lpc43xx/ssp.h
+++ b/include/libopencm3/lpc43xx/ssp.h
@@ -1,6 +1,7 @@
 /** @defgroup ssp_defines Synchronous Serial Port

-@brief <b>Defined Constants and Types for the LPC43xx Synchronous Serial Port</b>
+@brief <b>Defined Constants and Types for the LPC43xx Synchronous Serial
+Port</b>

@ingroup LPC43xx_defines

@@ -109,9 +110,9 @@ typedef enum {
 	SSP1_NUM = 0x1
 } ssp_num_t;

-/* 
-* SSP Control Register 0
-*/
+/*
+ * SSP Control Register 0
+ */
 /* SSP Data Size Bits 0 to 3 */
 typedef enum {
 	SSP_DATA_4BITS  = 0x3,
@@ -126,7 +127,7 @@ typedef enum {
 	SSP_DATA_13BITS = 0xC,
 	SSP_DATA_14BITS = 0xD,
 	SSP_DATA_15BITS = 0xE,
-	SSP_DATA_16BITS = 0xF 
+	SSP_DATA_16BITS = 0xF
 } ssp_datasize_t;

 /* SSP Frame Format/Type Bits 4 & 5 */
@@ -144,9 +145,9 @@ typedef enum {
 	SSP_CPOL_1_CPHA_1 = (BIT6|BIT7)
 } ssp_cpol_cpha_t;

-/* 
-* SSP Control Register 1
-*/
+/*
+ * SSP Control Register 1
+ */
 /* SSP Mode Bit0  */
 typedef enum {
 	SSP_MODE_NORMAL   = 0x0,
@@ -177,10 +178,11 @@ BEGIN_DECLS

 void ssp_disable(ssp_num_t ssp_num);

-/* 
+/*
 * SSP Init
 * clk_prescale shall be in range 2 to 254 (even number only).
- * Clock computation: PCLK / (CPSDVSR * [SCR+1]) => CPSDVSR=clk_prescale, SCR=serial_clock_rate
+ * Clock computation: PCLK / (CPSDVSR * [SCR+1]) => CPSDVSR=clk_prescale,
+ * SCR=serial_clock_rate
 */
 void ssp_init(ssp_num_t ssp_num,
 				ssp_datasize_t data_size,
--- a/include/libopencm3/lpc43xx/usb.h
+++ b/include/libopencm3/lpc43xx/usb.h
@@ -152,6 +152,6 @@


 /* --- USB1 registers ------------------------------------------------------ */
-//TODO
+/* TODO */

 #endif
--- a/include/libopencm3/lpc43xx/wwdt.h
+++ b/include/libopencm3/lpc43xx/wwdt.h
@@ -1,6 +1,7 @@
 /** @defgroup wwdt_defines Windowed Watchdog Timer

-@brief <b>Defined Constants and Types for the LPC43xx Windowed Watchdog Timer</b>
+@brief <b>Defined Constants and Types for the LPC43xx Windowed Watchdog
+Timer</b>

@ingroup LPC43xx_defines