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Merge branch 'master' into generalizations

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Conflicts:
	lib/lm3s/vector.c -- split out to lm3s/irq.h
	lib/stm32/f4/vector.c -- put the floating point initialization code into a function like in lpc43xx
This commit is contained in:
chrysn
2012-10-17 18:55:54 +02:00
parent a69d83d312 0a48344965
commit 7c33025c31
51 changed files with 3324 additions and 151 deletions
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482
include/libopencm3/lm3s/irq.h
View File

@@ -21,13 +21,485 @@
#ifndef LIBOPENCM3_LM3S_IRQ_H
#define LIBOPENCM3_LM3S_IRQ_H
/* TODO: Interrupt definitions */
#define IRQ_COUNT 0
#define IRQ_GPIOA 0
#define IRQ_GPIOB 1
#define IRQ_GPIOC 2
#define IRQ_GPIOD 3
#define IRQ_GPIOE 4
#define IRQ_UART0 5
#define IRQ_UART1 6
#define IRQ_SSI0 7
#define IRQ_I2C0 8
#define IRQ_PWM0_FAULT 9
#define IRQ_PWM0_0 10
#define IRQ_PWM0_1 11
#define IRQ_PWM0_2 12
#define IRQ_QEI0 13
#define IRQ_ADC0SS0 14
#define IRQ_ADC0SS1 15
#define IRQ_ADC0SS2 16
#define IRQ_ADC0SS3 17
#define IRQ_WATCHDOG 18
#define IRQ_TIMER0A 19
#define IRQ_TIMER0B 20
#define IRQ_TIMER1A 21
#define IRQ_TIMER1B 22
#define IRQ_TIMER2A 23
#define IRQ_TIMER2B 24
#define IRQ_COMP0 25
#define IRQ_COMP1 26
#define IRQ_COMP2 27
#define IRQ_SYSCTL 28
#define IRQ_FLASH 29
#define IRQ_GPIOF 30
#define IRQ_GPIOG 31
#define IRQ_GPIOH 32
#define IRQ_UART2 33
#define IRQ_SSI1 34
#define IRQ_TIMER3A 35
#define IRQ_TIMER3B 36
#define IRQ_I2C1 37
#define IRQ_QEI1 38
#define IRQ_CAN0 39
#define IRQ_CAN1 40
#define IRQ_CAN2 41
#define IRQ_ETH 42
#define IRQ_HIBERNATE 43
#define IRQ_USB0 44
#define IRQ_PWM0_3 45
#define IRQ_UDMA 46
#define IRQ_UDMAERR 47
#define IRQ_ADC1SS0 48
#define IRQ_ADC1SS1 49
#define IRQ_ADC1SS2 50
#define IRQ_ADC1SS3 51
#define IRQ_I2S0 52
#define IRQ_EPI0 53
#define IRQ_GPIOJ 54
#define IRQ_GPIOK 55
#define IRQ_GPIOL 56
#define IRQ_SSI2 57
#define IRQ_SSI3 58
#define IRQ_UART3 59
#define IRQ_UART4 60
#define IRQ_UART5 61
#define IRQ_UART6 62
#define IRQ_UART7 63
/* undefined: slot 64 */
/* undefined: slot 65 */
/* undefined: slot 66 */
/* undefined: slot 67 */
#define IRQ_I2C2 68
#define IRQ_I2C3 69
#define IRQ_TIMER4A 70
#define IRQ_TIMER4B 71
/* undefined: slot 72 */
/* undefined: slot 73 */
/* undefined: slot 74 */
/* undefined: slot 75 */
/* undefined: slot 76 */
/* undefined: slot 77 */
/* undefined: slot 78 */
/* undefined: slot 79 */
/* undefined: slot 80 */
/* undefined: slot 81 */
/* undefined: slot 82 */
/* undefined: slot 83 */
/* undefined: slot 84 */
/* undefined: slot 85 */
/* undefined: slot 86 */
/* undefined: slot 87 */
/* undefined: slot 88 */
/* undefined: slot 89 */
/* undefined: slot 90 */
/* undefined: slot 91 */
#define IRQ_TIMER5A 92
#define IRQ_TIMER5B 93
#define IRQ_WTIMER0A 94
#define IRQ_WTIMER0B 95
#define IRQ_WTIMER1A 96
#define IRQ_WTIMER1B 97
#define IRQ_WTIMER2A 98
#define IRQ_WTIMER2B 99
#define IRQ_WTIMER3A 100
#define IRQ_WTIMER3B 101
#define IRQ_WTIMER4A 102
#define IRQ_WTIMER4B 103
#define IRQ_WTIMER5A 104
#define IRQ_WTIMER5B 105
#define IRQ_SYSEXC 106
#define IRQ_PECI0 107
#define IRQ_LPC0 108
#define IRQ_I2C4 109
#define IRQ_I2C5 110
#define IRQ_GPIOM 111
#define IRQ_GPION 112
/* undefined: slot 113 */
#define IRQ_FAN0 114
/* undefined: slot 115 */
#define IRQ_GPIOP0 116
#define IRQ_GPIOP1 117
#define IRQ_GPIOP2 118
#define IRQ_GPIOP3 119
#define IRQ_GPIOP4 120
#define IRQ_GPIOP5 121
#define IRQ_GPIOP6 122
#define IRQ_GPIOP7 123
#define IRQ_GPIOQ0 124
#define IRQ_GPIOQ1 125
#define IRQ_GPIOQ2 126
#define IRQ_GPIOQ3 127
#define IRQ_GPIOQ4 128
#define IRQ_GPIOQ5 129
#define IRQ_GPIOQ6 130
#define IRQ_GPIOQ7 131
/* undefined: slot 132 */
/* undefined: slot 133 */
#define IRQ_PWM1_0 134
#define IRQ_PWM1_1 135
#define IRQ_PWM1_2 136
#define IRQ_PWM1_3 137
#define IRQ_PWM1_FAULT 138
/* TODO: Interrupt handler prototypes */
#define IRQ_COUNT 139
/* TODO: Interrupt handler weak aliases */
#define WEAK __attribute__ ((weak))
#define IRQ_HANDLERS
void WEAK gpioa_isr(void);
void WEAK gpiob_isr(void);
void WEAK gpioc_isr(void);
void WEAK gpiod_isr(void);
void WEAK gpioe_isr(void);
void WEAK uart0_isr(void);
void WEAK uart1_isr(void);
void WEAK ssi0_isr(void);
void WEAK i2c0_isr(void);
void WEAK pwm0_fault_isr(void);
void WEAK pwm0_0_isr(void);
void WEAK pwm0_1_isr(void);
void WEAK pwm0_2_isr(void);
void WEAK qei0_isr(void);
void WEAK adc0ss0_isr(void);
void WEAK adc0ss1_isr(void);
void WEAK adc0ss2_isr(void);
void WEAK adc0ss3_isr(void);
void WEAK watchdog_isr(void);
void WEAK timer0a_isr(void);
void WEAK timer0b_isr(void);
void WEAK timer1a_isr(void);
void WEAK timer1b_isr(void);
void WEAK timer2a_isr(void);
void WEAK timer2b_isr(void);
void WEAK comp0_isr(void);
void WEAK comp1_isr(void);
void WEAK comp2_isr(void);
void WEAK sysctl_isr(void);
void WEAK flash_isr(void);
void WEAK gpiof_isr(void);
void WEAK gpiog_isr(void);
void WEAK gpioh_isr(void);
void WEAK uart2_isr(void);
void WEAK ssi1_isr(void);
void WEAK timer3a_isr(void);
void WEAK timer3b_isr(void);
void WEAK i2c1_isr(void);
void WEAK qei1_isr(void);
void WEAK can0_isr(void);
void WEAK can1_isr(void);
void WEAK can2_isr(void);
void WEAK eth_isr(void);
void WEAK hibernate_isr(void);
void WEAK usb0_isr(void);
void WEAK pwm0_3_isr(void);
void WEAK udma_isr(void);
void WEAK udmaerr_isr(void);
void WEAK adc1ss0_isr(void);
void WEAK adc1ss1_isr(void);
void WEAK adc1ss2_isr(void);
void WEAK adc1ss3_isr(void);
void WEAK i2s0_isr(void);
void WEAK epi0_isr(void);
void WEAK gpioj_isr(void);
void WEAK gpiok_isr(void);
void WEAK gpiol_isr(void);
void WEAK ssi2_isr(void);
void WEAK ssi3_isr(void);
void WEAK uart3_isr(void);
void WEAK uart4_isr(void);
void WEAK uart5_isr(void);
void WEAK uart6_isr(void);
void WEAK uart7_isr(void);
void WEAK i2c2_isr(void);
void WEAK i2c3_isr(void);
void WEAK timer4a_isr(void);
void WEAK timer4b_isr(void);
void WEAK timer5a_isr(void);
void WEAK timer5b_isr(void);
void WEAK wtimer0a_isr(void);
void WEAK wtimer0b_isr(void);
void WEAK wtimer1a_isr(void);
void WEAK wtimer1b_isr(void);
void WEAK wtimer2a_isr(void);
void WEAK wtimer2b_isr(void);
void WEAK wtimer3a_isr(void);
void WEAK wtimer3b_isr(void);
void WEAK wtimer4a_isr(void);
void WEAK wtimer4b_isr(void);
void WEAK wtimer5a_isr(void);
void WEAK wtimer5b_isr(void);
void WEAK sysexc_isr(void);
void WEAK peci0_isr(void);
void WEAK lpc0_isr(void);
void WEAK i2c4_isr(void);
void WEAK i2c5_isr(void);
void WEAK gpiom_isr(void);
void WEAK gpion_isr(void);
void WEAK fan0_isr(void);
void WEAK gpiop0_isr(void);
void WEAK gpiop1_isr(void);
void WEAK gpiop2_isr(void);
void WEAK gpiop3_isr(void);
void WEAK gpiop4_isr(void);
void WEAK gpiop5_isr(void);
void WEAK gpiop6_isr(void);
void WEAK gpiop7_isr(void);
void WEAK gpioq0_isr(void);
void WEAK gpioq1_isr(void);
void WEAK gpioq2_isr(void);
void WEAK gpioq3_isr(void);
void WEAK gpioq4_isr(void);
void WEAK gpioq5_isr(void);
void WEAK gpioq6_isr(void);
void WEAK gpioq7_isr(void);
void WEAK pwm1_0_isr(void);
void WEAK pwm1_1_isr(void);
void WEAK pwm1_2_isr(void);
void WEAK pwm1_3_isr(void);
void WEAK pwm1_fault_isr(void);
#pragma weak gpioa_isr = blocking_handler
#pragma weak gpiob_isr = blocking_handler
#pragma weak gpioc_isr = blocking_handler
#pragma weak gpiod_isr = blocking_handler
#pragma weak gpioe_isr = blocking_handler
#pragma weak uart0_isr = blocking_handler
#pragma weak uart1_isr = blocking_handler
#pragma weak ssi0_isr = blocking_handler
#pragma weak i2c0_isr = blocking_handler
#pragma weak pwm0_fault_isr = blocking_handler
#pragma weak pwm0_0_isr = blocking_handler
#pragma weak pwm0_1_isr = blocking_handler
#pragma weak pwm0_2_isr = blocking_handler
#pragma weak qei0_isr = blocking_handler
#pragma weak adc0ss0_isr = blocking_handler
#pragma weak adc0ss1_isr = blocking_handler
#pragma weak adc0ss2_isr = blocking_handler
#pragma weak adc0ss3_isr = blocking_handler
#pragma weak watchdog_isr = blocking_handler
#pragma weak timer0a_isr = blocking_handler
#pragma weak timer0b_isr = blocking_handler
#pragma weak timer1a_isr = blocking_handler
#pragma weak timer1b_isr = blocking_handler
#pragma weak timer2a_isr = blocking_handler
#pragma weak timer2b_isr = blocking_handler
#pragma weak comp0_isr = blocking_handler
#pragma weak comp1_isr = blocking_handler
#pragma weak comp2_isr = blocking_handler
#pragma weak sysctl_isr = blocking_handler
#pragma weak flash_isr = blocking_handler
#pragma weak gpiof_isr = blocking_handler
#pragma weak gpiog_isr = blocking_handler
#pragma weak gpioh_isr = blocking_handler
#pragma weak uart2_isr = blocking_handler
#pragma weak ssi1_isr = blocking_handler
#pragma weak timer3a_isr = blocking_handler
#pragma weak timer3b_isr = blocking_handler
#pragma weak i2c1_isr = blocking_handler
#pragma weak qei1_isr = blocking_handler
#pragma weak can0_isr = blocking_handler
#pragma weak can1_isr = blocking_handler
#pragma weak can2_isr = blocking_handler
#pragma weak eth_isr = blocking_handler
#pragma weak hibernate_isr = blocking_handler
#pragma weak usb0_isr = blocking_handler
#pragma weak pwm0_3_isr = blocking_handler
#pragma weak udma_isr = blocking_handler
#pragma weak udmaerr_isr = blocking_handler
#pragma weak adc1ss0_isr = blocking_handler
#pragma weak adc1ss1_isr = blocking_handler
#pragma weak adc1ss2_isr = blocking_handler
#pragma weak adc1ss3_isr = blocking_handler
#pragma weak i2s0_isr = blocking_handler
#pragma weak epi0_isr = blocking_handler
#pragma weak gpioj_isr = blocking_handler
#pragma weak gpiok_isr = blocking_handler
#pragma weak gpiol_isr = blocking_handler
#pragma weak ssi2_isr = blocking_handler
#pragma weak ssi3_isr = blocking_handler
#pragma weak uart3_isr = blocking_handler
#pragma weak uart4_isr = blocking_handler
#pragma weak uart5_isr = blocking_handler
#pragma weak uart6_isr = blocking_handler
#pragma weak uart7_isr = blocking_handler
#pragma weak i2c2_isr = blocking_handler
#pragma weak i2c3_isr = blocking_handler
#pragma weak timer4a_isr = blocking_handler
#pragma weak timer4b_isr = blocking_handler
#pragma weak timer5a_isr = blocking_handler
#pragma weak timer5b_isr = blocking_handler
#pragma weak wtimer0a_isr = blocking_handler
#pragma weak wtimer0b_isr = blocking_handler
#pragma weak wtimer1a_isr = blocking_handler
#pragma weak wtimer1b_isr = blocking_handler
#pragma weak wtimer2a_isr = blocking_handler
#pragma weak wtimer2b_isr = blocking_handler
#pragma weak wtimer3a_isr = blocking_handler
#pragma weak wtimer3b_isr = blocking_handler
#pragma weak wtimer4a_isr = blocking_handler
#pragma weak wtimer4b_isr = blocking_handler
#pragma weak wtimer5a_isr = blocking_handler
#pragma weak wtimer5b_isr = blocking_handler
#pragma weak sysexc_isr = blocking_handler
#pragma weak peci0_isr = blocking_handler
#pragma weak lpc0_isr = blocking_handler
#pragma weak i2c4_isr = blocking_handler
#pragma weak i2c5_isr = blocking_handler
#pragma weak gpiom_isr = blocking_handler
#pragma weak gpion_isr = blocking_handler
#pragma weak fan0_isr = blocking_handler
#pragma weak gpiop0_isr = blocking_handler
#pragma weak gpiop1_isr = blocking_handler
#pragma weak gpiop2_isr = blocking_handler
#pragma weak gpiop3_isr = blocking_handler
#pragma weak gpiop4_isr = blocking_handler
#pragma weak gpiop5_isr = blocking_handler
#pragma weak gpiop6_isr = blocking_handler
#pragma weak gpiop7_isr = blocking_handler
#pragma weak gpioq0_isr = blocking_handler
#pragma weak gpioq1_isr = blocking_handler
#pragma weak gpioq2_isr = blocking_handler
#pragma weak gpioq3_isr = blocking_handler
#pragma weak gpioq4_isr = blocking_handler
#pragma weak gpioq5_isr = blocking_handler
#pragma weak gpioq6_isr = blocking_handler
#pragma weak gpioq7_isr = blocking_handler
#pragma weak pwm1_0_isr = blocking_handler
#pragma weak pwm1_1_isr = blocking_handler
#pragma weak pwm1_2_isr = blocking_handler
#pragma weak pwm1_3_isr = blocking_handler
#pragma weak pwm1_fault_isr = blocking_handler
#define IRQ_HANDLERS \
[IRQ_GPIOA] = gpioa_isr, \
[IRQ_GPIOB] = gpiob_isr, \
[IRQ_GPIOC] = gpioc_isr, \
[IRQ_GPIOD] = gpiod_isr, \
[IRQ_GPIOE] = gpioe_isr, \
[IRQ_UART0] = uart0_isr, \
[IRQ_UART1] = uart1_isr, \
[IRQ_SSI0] = ssi0_isr, \
[IRQ_I2C0] = i2c0_isr, \
[IRQ_PWM0_FAULT] = pwm0_fault_isr, \
[IRQ_PWM0_0] = pwm0_0_isr, \
[IRQ_PWM0_1] = pwm0_1_isr, \
[IRQ_PWM0_2] = pwm0_2_isr, \
[IRQ_QEI0] = qei0_isr, \
[IRQ_ADC0SS0] = adc0ss0_isr, \
[IRQ_ADC0SS1] = adc0ss1_isr, \
[IRQ_ADC0SS2] = adc0ss2_isr, \
[IRQ_ADC0SS3] = adc0ss3_isr, \
[IRQ_WATCHDOG] = watchdog_isr, \
[IRQ_TIMER0A] = timer0a_isr, \
[IRQ_TIMER0B] = timer0b_isr, \
[IRQ_TIMER1A] = timer1a_isr, \
[IRQ_TIMER1B] = timer1b_isr, \
[IRQ_TIMER2A] = timer2a_isr, \
[IRQ_TIMER2B] = timer2b_isr, \
[IRQ_COMP0] = comp0_isr, \
[IRQ_COMP1] = comp1_isr, \
[IRQ_COMP2] = comp2_isr, \
[IRQ_SYSCTL] = sysctl_isr, \
[IRQ_FLASH] = flash_isr, \
[IRQ_GPIOF] = gpiof_isr, \
[IRQ_GPIOG] = gpiog_isr, \
[IRQ_GPIOH] = gpioh_isr, \
[IRQ_UART2] = uart2_isr, \
[IRQ_SSI1] = ssi1_isr, \
[IRQ_TIMER3A] = timer3a_isr, \
[IRQ_TIMER3B] = timer3b_isr, \
[IRQ_I2C1] = i2c1_isr, \
[IRQ_QEI1] = qei1_isr, \
[IRQ_CAN0] = can0_isr, \
[IRQ_CAN1] = can1_isr, \
[IRQ_CAN2] = can2_isr, \
[IRQ_ETH] = eth_isr, \
[IRQ_HIBERNATE] = hibernate_isr, \
[IRQ_USB0] = usb0_isr, \
[IRQ_PWM0_3] = pwm0_3_isr, \
[IRQ_UDMA] = udma_isr, \
[IRQ_UDMAERR] = udmaerr_isr, \
[IRQ_ADC1SS0] = adc1ss0_isr, \
[IRQ_ADC1SS1] = adc1ss1_isr, \
[IRQ_ADC1SS2] = adc1ss2_isr, \
[IRQ_ADC1SS3] = adc1ss3_isr, \
[IRQ_I2S0] = i2s0_isr, \
[IRQ_EPI0] = epi0_isr, \
[IRQ_GPIOJ] = gpioj_isr, \
[IRQ_GPIOK] = gpiok_isr, \
[IRQ_GPIOL] = gpiol_isr, \
[IRQ_SSI2] = ssi2_isr, \
[IRQ_SSI3] = ssi3_isr, \
[IRQ_UART3] = uart3_isr, \
[IRQ_UART4] = uart4_isr, \
[IRQ_UART5] = uart5_isr, \
[IRQ_UART6] = uart6_isr, \
[IRQ_UART7] = uart7_isr, \
[IRQ_I2C2] = i2c2_isr, \
[IRQ_I2C3] = i2c3_isr, \
[IRQ_TIMER4A] = timer4a_isr, \
[IRQ_TIMER4B] = timer4b_isr, \
[IRQ_TIMER5A] = timer5a_isr, \
[IRQ_TIMER5B] = timer5b_isr, \
[IRQ_WTIMER0A] = wtimer0a_isr, \
[IRQ_WTIMER0B] = wtimer0b_isr, \
[IRQ_WTIMER1A] = wtimer1a_isr, \
[IRQ_WTIMER1B] = wtimer1b_isr, \
[IRQ_WTIMER2A] = wtimer2a_isr, \
[IRQ_WTIMER2B] = wtimer2b_isr, \
[IRQ_WTIMER3A] = wtimer3a_isr, \
[IRQ_WTIMER3B] = wtimer3b_isr, \
[IRQ_WTIMER4A] = wtimer4a_isr, \
[IRQ_WTIMER4B] = wtimer4b_isr, \
[IRQ_WTIMER5A] = wtimer5a_isr, \
[IRQ_WTIMER5B] = wtimer5b_isr, \
[IRQ_SYSEXC] = sysexc_isr, \
[IRQ_PECI0] = peci0_isr, \
[IRQ_LPC0] = lpc0_isr, \
[IRQ_I2C4] = i2c4_isr, \
[IRQ_I2C5] = i2c5_isr, \
[IRQ_GPIOM] = gpiom_isr, \
[IRQ_GPION] = gpion_isr, \
[IRQ_FAN0] = fan0_isr, \
[IRQ_GPIOP0] = gpiop0_isr, \
[IRQ_GPIOP1] = gpiop1_isr, \
[IRQ_GPIOP2] = gpiop2_isr, \
[IRQ_GPIOP3] = gpiop3_isr, \
[IRQ_GPIOP4] = gpiop4_isr, \
[IRQ_GPIOP5] = gpiop5_isr, \
[IRQ_GPIOP6] = gpiop6_isr, \
[IRQ_GPIOP7] = gpiop7_isr, \
[IRQ_GPIOQ0] = gpioq0_isr, \
[IRQ_GPIOQ1] = gpioq1_isr, \
[IRQ_GPIOQ2] = gpioq2_isr, \
[IRQ_GPIOQ3] = gpioq3_isr, \
[IRQ_GPIOQ4] = gpioq4_isr, \
[IRQ_GPIOQ5] = gpioq5_isr, \
[IRQ_GPIOQ6] = gpioq6_isr, \
[IRQ_GPIOQ7] = gpioq7_isr, \
[IRQ_PWM1_0] = pwm1_0_isr, \
[IRQ_PWM1_1] = pwm1_1_isr, \
[IRQ_PWM1_2] = pwm1_2_isr, \
[IRQ_PWM1_3] = pwm1_3_isr, \
[IRQ_PWM1_FAULT] = pwm1_fault_isr,
#endif

14
include/libopencm3/stm32/crc.h
View File

@@ -1,3 +1,17 @@
/** @defgroup crc_defines CRC Defines
@brief <b>libopencm3 Defined Constants and Types for the STM32F CRC Generator </b>
@ingroup STM32F_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
@date 18 August 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*

89
include/libopencm3/stm32/f1/adc.h
View File

@@ -252,7 +252,7 @@ LGPL License Terms @ref lgpl_license
#define ADC_CR1_DUALMOD_MASK (0xF << 16)
#define ADC_CR1_DUALMOD_SHIFT 16
/* DISCNUM[2:0]: Discontinous mode channel count. */
/* DISCNUM[2:0]: Discontinuous mode channel count. */
/****************************************************************************/
/** @defgroup adc_cr1_discnum ADC Number of channels in discontinuous mode.
@ingroup STM32F1xx_adc_defines
@@ -270,10 +270,10 @@ LGPL License Terms @ref lgpl_license
#define ADC_CR1_DISCNUM_MASK (0x7 << 13)
#define ADC_CR1_DISCNUM_SHIFT 13
/* JDISCEN: */ /** Discontinous mode on injected channels. */
/* JDISCEN: */ /** Discontinuous mode on injected channels. */
#define ADC_CR1_JDISCEN (1 << 12)
/* DISCEN: */ /** Discontinous mode on regular channels. */
/* DISCEN: */ /** Discontinuous mode on regular channels. */
#define ADC_CR1_DISCEN (1 << 11)
/* JAUTO: */ /** Automatic Injection Group conversion. */
@@ -557,7 +557,7 @@ LGPL License Terms @ref lgpl_license
/* --- ADC_SMPRx generic values -------------------------------------------- */
/****************************************************************************/
/* ADC_SMPRG ADC Sample Time Selection for Channels */
/** @defgroup adc_sample_rg ADC Sample Time Selection Generic
/** @defgroup adc_sample_rg ADC Sample Time Selection for All Channels
@ingroup STM32F1xx_adc_defines
@{*/
@@ -587,18 +587,11 @@ LGPL License Terms @ref lgpl_license
#define ADC_SQR1_SQ15_LSB 10
#define ADC_SQR1_SQ14_LSB 5
#define ADC_SQR1_SQ13_LSB 0
#define ADC_SQR1_L_MSK (0xf << ADC_L_LSB)
#define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQ16_LSB)
#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQ15_LSB)
#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQ14_LSB)
#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQ13_LSB)
/* TODO Fix error
#define ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB)
#define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQR1_SQ16_LSB)
#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQR1_SQ15_LSB)
#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQR1_SQ14_LSB)
#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQR1_SQ13_LSB)
*/
/* --- ADC_SQR2 values ----------------------------------------------------- */
@@ -608,20 +601,12 @@ LGPL License Terms @ref lgpl_license
#define ADC_SQR2_SQ9_LSB 10
#define ADC_SQR2_SQ8_LSB 5
#define ADC_SQR2_SQ7_LSB 0
#define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQ12_LSB)
#define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQ11_LSB)
#define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQ10_LSB)
#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQ9_LSB)
#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQ8_LSB)
#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQ7_LSB)
/* TODO Fix error
#define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQR2_SQ12_LSB)
#define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQR2_SQ11_LSB)
#define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQR2_SQ10_LSB)
#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQR2_SQ9_LSB)
#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQR2_SQ8_LSB)
#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQR2_SQ7_LSB)
*/
/* --- ADC_SQR3 values ----------------------------------------------------- */
@@ -631,20 +616,12 @@ LGPL License Terms @ref lgpl_license
#define ADC_SQR3_SQ3_LSB 10
#define ADC_SQR3_SQ2_LSB 5
#define ADC_SQR3_SQ1_LSB 0
#define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQ6_LSB)
#define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQ5_LSB)
#define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQ4_LSB)
#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQ3_LSB)
#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQ2_LSB)
#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQ1_LSB)
/* TODO Fix error
#define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQR3_SQ6_LSB)
#define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQR3_SQ5_LSB)
#define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQR3_SQ4_LSB)
#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQR3_SQ3_LSB)
#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQR3_SQ2_LSB)
#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQR3_SQ1_LSB)
*/
/* --- ADC_JSQR values ----------------------------------------------------- */
#define ADC_JSQR_JL_LSB 20
@@ -652,18 +629,24 @@ LGPL License Terms @ref lgpl_license
#define ADC_JSQR_JSQ3_LSB 10
#define ADC_JSQR_JSQ2_LSB 5
#define ADC_JSQR_JSQ1_LSB 0
#define ADC_JSQR_JL_MSK (0x2 << ADC_JL_LSB)
#define ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQ4_LSB)
#define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQ3_LSB)
#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQ2_LSB)
#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQ1_LSB)
/* TODO Fix error
/* JL[2:0]: Discontinous mode channel count injected channels. */
/****************************************************************************/
/** @defgroup adc_jsqr_jl ADC Number of channels in discontinuous mode fro injected channels.
@ingroup STM32F1xx_adc_defines
@{*/
#define ADC_JSQR_JL_1CHANNELS (0x0 << ADC_JSQR_JL_LSB)
#define ADC_JSQR_JL_2CHANNELS (0x1 << ADC_JSQR_JL_LSB)
#define ADC_JSQR_JL_3CHANNELS (0x2 << ADC_JSQR_JL_LSB)
#define ADC_JSQR_JL_4CHANNELS (0x3 << ADC_JSQR_JL_LSB)
/**@}*/
#define ADC_JSQR_JL_SHIFT 13
#define ADC_JSQR_JL_MSK (0x2 << ADC_JSQR_JL_LSB)
#define ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQR_JSQ4_LSB)
#define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQR_JSQ3_LSB)
#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQR_JSQ2_LSB)
#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQR_JSQ1_LSB)
*/
/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */
@@ -679,22 +662,31 @@ LGPL License Terms @ref lgpl_license
BEGIN_DECLS
void adc_power_on(u32 adc);
void adc_start_conversion_direct(u32 adc);
void adc_set_single_channel(u32 adc, u8 channel);
void adc_set_dual_mode(u32 mode);
bool adc_eoc(u32 adc);
bool adc_eoc_injected(u32 adc);
u32 adc_read_regular(u32 adc);
u32 adc_read_injected(u32 adc, u8 reg);
void adc_set_injected_offset(u32 adc, u8 reg, u32 offset);
void adc_enable_analog_watchdog_regular(u32 adc);
void adc_disable_analog_watchdog_regular(u32 adc);
void adc_enable_analog_watchdog_injected(u32 adc);
void adc_disable_analog_watchdog_injected(u32 adc);
void adc_enable_discontinous_mode_regular(u32 adc);
void adc_disable_discontinous_mode_regular(u32 adc);
void adc_enable_discontinous_mode_injected(u32 adc);
void adc_disable_discontinous_mode_injected(u32 adc);
void adc_enable_discontinuous_mode_regular(u32 adc, u8 length);
void adc_disable_discontinuous_mode_regular(u32 adc);
void adc_enable_discontinuous_mode_injected(u32 adc);
void adc_disable_discontinuous_mode_injected(u32 adc);
void adc_enable_automatic_injected_group_conversion(u32 adc);
void adc_disable_automatic_injected_group_conversion(u32 adc);
void adc_enable_analog_watchdog_on_all_channels(u32 adc);
void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel);
void adc_enable_scan_mode(u32 adc);
void adc_disable_scan_mode(u32 adc);
void adc_enable_jeoc_interrupt(u32 adc);
void adc_disable_jeoc_interrupt(u32 adc);
void adc_enable_eoc_interrupt_injected(u32 adc);
void adc_disable_eoc_interrupt_injected(u32 adc);
void adc_enable_awd_interrupt(u32 adc);
void adc_disable_awd_interrupt(u32 adc);
void adc_enable_eoc_interrupt(u32 adc);
@@ -713,17 +705,28 @@ void adc_enable_dma(u32 adc);
void adc_disable_dma(u32 adc);
void adc_reset_calibration(u32 adc);
void adc_calibration(u32 adc);
void adc_set_continous_conversion_mode(u32 adc);
void adc_set_continuous_conversion_mode(u32 adc);
void adc_set_single_conversion_mode(u32 adc);
#ifdef __GNUC__
void adc_on(u32 adc) __attribute__ ((deprecated ("will be removed in the first release")));
#else
void adc_on(u32 adc);
#endif
void adc_off(u32 adc);
void adc_set_conversion_time(u32 adc, u8 channel, u8 time);
void adc_set_conversion_time_on_all_channels(u32 adc, u8 time);
void adc_set_sample_time(u32 adc, u8 channel, u8 time);
void adc_set_sample_time_on_all_channels(u32 adc, u8 time);
void adc_set_watchdog_high_threshold(u32 adc, u16 threshold);
void adc_set_watchdog_low_threshold(u32 adc, u16 threshold);
void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]);
void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]);
#ifdef __GNUC__
void adc_set_continous_conversion_mode(u32 adc) __attribute__ ((deprecated ("change to adc_set_continuous_conversion_mode")));
void adc_set_conversion_time(u32 adc, u8 channel, u8 time) __attribute__ ((deprecated ("change to adc_set_sample_time")));
void adc_set_conversion_time_on_all_channels(u32 adc, u8 time) __attribute__ ((deprecated ("change to adc_set_sample_time_on_all_channels")));
void adc_enable_jeoc_interrupt(u32 adc) __attribute__ ((deprecated ("change to adc_enable_eoc_interrupt_injected")));
void adc_disable_jeoc_interrupt(u32 adc) __attribute__ ((deprecated ("change to adc_disable_eoc_interrupt_injected")));
#endif
END_DECLS
#endif

61
include/libopencm3/stm32/f4/rng.h Normal file
View File

@@ -0,0 +1,61 @@
/*
* This file is part of the libopencm3 project.
*
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_RNG_H
#define LIBOPENCM3_RNG_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
/* --- Random number generator registers ----------------------------------- */
/* Control register */
#define RNG_CR MMIO32(RNG_BASE + 0x00)
/* Status register */
#define RNG_SR MMIO32(RNG_BASE + 0x04)
/* Data register */
#define RNG_DR MMIO32(RNG_BASE + 0x08)
/* --- RNG_CR values ------------------------------------------------------- */
/* RNG ENABLE */
#define RNG_CR_EN (1 << 2)
/* RNG interupt enable */
#define RNG_CR_IE (1 << 3)
/* --- RNG_SR values ------------------------------------------------------- */
/* Data ready */
#define RNG_SR_DRDY (1 << 0)
/* Clock error current status */
#define RNG_SR_CECS (1 << 1)
/* Seed error current status */
#define RNG_SR_SECS (1 << 2)
/* Clock error interup status */
#define RNG_SR_CEIS (1 << 5)
/* Seed error interup status */
#define RNG_SR_SEIS (1 << 6)
#endif

69
include/libopencm3/stm32/f4/scb.h
View File

@@ -72,6 +72,63 @@
/* AFSR: Auxiliary Fault Status Register */
#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
/* ID_PFR0: Processor Feature Register 0 */
#define SCB_ID_PFR0 MMIO32(SCB_BASE + 0x40)
/* ID_PFR1: Processor Feature Register 1 */
#define SCB_ID_PFR1 MMIO32(SCB_BASE + 0x44)
/* ID_DFR0: Debug Features Register 0 */
#define SCB_ID_DFR0 MMIO32(SCB_BASE + 0x48)
/* ID_AFR0: Auxiliary Features Register 0 */
#define SCB_ID_AFR0 MMIO32(SCB_BASE + 0x4C)
/* ID_MMFR0: Memory Model Feature Register 0 */
#define SCB_ID_MMFR0 MMIO32(SCB_BASE + 0x50)
/* ID_MMFR1: Memory Model Feature Register 1 */
#define SCB_ID_MMFR1 MMIO32(SCB_BASE + 0x54)
/* ID_MMFR2: Memory Model Feature Register 2 */
#define SCB_ID_MMFR2 MMIO32(SCB_BASE + 0x58)
/* ID_MMFR3: Memory Model Feature Register 3 */
#define SCB_ID_MMFR3 MMIO32(SCB_BASE + 0x5C)
/* ID_ISAR0: Instruction Set Attributes Register 0 */
#define SCB_ID_ISAR0 MMIO32(SCB_BASE + 0x60)
/* ID_ISAR1: Instruction Set Attributes Register 1 */
#define SCB_ID_ISAR1 MMIO32(SCB_BASE + 0x64)
/* ID_ISAR2: Instruction Set Attributes Register 2 */
#define SCB_ID_ISAR2 MMIO32(SCB_BASE + 0x68)
/* ID_ISAR3: Instruction Set Attributes Register 3 */
#define SCB_ID_ISAR3 MMIO32(SCB_BASE + 0x6C)
/* ID_ISAR4: Instruction Set Attributes Register 4 */
#define SCB_ID_ISAR4 MMIO32(SCB_BASE + 0x70)
/* CPACR: Coprocessor Access Control Register */
#define SCB_CPACR MMIO32(SCB_BASE + 0x88)
/* FPCCR: Floating-Point Context Control Register */
#define SCB_FPCCR MMIO32(SCB_BASE + 0x234)
/* FPCAR: Floating-Point Context Address Register */
#define SCB_FPCAR MMIO32(SCB_BASE + 0x238)
/* FPDSCR: Floating-Point Default Status Control Register */
#define SCB_FPDSCR MMIO32(SCB_BASE + 0x23C)
/* MVFR0: Media and Floating-Point Feature Register 0 */
#define SCB_MVFR0 MMIO32(SCB_BASE + 0x240)
/* MVFR1: Media and Floating-Point Feature Register 1 */
#define SCB_MVFR1 MMIO32(SCB_BASE + 0x244)
/* --- SCB values ---------------------------------------------------------- */
/* --- SCB_CPUID values ---------------------------------------------------- */
@@ -292,6 +349,18 @@
/* BFAR [31:0]: Bus fault address */
/* --- SCB_CPACR values ---------------------------------------------------- */
/* CPACR CPn: Access privileges values */
#define SCB_CPACR_NONE 0 /* Access denied */
#define SCB_CPACR_PRIV 1 /* Privileged access only */
#define SCB_CPACR_FULL 3 /* Full access */
/* CPACR [20:21]: Access privileges for coprocessor 10 */
#define SCB_CPACR_CP10 (1 << 20)
/* CPACR [22:23]: Access privileges for coprocessor 11 */
#define SCB_CPACR_CP11 (1 << 22)
/* --- SCB functions ------------------------------------------------------- */
BEGIN_DECLS

38
include/libopencm3/stm32/i2c.h
View File

@@ -1,3 +1,19 @@
/** @defgroup i2c_defines I2C Defines
@ingroup STM32F_defines
@brief <b>libopencm3 Defined Constants and Types for the STM32 I2C </b>
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
@date 12 October 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
@@ -23,11 +39,19 @@
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
/**@{*/
/* --- Convenience macros -------------------------------------------------- */
/* I2C register base adresses (for convenience) */
/****************************************************************************/
/** @defgroup i2c_reg_base I2C register base address
@ingroup i2c_defines
@{*/
#define I2C1 I2C1_BASE
#define I2C2 I2C2_BASE
/**@}*/
/* --- I2C registers ------------------------------------------------------- */
@@ -146,6 +170,11 @@
/* Note: Bits [7:6] are reserved, and forced to 0 by hardware. */
/* FREQ[5:0]: Peripheral clock frequency (valid values: 2-36 MHz) */
/****************************************************************************/
/** @defgroup i2c_clock I2C clock frequency settings
@ingroup i2c_defines
@{*/
#define I2C_CR2_FREQ_2MHZ 0x02
#define I2C_CR2_FREQ_3MHZ 0x03
#define I2C_CR2_FREQ_4MHZ 0x04
@@ -181,6 +210,7 @@
#define I2C_CR2_FREQ_34MHZ 0x22
#define I2C_CR2_FREQ_35MHZ 0x23
#define I2C_CR2_FREQ_36MHZ 0x24
/**@}*/
/* --- I2Cx_OAR1 values ---------------------------------------------------- */
@@ -311,8 +341,14 @@
/* --- I2C const definitions ----------------------------------------------- */
/****************************************************************************/
/** @defgroup i2c_rw I2C Read/Write bit
@ingroup i2c_defines
@{*/
#define I2C_WRITE 0
#define I2C_READ 1
/**@}*/
/* --- I2C funtion prototypes----------------------------------------------- */
@@ -336,3 +372,5 @@ void i2c_send_data(u32 i2c, u8 data);
END_DECLS
#endif
/**@}*/

62
include/libopencm3/stm32/spi.h
View File

@@ -1,3 +1,19 @@
/** @defgroup spi_defines SPI Defines
@ingroup STM32F_defines
@brief <b>libopencm3 Defined Constants and Types for the STM32 SPI </b>
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
@date 12 October 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
@@ -23,13 +39,21 @@
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
/**@{*/
/* Registers can be accessed as 16bit or 32bit values. */
/* --- Convenience macros -------------------------------------------------- */
/****************************************************************************/
/** @defgroup spi_reg_base SPI Register base address
@ingroup spi_defines
@{*/
#define SPI1 SPI1_BASE
#define SPI2 SPI2_I2S_BASE
#define SPI3 SPI3_I2S_BASE
/**@}*/
/* --- SPI registers ------------------------------------------------------- */
@@ -110,8 +134,14 @@
#define SPI_CR1_CRCNEXT (1 << 12)
/* DFF: Data frame format */
/****************************************************************************/
/** @defgroup spi_dff SPI data frame format
@ingroup spi_defines
@{*/
#define SPI_CR1_DFF_8BIT (0 << 11)
#define SPI_CR1_DFF_16BIT (1 << 11)
/**@}*/
#define SPI_CR1_DFF (1 << 11)
/* RXONLY: Receive only */
@@ -124,13 +154,24 @@
#define SPI_CR1_SSI (1 << 8)
/* LSBFIRST: Frame format */
/****************************************************************************/
/** @defgroup spi_lsbfirst SPI lsb/msb first
@ingroup spi_defines
@{*/
#define SPI_CR1_MSBFIRST (0 << 7)
#define SPI_CR1_LSBFIRST (1 << 7)
/**@}*/
/* SPE: SPI enable */
#define SPI_CR1_SPE (1 << 6)
/* BR[2:0]: Baud rate control */
/****************************************************************************/
/** @defgroup spi_baudrate SPI peripheral baud rates
@ingroup spi_defines
@{*/
#define SPI_CR1_BAUDRATE_FPCLK_DIV_2 (0x00 << 3)
#define SPI_CR1_BAUDRATE_FPCLK_DIV_4 (0x01 << 3)
#define SPI_CR1_BAUDRATE_FPCLK_DIV_8 (0x02 << 3)
@@ -139,6 +180,12 @@
#define SPI_CR1_BAUDRATE_FPCLK_DIV_64 (0x05 << 3)
#define SPI_CR1_BAUDRATE_FPCLK_DIV_128 (0x06 << 3)
#define SPI_CR1_BAUDRATE_FPCLK_DIV_256 (0x07 << 3)
/**@}*/
/****************************************************************************/
/** @defgroup spi_br_pre SPI peripheral baud rate prescale values
@ingroup spi_defines
@{*/
#define SPI_CR1_BR_FPCLK_DIV_2 0x0
#define SPI_CR1_BR_FPCLK_DIV_4 0x1
#define SPI_CR1_BR_FPCLK_DIV_8 0x2
@@ -147,18 +194,31 @@
#define SPI_CR1_BR_FPCLK_DIV_64 0x5
#define SPI_CR1_BR_FPCLK_DIV_128 0x6
#define SPI_CR1_BR_FPCLK_DIV_256 0x7
/**@}*/
/* MSTR: Master selection */
#define SPI_CR1_MSTR (1 << 2)
/* CPOL: Clock polarity */
/****************************************************************************/
/** @defgroup spi_cpol SPI clock polarity
@ingroup spi_defines
@{*/
#define SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE (0 << 1)
#define SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE (1 << 1)
/**@}*/
#define SPI_CR1_CPOL (1 << 1)
/* CPHA: Clock phase */
/****************************************************************************/
/** @defgroup spi_cpha SPI clock phase
@ingroup spi_defines
@{*/
#define SPI_CR1_CPHA_CLK_TRANSITION_1 (0 << 0)
#define SPI_CR1_CPHA_CLK_TRANSITION_2 (1 << 0)
/**@}*/
#define SPI_CR1_CPHA (1 << 0)
/* --- SPI_CR2 values ------------------------------------------------------ */
@@ -347,4 +407,6 @@ void spi_disable_rx_dma(u32 spi);
END_DECLS
/**@}*/
#endif

28
include/libopencm3/stm32/timer.h
View File

@@ -1,6 +1,6 @@
/** @defgroup STM32F_tim_defines Timers Defines
@brief <b>libopencm3 Defined Constants and Types for the STM32F1xx Timers</b>
@brief <b>libopencm3 Defined Constants and Types for the STM32 Timers</b>
@ingroup STM32F_defines
@@ -44,7 +44,7 @@ LGPL License Terms @ref lgpl_license
/* Timer register base adresses (for convenience) */
/****************************************************************************/
/** @defgroup tim_reg_base Timer register base addresses
@ingroup STM32F1xx_tim_defines
@ingroup STM32F_tim_defines
@{*/
#define TIM1 TIM1_BASE
@@ -251,7 +251,7 @@ LGPL License Terms @ref lgpl_license
/****************************************************************************/
/** @defgroup tim_x_cr1_cdr TIMx_CR1 CKD[1:0] Clock Division Ratio
@ingroup STM32F1xx_tim_defines
@ingroup STM32F_tim_defines
@{*/
/* CKD[1:0]: Clock division */
@@ -267,7 +267,7 @@ LGPL License Terms @ref lgpl_license
/* CMS[1:0]: Center-aligned mode selection */
/****************************************************************************/
/** @defgroup tim_x_cr1_cms TIMx_CR1 CMS[1:0]: Center-aligned Mode Selection
@ingroup STM32F1xx_tim_defines
@ingroup STM32F_tim_defines
@{*/
#define TIM_CR1_CMS_EDGE (0x0 << 5)
@@ -280,7 +280,7 @@ LGPL License Terms @ref lgpl_license
/* DIR: Direction */
/****************************************************************************/
/** @defgroup tim_x_cr1_dir TIMx_CR1 DIR: Direction
@ingroup STM32F1xx_tim_defines
@ingroup STM32F_tim_defines
@{*/
#define TIM_CR1_DIR_UP (0 << 4)
@@ -303,7 +303,7 @@ LGPL License Terms @ref lgpl_license
/****************************************************************************/
/** @defgroup tim_x_cr2_ois TIMx_CR2_OIS: Force Output Idle State Control Values
@ingroup STM32F1xx_tim_defines
@ingroup STM32F_tim_defines
@{*/
/* OIS4:*//** Output idle state 4 (OC4 output) */
@@ -335,7 +335,7 @@ LGPL License Terms @ref lgpl_license
/* MMS[2:0]: Master mode selection */
/****************************************************************************/
/** @defgroup tim_mastermode TIMx_CR2 MMS[6:4]: Master Mode Selection
@ingroup STM32F1xx_tim_defines
@ingroup STM32F_tim_defines
@{*/
#define TIM_CR2_MMS_RESET (0x0 << 4)
@@ -397,7 +397,7 @@ LGPL License Terms @ref lgpl_license
/* TS[2:0]: Trigger selection */
/** @defgroup tim_ts TS Trigger selection
@ingroup STM32F1xx_tim_defines
@ingroup STM32F_tim_defines
@{*/
/** Internal Trigger 0 (ITR0) */
@@ -421,7 +421,7 @@ LGPL License Terms @ref lgpl_license
/* SMS[2:0]: Slave mode selection */
/** @defgroup tim_sms SMS Slave mode selection
@ingroup STM32F1xx_tim_defines
@ingroup STM32F_tim_defines
@{*/
/** Slave mode disabled */
@@ -451,7 +451,7 @@ and generates an update of the registers. */
/****************************************************************************/
/** @defgroup tim_irq_enable TIMx_DIER Timer DMA and Interrupt Enable Values
@ingroup STM32F1xx_tim_defines
@ingroup STM32F_tim_defines
@{*/
/* TDE:*//** Trigger DMA request enable */
@@ -503,7 +503,7 @@ and generates an update of the registers. */
/* --- TIMx_SR values ------------------------------------------------------ */
/****************************************************************************/
/** @defgroup tim_sr_values TIMx_SR Timer Status Register Flags
@ingroup STM32F1xx_tim_defines
@ingroup STM32F_tim_defines
@{*/
@@ -548,7 +548,7 @@ and generates an update of the registers. */
/****************************************************************************/
/** @defgroup tim_event_gen TIMx_EGR Timer Event Generator Values
@ingroup STM32F1xx_tim_defines
@ingroup STM32F_tim_defines
@{*/
@@ -908,7 +908,7 @@ and generates an update of the registers. */
/* LOCK[1:0]: Lock configuration */
/****************************************************************************/
/** @defgroup tim_lock TIM_BDTR_LOCK Timer Lock Values
@ingroup STM32F1xx_tim_defines
@ingroup STM32F_tim_defines
@{*/
#define TIM_BDTR_LOCK_OFF (0x0 << 8)
@@ -1028,6 +1028,7 @@ BEGIN_DECLS
void timer_reset(u32 timer_peripheral);
void timer_enable_irq(u32 timer_peripheral, u32 irq);
void timer_disable_irq(u32 timer_peripheral, u32 irq);
bool timer_return_interrupt_source(u32 timer_peripheral, u32 flag);
bool timer_get_flag(u32 timer_peripheral, u32 flag);
void timer_clear_flag(u32 timer_peripheral, u32 flag);
void timer_set_mode(u32 timer_peripheral, u32 clock_div,
@@ -1090,6 +1091,7 @@ void timer_set_break_lock(u32 timer_peripheral, u32 lock);
void timer_set_deadtime(u32 timer_peripheral, u32 deadtime);
void timer_generate_event(u32 timer_peripheral, u32 event);
u32 timer_get_counter(u32 timer_peripheral);
void timer_set_counter(u32 timer_peripheral, u32 count);
void timer_ic_set_filter(u32 timer, enum tim_ic_id ic, enum tim_ic_filter flt);
void timer_ic_set_prescaler(u32 timer, enum tim_ic_id ic, enum tim_ic_psc psc);

83
include/libopencm3/stm32/usart.h
View File

@@ -1,3 +1,18 @@
/** @defgroup STM32F_usart_defines USART Defines
@brief <b>libopencm3 Defined Constants and Types for the STM32F Digital to Analog Converter </b>
@ingroup STM32F_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
@date 1 September 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
@@ -17,6 +32,8 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#ifndef LIBOPENCM3_USART_H
#define LIBOPENCM3_USART_H
@@ -25,9 +42,15 @@
/* --- Convenience macros -------------------------------------------------- */
/****************************************************************************/
/** @defgroup usart_reg_base USART register base addresses
@ingroup STM32F_usart_defines
@{*/
#define USART1 USART1_BASE
#define USART2 USART2_BASE
#define USART3 USART3_BASE
/**@}*/
#define UART4 UART4_BASE
#define UART5 UART5_BASE
@@ -90,37 +113,43 @@
#define UART5_GTPR USART_GTPR(UART5_BASE)
/* --- USART_SR values ----------------------------------------------------- */
/****************************************************************************/
/** @defgroup usart_sr_flags USART Status register Flags
@ingroup STM32F_usart_defines
/* CTS: CTS flag */
/* Note: N/A on UART4/5 */
@{*/
/** CTS: CTS flag */
/** @note: undefined on UART4 and UART5 */
#define USART_SR_CTS (1 << 9)
/* LBD: LIN break detection flag */
/** LBD: LIN break detection flag */
#define USART_SR_LBD (1 << 8)
/* TXE: Transmit data buffer empty */
/** TXE: Transmit data buffer empty */
#define USART_SR_TXE (1 << 7)
/* TC: Transmission complete */
/** TC: Transmission complete */
#define USART_SR_TC (1 << 6)
/* RXNE: Read data register not empty */
/** RXNE: Read data register not empty */
#define USART_SR_RXNE (1 << 5)
/* IDLE: Idle line detected */
/** IDLE: Idle line detected */
#define USART_SR_IDLE (1 << 4)
/* ORE: Overrun error */
/** ORE: Overrun error */
#define USART_SR_ORE (1 << 3)
/* NE: Noise error flag */
/** NE: Noise error flag */
#define USART_SR_NE (1 << 2)
/* FE: Framing error */
/** FE: Framing error */
#define USART_SR_FE (1 << 1)
/* PE: Parity error */
/** PE: Parity error */
#define USART_SR_PE (1 << 0)
/**@}*/
/* --- USART_DR values ----------------------------------------------------- */
@@ -269,27 +298,51 @@
/* --- Convenience defines ------------------------------------------------- */
/* CR1_PCE / CR1_PS combined values */
/****************************************************************************/
/** @defgroup usart_cr1_parity USART Parity Selection
@ingroup STM32F_usart_defines
@{*/
#define USART_PARITY_NONE 0x00
#define USART_PARITY_EVEN USART_CR1_PCE
#define USART_PARITY_ODD (USART_CR1_PS | USART_CR1_PCE)
/**@}*/
#define USART_PARITY_MASK (USART_CR1_PS | USART_CR1_PCE)
/* CR1_TE/CR1_RE combined values */
/****************************************************************************/
/** @defgroup usart_cr1_mode USART Tx/Rx Mode Selection
@ingroup STM32F_usart_defines
@{*/
#define USART_MODE_RX USART_CR1_RE
#define USART_MODE_TX USART_CR1_TE
#define USART_MODE_TX_RX (USART_CR1_RE | USART_CR1_TE)
/**@}*/
#define USART_MODE_MASK (USART_CR1_RE | USART_CR1_TE)
/****************************************************************************/
/** @defgroup usart_cr2_stopbits USART Stop Bit Selection
@ingroup STM32F_usart_defines
@{*/
#define USART_STOPBITS_1 USART_CR2_STOPBITS_1 /* 1 stop bit */
#define USART_STOPBITS_0_5 USART_CR2_STOPBITS_0_5 /* 0.5 stop bits */
#define USART_STOPBITS_2 USART_CR2_STOPBITS_2 /* 2 stop bits */
#define USART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5 /* 1.5 stop bits */
/**@}*/
/* CR3_CTSE/CR3_RTSE combined values */
/****************************************************************************/
/** @defgroup usart_cr3_flowcontrol USART Hardware Flow Control Selection
@ingroup STM32F_usart_defines
@{*/
#define USART_FLOWCONTROL_NONE 0x00
#define USART_FLOWCONTROL_RTS USART_CR3_RTSE
#define USART_FLOWCONTROL_CTS USART_CR3_CTSE
#define USART_FLOWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
/**@}*/
#define USART_FLOWCONTROL_MASK (USART_CR3_RTSE | USART_CR3_CTSE)
/* --- Function prototypes ------------------------------------------------- */
@@ -314,7 +367,15 @@ void usart_enable_rx_dma(u32 usart);
void usart_disable_rx_dma(u32 usart);
void usart_enable_tx_dma(u32 usart);
void usart_disable_tx_dma(u32 usart);
void usart_enable_rx_interrupt(u32 usart);
void usart_disable_rx_interrupt(u32 usart);
void usart_enable_tx_interrupt(u32 usart);
void usart_disable_tx_interrupt(u32 usart);
bool usart_get_flag(u32 usart, u32 flag);
bool usart_get_interrupt_source(u32 usart, u32 flag);
END_DECLS
#endif
/**@}*/