Inital support for EFM32LG
This commit is contained in:
Kuldeep Singh Dhaka
committed by
Piotr Esden-Tempski
Piotr Esden-Tempski
parent
c28d9727d7
commit
77354cb371
425
lib/usb/usb_efm32lg.c
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425
lib/usb/usb_efm32lg.c
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@@ -0,0 +1,425 @@
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
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* Copyright (C) 2015 Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <string.h>
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/efm32/memorymap.h>
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#include <libopencm3/efm32/cmu.h>
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#include <libopencm3/efm32/usb.h>
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#include <libopencm3/usb/usbd.h>
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#include "usb_private.h"
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/* Receive FIFO size in 32-bit words. */
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#define RX_FIFO_SIZE 256
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/* FIME: EFM32LG have 6 bidirectonal-endpoint
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* problem is "uint32_t doeptsiz[4];" in usb_private.h
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* doeptsiz is fixed size of length 4,
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* if we it to be of length 6
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* possibly, same with "uint8_t force_nak[4];"
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*
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* solution: remove everything driver specific from usb_private.h
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* and move that to there specific driver files.
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* maybe a pointer to driver specific data will do the task. */
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#define ENDPOINT_COUNT 4
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static struct _usbd_device _usbd_dev;
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/** Initialize the USB_FS device controller hardware of the STM32. */
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static usbd_device *efm32lg_usbd_init(void)
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{
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/* Enable clock */
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CMU_HFCORECLKEN0 |= CMU_HFCORECLKEN0_USB | CMU_HFCORECLKEN0_USBC;
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CMU_CMD = CMU_CMD_USBCCLKSEL_HFCLKNODIV;
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/* wait till clock not selected */
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while(!(CMU_STATUS & CMU_STATUS_USBCHFCLKSEL));
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USB_GINTSTS = USB_GINTSTS_MMIS;
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USB_CTRL &= ~USB_CTRL_DMPUAP;
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USB_ROUTE = USB_ROUTE_DMPUPEN | USB_ROUTE_PHYPEN;
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/* Wait for AHB idle. */
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while (!(USB_GRSTCTL & USB_GRSTCTL_AHBIDL));
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/* Do core soft reset. */
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USB_GRSTCTL |= USB_GRSTCTL_CSRST;
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while (USB_GRSTCTL & USB_GRSTCTL_CSRST);
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/* Force peripheral only mode. */
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USB_GUSBCFG |= USB_GUSBCFG_FDMOD | USB_GUSBCFG_TRDT_16BIT;
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/* Full speed device. */
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USB_DCFG |= USB_DCFG_DSPD;
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/* Restart the PHY clock. */
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USB_PCGCCTL = 0;
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USB_GRXFSIZ = efm32lg_usb_driver.rx_fifo_size;
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_usbd_dev.fifo_mem_top = efm32lg_usb_driver.rx_fifo_size;
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/* Unmask interrupts for TX and RX. */
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USB_GAHBCFG |= USB_GAHBCFG_GLBLINTRMSK;
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USB_GINTMSK = USB_GINTMSK_ENUMDNEM |
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USB_GINTMSK_RXFLVLM |
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USB_GINTMSK_IEPINT |
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USB_GINTMSK_USBSUSPM |
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USB_GINTMSK_WUIM;
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USB_DAINTMSK = 0xF;
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USB_DIEPMSK = USB_DIEPMSK_XFRCM;
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return &_usbd_dev;
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}
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static void efm32lg_set_address(usbd_device *usbd_dev, uint8_t addr)
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{
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(void)usbd_dev;
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USB_DCFG = (USB_DCFG & ~USB_DCFG_DAD) | (addr << 4);
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}
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static void efm32lg_ep_setup(usbd_device *usbd_dev, uint8_t addr, uint8_t type,
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uint16_t max_size,
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void (*callback) (usbd_device *usbd_dev, uint8_t ep))
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{
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/*
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* Configure endpoint address and type. Allocate FIFO memory for
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* endpoint. Install callback funciton.
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*/
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uint8_t dir = addr & 0x80;
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addr &= 0x7f;
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if (addr == 0) { /* For the default control endpoint */
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/* Configure IN part. */
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if (max_size >= 64) {
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USB_DIEP0CTL = USB_DIEP0CTL_MPSIZ_64;
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} else if (max_size >= 32) {
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USB_DIEP0CTL = USB_DIEP0CTL_MPSIZ_32;
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} else if (max_size >= 16) {
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USB_DIEP0CTL = USB_DIEP0CTL_MPSIZ_16;
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} else {
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USB_DIEP0CTL = USB_DIEP0CTL_MPSIZ_8;
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}
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USB_DIEP0TSIZ =
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(max_size & USB_DIEP0TSIZ_XFRSIZ_MASK);
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USB_DIEP0CTL |=
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USB_DIEP0CTL_EPENA | USB_DIEP0CTL_SNAK;
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/* Configure OUT part. */
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usbd_dev->doeptsiz[0] = USB_DIEP0TSIZ_STUPCNT_1 |
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USB_DIEP0TSIZ_PKTCNT |
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(max_size & USB_DIEP0TSIZ_XFRSIZ_MASK);
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USB_DOEPx_TSIZ(0) = usbd_dev->doeptsiz[0];
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USB_DOEPx_CTL(0) |=
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USB_DOEP0CTL_EPENA | USB_DIEP0CTL_SNAK;
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USB_GNPTXFSIZ = ((max_size / 4) << 16) |
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usbd_dev->driver->rx_fifo_size;
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usbd_dev->fifo_mem_top += max_size / 4;
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usbd_dev->fifo_mem_top_ep0 = usbd_dev->fifo_mem_top;
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return;
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}
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if (dir) {
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USB_DIEPTXF(addr) = ((max_size / 4) << 16) |
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usbd_dev->fifo_mem_top;
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usbd_dev->fifo_mem_top += max_size / 4;
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USB_DIEPx_TSIZ(addr) =
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(max_size & USB_DIEP0TSIZ_XFRSIZ_MASK);
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USB_DIEPx_CTL(addr) |=
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USB_DIEP0CTL_EPENA | USB_DIEP0CTL_SNAK | (type << 18)
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| USB_DIEP0CTL_USBAEP | USB_DIEP0CTL_SD0PID
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| (addr << 22) | max_size;
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if (callback) {
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usbd_dev->user_callback_ctr[addr][USB_TRANSACTION_IN] =
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(void *)callback;
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}
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}
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if (!dir) {
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usbd_dev->doeptsiz[addr] = USB_DIEP0TSIZ_PKTCNT |
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(max_size & USB_DIEP0TSIZ_XFRSIZ_MASK);
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USB_DOEPx_TSIZ(addr) = usbd_dev->doeptsiz[addr];
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USB_DOEPx_CTL(addr) |= USB_DOEP0CTL_EPENA |
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USB_DOEP0CTL_USBAEP | USB_DIEP0CTL_CNAK |
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USB_DOEP0CTL_SD0PID | (type << 18) | max_size;
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if (callback) {
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usbd_dev->user_callback_ctr[addr][USB_TRANSACTION_OUT] =
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(void *)callback;
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}
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}
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}
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static void efm32lg_endpoints_reset(usbd_device *usbd_dev)
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{
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/* The core resets the endpoints automatically on reset. */
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usbd_dev->fifo_mem_top = usbd_dev->fifo_mem_top_ep0;
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}
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static void efm32lg_ep_stall_set(usbd_device *usbd_dev, uint8_t addr, uint8_t stall)
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{
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(void)usbd_dev;
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if (addr == 0) {
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if (stall) {
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USB_DIEPx_CTL(addr) |= USB_DIEP0CTL_STALL;
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} else {
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USB_DIEPx_CTL(addr) &= ~USB_DIEP0CTL_STALL;
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}
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}
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if (addr & 0x80) {
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addr &= 0x7F;
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if (stall) {
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USB_DIEPx_CTL(addr) |= USB_DIEP0CTL_STALL;
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} else {
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USB_DIEPx_CTL(addr) &= ~USB_DIEP0CTL_STALL;
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USB_DIEPx_CTL(addr) |= USB_DIEP0CTL_SD0PID;
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}
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} else {
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if (stall) {
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USB_DOEPx_CTL(addr) |= USB_DOEP0CTL_STALL;
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} else {
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USB_DOEPx_CTL(addr) &= ~USB_DOEP0CTL_STALL;
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USB_DOEPx_CTL(addr) |= USB_DOEP0CTL_SD0PID;
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}
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}
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}
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static uint8_t efm32lg_ep_stall_get(usbd_device *usbd_dev, uint8_t addr)
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{
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(void)usbd_dev;
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/* Return non-zero if STALL set. */
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if (addr & 0x80) {
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return (USB_DIEPx_CTL(addr & 0x7f) &
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USB_DIEP0CTL_STALL) ? 1 : 0;
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} else {
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return (USB_DOEPx_CTL(addr) &
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USB_DOEP0CTL_STALL) ? 1 : 0;
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}
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}
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static void efm32lg_ep_nak_set(usbd_device *usbd_dev, uint8_t addr, uint8_t nak)
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{
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/* It does not make sence to force NAK on IN endpoints. */
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if (addr & 0x80) {
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return;
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}
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usbd_dev->force_nak[addr] = nak;
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if (nak) {
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USB_DOEPx_CTL(addr) |= USB_DOEP0CTL_SNAK;
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} else {
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USB_DOEPx_CTL(addr) |= USB_DOEP0CTL_CNAK;
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}
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}
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static uint16_t efm32lg_ep_write_packet(usbd_device *usbd_dev, uint8_t addr,
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const void *buf, uint16_t len)
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{
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(void)usbd_dev;
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const uint32_t *buf32 = buf;
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int i;
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addr &= 0x7F;
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/* Return if endpoint is already enabled. */
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if (USB_DIEPx_TSIZ(addr) & USB_DIEP0TSIZ_PKTCNT) {
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return 0;
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}
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/* Enable endpoint for transmission. */
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USB_DIEPx_TSIZ(addr) = USB_DIEP0TSIZ_PKTCNT | len;
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USB_DIEPx_CTL(addr) |= USB_DIEP0CTL_EPENA |
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USB_DIEP0CTL_CNAK;
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volatile uint32_t *fifo = USB_FIFOxD(addr);
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/* Copy buffer to endpoint FIFO, note - memcpy does not work */
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for (i = len; i > 0; i -= 4) {
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*fifo++ = *buf32++;
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}
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return len;
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}
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static uint16_t efm32lg_ep_read_packet(usbd_device *usbd_dev, uint8_t addr,
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void *buf, uint16_t len)
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{
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int i;
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uint32_t *buf32 = buf;
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uint32_t extra;
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len = MIN(len, usbd_dev->rxbcnt);
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usbd_dev->rxbcnt -= len;
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volatile uint32_t *fifo = USB_FIFOxD(addr);
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for (i = len; i >= 4; i -= 4) {
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*buf32++ = *fifo++;
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}
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if (i) {
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extra = *fifo++;
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memcpy(buf32, &extra, i);
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}
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USB_DOEPx_TSIZ(addr) = usbd_dev->doeptsiz[addr];
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USB_DOEPx_CTL(addr) |= USB_DOEP0CTL_EPENA |
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(usbd_dev->force_nak[addr] ?
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USB_DOEP0CTL_SNAK : USB_DOEP0CTL_CNAK);
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return len;
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}
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static void efm32lg_poll(usbd_device *usbd_dev)
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{
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/* Read interrupt status register. */
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uint32_t intsts = USB_GINTSTS;
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int i;
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if (intsts & USB_GINTSTS_ENUMDNE) {
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/* Handle USB RESET condition. */
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USB_GINTSTS = USB_GINTSTS_ENUMDNE;
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usbd_dev->fifo_mem_top = usbd_dev->driver->rx_fifo_size;
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_usbd_reset(usbd_dev);
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return;
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}
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/* Note: RX and TX handled differently in this device. */
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if (intsts & USB_GINTSTS_RXFLVL) {
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/* Receive FIFO non-empty. */
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uint32_t rxstsp = USB_GRXSTSP;
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uint32_t pktsts = rxstsp & USB_GRXSTSP_PKTSTS_MASK;
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if ((pktsts != USB_GRXSTSP_PKTSTS_OUT) &&
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(pktsts != USB_GRXSTSP_PKTSTS_SETUP)) {
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return;
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}
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uint8_t ep = rxstsp & USB_GRXSTSP_EPNUM_MASK;
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uint8_t type;
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if (pktsts == USB_GRXSTSP_PKTSTS_SETUP) {
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type = USB_TRANSACTION_SETUP;
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} else {
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type = USB_TRANSACTION_OUT;
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}
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/* Save packet size for stm32f107_ep_read_packet(). */
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usbd_dev->rxbcnt = (rxstsp & USB_GRXSTSP_BCNT_MASK) >> 4;
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/*
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* FIXME: Why is a delay needed here?
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* This appears to fix a problem where the first 4 bytes
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* of the DATA OUT stage of a control transaction are lost.
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*/
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for (i = 0; i < 1000; i++) {
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__asm__("nop");
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}
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if (usbd_dev->user_callback_ctr[ep][type]) {
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usbd_dev->user_callback_ctr[ep][type] (usbd_dev, ep);
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}
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/* Discard unread packet data. */
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for (i = 0; i < usbd_dev->rxbcnt; i += 4) {
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(void)*USB_FIFOxD(ep);
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}
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usbd_dev->rxbcnt = 0;
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}
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/*
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* There is no global interrupt flag for transmit complete.
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* The XFRC bit must be checked in each USB_DIEPx_INT(x).
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*/
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for (i = 0; i < ENDPOINT_COUNT; i++) { /* Iterate over endpoints. */
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if (USB_DIEPx_INT(i) & USB_DIEP_INT_XFRC) {
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/* Transfer complete. */
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if (usbd_dev->user_callback_ctr[i]
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[USB_TRANSACTION_IN]) {
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usbd_dev->user_callback_ctr[i]
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[USB_TRANSACTION_IN](usbd_dev, i);
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}
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USB_DIEPx_INT(i) = USB_DIEP_INT_XFRC;
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}
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}
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if (intsts & USB_GINTSTS_USBSUSP) {
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if (usbd_dev->user_callback_suspend) {
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usbd_dev->user_callback_suspend();
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}
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USB_GINTSTS = USB_GINTSTS_USBSUSP;
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}
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if (intsts & USB_GINTSTS_WKUPINT) {
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if (usbd_dev->user_callback_resume) {
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usbd_dev->user_callback_resume();
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}
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USB_GINTSTS = USB_GINTSTS_WKUPINT;
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}
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if (intsts & USB_GINTSTS_SOF) {
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if (usbd_dev->user_callback_sof) {
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usbd_dev->user_callback_sof();
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}
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USB_GINTSTS = USB_GINTSTS_SOF;
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}
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if (usbd_dev->user_callback_sof) {
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USB_GINTMSK |= USB_GINTMSK_SOFM;
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} else {
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USB_GINTMSK &= ~USB_GINTMSK_SOFM;
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}
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}
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static void efm32lg_disconnect(usbd_device *usbd_dev, bool disconnected)
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{
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(void)usbd_dev;
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if (disconnected) {
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USB_DCTL |= USB_DCTL_SDIS;
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} else {
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USB_DCTL &= ~USB_DCTL_SDIS;
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}
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}
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const struct _usbd_driver efm32lg_usb_driver = {
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.init = efm32lg_usbd_init,
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.set_address = efm32lg_set_address,
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.ep_setup = efm32lg_ep_setup,
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.ep_reset = efm32lg_endpoints_reset,
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.ep_stall_set = efm32lg_ep_stall_set,
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.ep_stall_get = efm32lg_ep_stall_get,
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.ep_nak_set = efm32lg_ep_nak_set,
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.ep_write_packet = efm32lg_ep_write_packet,
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.ep_read_packet = efm32lg_ep_read_packet,
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.poll = efm32lg_poll,
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.disconnect = efm32lg_disconnect,
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.base_address = USB_BASE,
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.set_address_before_status = 1,
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.rx_fifo_size = RX_FIFO_SIZE,
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};
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