diff --git a/include/libopencm3/cm3/memorymap.h b/include/libopencm3/cm3/memorymap.h
index 450eb586..a7a56948 100644
--- a/include/libopencm3/cm3/memorymap.h
+++ b/include/libopencm3/cm3/memorymap.h
@@ -23,7 +23,7 @@
 /* --- ARM Cortex-M0, M3 and M4 specific definitions ----------------------- */
 
 /* Private peripheral bus - Internal */
-#define PPBI_BASE                       0xE0000000
+#define PPBI_BASE                       (0xE0000000U)
 
 /* Those defined only on ARMv7 and above */
 #if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
diff --git a/include/libopencm3/efm32/efm32tg/memorymap.h b/include/libopencm3/efm32/efm32tg/memorymap.h
index abf37cec..d17bb60c 100644
--- a/include/libopencm3/efm32/efm32tg/memorymap.h
+++ b/include/libopencm3/efm32/efm32tg/memorymap.h
@@ -31,13 +31,13 @@
  * there are discrepancies. */
 #include <libopencm3/cm3/memorymap.h>
 
-#define CODE_BASE		0x00000000
+#define CODE_BASE		(0x00000000U)
 
-#define SRAM_BASE		0x20000000
-#define SRAM_BASE_BITBAND	0x22000000
+#define SRAM_BASE		(0x20000000U)
+#define SRAM_BASE_BITBAND	(0x22000000U)
 
-#define PERIPH_BASE		0x40000000
-#define PERIPH_BASE_BITBAND	0x42000000
+#define PERIPH_BASE		(0x40000000U)
+#define PERIPH_BASE_BITBAND	(0x42000000U)
 
 /* Details of the "Code" section */
 
diff --git a/include/libopencm3/lm3s/memorymap.h b/include/libopencm3/lm3s/memorymap.h
index 55347bf2..df5d6e34 100644
--- a/include/libopencm3/lm3s/memorymap.h
+++ b/include/libopencm3/lm3s/memorymap.h
@@ -24,24 +24,24 @@
 
 /* --- LM3S specific peripheral definitions ----------------------------- */
 
-#define GPIOA_APB_BASE			(0x40004000)
-#define GPIOB_APB_BASE			(0x40005000)
-#define GPIOC_APB_BASE			(0x40006000)
-#define GPIOD_APB_BASE			(0x40007000)
-#define GPIOE_APB_BASE			(0x40024000)
-#define GPIOF_APB_BASE			(0x40025000)
-#define GPIOG_APB_BASE			(0x40026000)
-#define GPIOH_APB_BASE			(0x40027000)
+#define GPIOA_APB_BASE			(0x40004000U)
+#define GPIOB_APB_BASE			(0x40005000U)
+#define GPIOC_APB_BASE			(0x40006000U)
+#define GPIOD_APB_BASE			(0x40007000U)
+#define GPIOE_APB_BASE			(0x40024000U)
+#define GPIOF_APB_BASE			(0x40025000U)
+#define GPIOG_APB_BASE			(0x40026000U)
+#define GPIOH_APB_BASE			(0x40027000U)
 
-#define GPIOA_BASE			(0x40058000)
-#define GPIOB_BASE			(0x40059000)
-#define GPIOC_BASE			(0x4005A000)
-#define GPIOD_BASE			(0x4005B000)
-#define GPIOE_BASE			(0x4005C000)
-#define GPIOF_BASE			(0x4005D000)
-#define GPIOG_BASE			(0x4005E000)
-#define GPIOH_BASE			(0x4005F000)
+#define GPIOA_BASE			(0x40058000U)
+#define GPIOB_BASE			(0x40059000U)
+#define GPIOC_BASE			(0x4005A000U)
+#define GPIOD_BASE			(0x4005B000U)
+#define GPIOE_BASE			(0x4005C000U)
+#define GPIOF_BASE			(0x4005D000U)
+#define GPIOG_BASE			(0x4005E000U)
+#define GPIOH_BASE			(0x4005F000U)
 
-#define SYSTEMCONTROL_BASE		(0x400FE000)
+#define SYSTEMCONTROL_BASE		(0x400FE000U)
 
 #endif
diff --git a/include/libopencm3/lm4f/memorymap.h b/include/libopencm3/lm4f/memorymap.h
index 12b05a21..759d00f7 100644
--- a/include/libopencm3/lm4f/memorymap.h
+++ b/include/libopencm3/lm4f/memorymap.h
@@ -24,43 +24,43 @@
 
 /* --- LM4F specific peripheral definitions ----------------------------- */
 
-#define GPIOA_APB_BASE			(0x40004000)
-#define GPIOB_APB_BASE			(0x40005000)
-#define GPIOC_APB_BASE			(0x40006000)
-#define GPIOD_APB_BASE			(0x40007000)
-#define GPIOE_APB_BASE			(0x40024000)
-#define GPIOF_APB_BASE			(0x40025000)
-#define GPIOG_APB_BASE			(0x40026000)
-#define GPIOH_APB_BASE			(0x40027000)
-#define GPIOJ_APB_BASE			(0x4003D000)
+#define GPIOA_APB_BASE			(0x40004000U)
+#define GPIOB_APB_BASE			(0x40005000U)
+#define GPIOC_APB_BASE			(0x40006000U)
+#define GPIOD_APB_BASE			(0x40007000U)
+#define GPIOE_APB_BASE			(0x40024000U)
+#define GPIOF_APB_BASE			(0x40025000U)
+#define GPIOG_APB_BASE			(0x40026000U)
+#define GPIOH_APB_BASE			(0x40027000U)
+#define GPIOJ_APB_BASE			(0x4003D000U)
 
-#define GPIOA_BASE			(0x40058000)
-#define GPIOB_BASE			(0x40059000)
-#define GPIOC_BASE			(0x4005A000)
-#define GPIOD_BASE			(0x4005B000)
-#define GPIOE_BASE			(0x4005C000)
-#define GPIOF_BASE			(0x4005D000)
-#define GPIOG_BASE			(0x4005E000)
-#define GPIOH_BASE			(0x4005F000)
-#define GPIOJ_BASE			(0x40060000)
-#define GPIOK_BASE			(0x40061000)
-#define GPIOL_BASE			(0x40062000)
-#define GPIOM_BASE			(0x40063000)
-#define GPION_BASE			(0x40064000)
-#define GPIOP_BASE			(0x40065000)
-#define GPIOQ_BASE			(0x40066000)
+#define GPIOA_BASE			(0x40058000U)
+#define GPIOB_BASE			(0x40059000U)
+#define GPIOC_BASE			(0x4005A000U)
+#define GPIOD_BASE			(0x4005B000U)
+#define GPIOE_BASE			(0x4005C000U)
+#define GPIOF_BASE			(0x4005D000U)
+#define GPIOG_BASE			(0x4005E000U)
+#define GPIOH_BASE			(0x4005F000U)
+#define GPIOJ_BASE			(0x40060000U)
+#define GPIOK_BASE			(0x40061000U)
+#define GPIOL_BASE			(0x40062000U)
+#define GPIOM_BASE			(0x40063000U)
+#define GPION_BASE			(0x40064000U)
+#define GPIOP_BASE			(0x40065000U)
+#define GPIOQ_BASE			(0x40066000U)
 
-#define UART0_BASE			(0x4000C000)
-#define UART1_BASE			(0x4000D000)
-#define UART2_BASE			(0x4000E000)
-#define UART3_BASE			(0x4000F000)
-#define UART4_BASE			(0x40010000)
-#define UART5_BASE			(0x40011000)
-#define UART6_BASE			(0x40012000)
-#define UART7_BASE			(0x40013000)
+#define UART0_BASE			(0x4000C000U)
+#define UART1_BASE			(0x4000D000U)
+#define UART2_BASE			(0x4000E000U)
+#define UART3_BASE			(0x4000F000U)
+#define UART4_BASE			(0x40010000U)
+#define UART5_BASE			(0x40011000U)
+#define UART6_BASE			(0x40012000U)
+#define UART7_BASE			(0x40013000U)
 
-#define USB_BASE			(0x40050000)
+#define USB_BASE			(0x40050000U)
 
-#define SYSCTL_BASE			(0x400FE000)
+#define SYSCTL_BASE			(0x400FE000U)
 
 #endif
diff --git a/include/libopencm3/lpc13xx/memorymap.h b/include/libopencm3/lpc13xx/memorymap.h
index 51397b58..01b94b22 100644
--- a/include/libopencm3/lpc13xx/memorymap.h
+++ b/include/libopencm3/lpc13xx/memorymap.h
@@ -25,8 +25,8 @@
 /* --- LPC13XX specific peripheral definitions ----------------------------- */
 
 /* Memory map for all busses */
-#define PERIPH_BASE_APB			0x40000000
-#define PERIPH_BASE_AHB			0x50000000
+#define PERIPH_BASE_APB			(0x40000000U)
+#define PERIPH_BASE_AHB			(0x50000000U)
 
 /* Register boundary addresses */
 
diff --git a/include/libopencm3/lpc17xx/memorymap.h b/include/libopencm3/lpc17xx/memorymap.h
index 9dce5dd8..b82a51bc 100644
--- a/include/libopencm3/lpc17xx/memorymap.h
+++ b/include/libopencm3/lpc17xx/memorymap.h
@@ -25,9 +25,9 @@
 /* --- LPC17XX specific peripheral definitions ----------------------------- */
 
 /* Memory map for all busses */
-#define PERIPH_BASE_APB0		0x40000000
-#define PERIPH_BASE_APB1		0x40080000
-#define PERIPH_BASE_AHB			0x20000000
+#define PERIPH_BASE_APB0		(0x40000000U)
+#define PERIPH_BASE_APB1		(0x40080000U)
+#define PERIPH_BASE_AHB			(0x20000000U)
 
 /* Register boundary addresses */
 
diff --git a/include/libopencm3/lpc43xx/memorymap.h b/include/libopencm3/lpc43xx/memorymap.h
index ac3ade2b..5d2bdc4d 100644
--- a/include/libopencm3/lpc43xx/memorymap.h
+++ b/include/libopencm3/lpc43xx/memorymap.h
@@ -26,11 +26,11 @@
 /* --- LPC43XX specific peripheral definitions ----------------------------- */
 
 /* Memory map for all busses */
-#define PERIPH_BASE_AHB                 0x40000000
-#define PERIPH_BASE_APB0                0x40080000
-#define PERIPH_BASE_APB1                0x400A0000
-#define PERIPH_BASE_APB2                0x400C0000
-#define PERIPH_BASE_APB3                0x400E0000
+#define PERIPH_BASE_AHB                 (0x40000000U)
+#define PERIPH_BASE_APB0                (0x40080000U)
+#define PERIPH_BASE_APB1                (0x400A0000U)
+#define PERIPH_BASE_APB2                (0x400C0000U)
+#define PERIPH_BASE_APB3                (0x400E0000U)
 
 /* Register boundary addresses */
 
@@ -50,20 +50,20 @@
 /* 0x4001 2000 - 0x4003 FFFF Reserved */
 
 /* RTC domain peripherals */
-#define ATIMER_BASE                     0x40040000
-#define BACKUP_REG_BASE                 0x40041000
-#define PMC_BASE                        0x40042000
-#define CREG_BASE                       0x40043000
-#define EVENTROUTER_BASE                0x40044000
-#define OTP_BASE                        0x40045000
-#define RTC_BASE                        0x40046000
+#define ATIMER_BASE                     (0x40040000U)
+#define BACKUP_REG_BASE                 (0x40041000U)
+#define PMC_BASE                        (0x40042000U)
+#define CREG_BASE                       (0x40043000U)
+#define EVENTROUTER_BASE                (0x40044000U)
+#define OTP_BASE                        (0x40045000U)
+#define RTC_BASE                        (0x40046000U)
 /* 0x4004 7000 - 0x4004 FFFF Reserved */
 
 /* clocking/reset control peripherals */
-#define CGU_BASE                        0x40050000
-#define CCU1_BASE                       0x40051000
-#define CCU2_BASE                       0x40052000
-#define RGU_BASE                        0x40053000
+#define CGU_BASE                        (0x40050000U)
+#define CCU1_BASE                       (0x40051000U)
+#define CCU2_BASE                       (0x40052000U)
+#define RGU_BASE                        (0x40053000U)
 /* 0x4005 4000 - 0x4005 FFFF Reserved */
 
 /* 0x4006 0000 - 0x4007 FFFF Reserved */
@@ -116,16 +116,16 @@
 
 /* 0x400F 0000 - 0x400F 0FFF Reserved */
 
-#define AES_BASE                        0x400F1000
+#define AES_BASE                        (0x400F1000U)
 
 /* 0x400F 2000 - 0x400F 3FFF Reserved */
 
-#define GPIO_PORT_BASE                  0x400F4000
+#define GPIO_PORT_BASE                  (0x400F4000U)
 
 /* 0x400F 8000 - 0x400F FFFF Reserved */
 
-#define SPI_PORT_BASE                   0x40100000
-#define SGPIO_PORT_BASE                 0x40101000
+#define SPI_PORT_BASE                   (0x40100000U)
+#define SGPIO_PORT_BASE                 (0x40101000U)
 
 /* 0x4010 2000 - 0x41FF FFFF Reserved */
 
diff --git a/include/libopencm3/sam/3n/memorymap.h b/include/libopencm3/sam/3n/memorymap.h
index 9dde0f4d..34c193fa 100644
--- a/include/libopencm3/sam/3n/memorymap.h
+++ b/include/libopencm3/sam/3n/memorymap.h
@@ -24,37 +24,37 @@
 
 /* --- SAM3N peripheral space -------------------------------------------- */
 
-#define SPI_BASE			(0x40008000)
-#define TC0_BASE			(0x40010000)
-#define TC1_BASE			(0x40010040)
-#define TC2_BASE			(0x40010080)
-#define TC3_BASE			(0x40014000)
-#define TC4_BASE			(0x40014040)
-#define TC5_BASE			(0x40014080)
-#define TWI0_BASE			(0x40018000)
-#define TWI1_BASE			(0x4001C000)
-#define PWM_BASE			(0x40020000)
-#define USART0_BASE			(0x40024000)
-#define USART1_BASE			(0x40028000)
-#define ADC_BASE			(0x40038000)
-#define DACC_BASE			(0x4003C000)
+#define SPI_BASE			(0x40008000U)
+#define TC0_BASE			(0x40010000U)
+#define TC1_BASE			(0x40010040U)
+#define TC2_BASE			(0x40010080U)
+#define TC3_BASE			(0x40014000U)
+#define TC4_BASE			(0x40014040U)
+#define TC5_BASE			(0x40014080U)
+#define TWI0_BASE			(0x40018000U)
+#define TWI1_BASE			(0x4001C000U)
+#define PWM_BASE			(0x40020000U)
+#define USART0_BASE			(0x40024000U)
+#define USART1_BASE			(0x40028000U)
+#define ADC_BASE			(0x40038000U)
+#define DACC_BASE			(0x4003C000U)
 
 /* --- SAM3N system controller space ------------------------------------- */
-#define SMC_BASE			(0x400E0000)
-#define MATRIX_BASE			(0x400E0200)
-#define PMC_BASE			(0x400E0400)
-#define UART0_BASE			(0x400E0600)
-#define CHIPID_BASE			(0x400E0740)
-#define UART1_BASE			(0x400E0800)
-#define EEFC_BASE			(0x400E0A00)
-#define PIOA_BASE			(0x400E0E00)
-#define PIOB_BASE			(0x400E1000)
-#define PIOC_BASE			(0x400E1200)
-#define RSTC_BASE			(0x400E1400)
-#define SUPC_BASE			(0x400E1410)
-#define RTT_BASE			(0x400E1430)
-#define WDT_BASE			(0x400E1450)
-#define RTC_BASE			(0x400E1460)
-#define GPBR_BASE			(0x400E1490)
+#define SMC_BASE			(0x400E0000U)
+#define MATRIX_BASE			(0x400E0200U)
+#define PMC_BASE			(0x400E0400U)
+#define UART0_BASE			(0x400E0600U)
+#define CHIPID_BASE			(0x400E0740U)
+#define UART1_BASE			(0x400E0800U)
+#define EEFC_BASE			(0x400E0A00U)
+#define PIOA_BASE			(0x400E0E00U)
+#define PIOB_BASE			(0x400E1000U)
+#define PIOC_BASE			(0x400E1200U)
+#define RSTC_BASE			(0x400E1400U)
+#define SUPC_BASE			(0x400E1410U)
+#define RTT_BASE			(0x400E1430U)
+#define WDT_BASE			(0x400E1450U)
+#define RTC_BASE			(0x400E1460U)
+#define GPBR_BASE			(0x400E1490U)
 
 #endif
diff --git a/include/libopencm3/sam/3x/memorymap.h b/include/libopencm3/sam/3x/memorymap.h
index ca0bb1a5..3b214ea7 100644
--- a/include/libopencm3/sam/3x/memorymap.h
+++ b/include/libopencm3/sam/3x/memorymap.h
@@ -24,55 +24,55 @@
 
 /* --- SAM3X peripheral space -------------------------------------------- */
 
-#define HSMCI_BASE			(0x40000000)
-#define SSC_BASE			(0x40004000)
-#define SPI0_BASE			(0x40008000)
-#define SPI1_BASE			(0x4000C000)
-#define TC0_BASE			(0x40080000)
-#define TC1_BASE			(0x40080040)
-#define TC2_BASE			(0x40080080)
-#define TC3_BASE			(0x40084000)
-#define TC4_BASE			(0x40084040)
-#define TC5_BASE			(0x40084080)
-#define TC6_BASE			(0x40088000)
-#define TC7_BASE			(0x40088040)
-#define TC8_BASE			(0x40088080)
-#define TWI0_BASE			(0x4008C000)
-#define TWI1_BASE			(0x40090000)
-#define PWM_BASE			(0x40094000)
-#define USART0_BASE			(0x40098000)
-#define USART1_BASE			(0x4009C000)
-#define USART2_BASE			(0x400A0000)
-#define USART3_BASE			(0x400A4000)
-#define UOTGHS_BASE			(0x400AC000)
-#define EMAC_BASE			(0x400B0000)
-#define CAN0_BASE			(0x400B4000)
-#define CAN1_BASE			(0x400B8000)
-#define TRNG_BASE			(0x400BC000)
-#define ADC_BASE			(0x400C0000)
-#define DMAC_BASE			(0x400C4000)
+#define HSMCI_BASE			(0x40000000U)
+#define SSC_BASE			(0x40004000U)
+#define SPI0_BASE			(0x40008000U)
+#define SPI1_BASE			(0x4000C000U)
+#define TC0_BASE			(0x40080000U)
+#define TC1_BASE			(0x40080040U)
+#define TC2_BASE			(0x40080080U)
+#define TC3_BASE			(0x40084000U)
+#define TC4_BASE			(0x40084040U)
+#define TC5_BASE			(0x40084080U)
+#define TC6_BASE			(0x40088000U)
+#define TC7_BASE			(0x40088040U)
+#define TC8_BASE			(0x40088080U)
+#define TWI0_BASE			(0x4008C000U)
+#define TWI1_BASE			(0x40090000U)
+#define PWM_BASE			(0x40094000U)
+#define USART0_BASE			(0x40098000U)
+#define USART1_BASE			(0x4009C000U)
+#define USART2_BASE			(0x400A0000U)
+#define USART3_BASE			(0x400A4000U)
+#define UOTGHS_BASE			(0x400AC000U)
+#define EMAC_BASE			(0x400B0000U)
+#define CAN0_BASE			(0x400B4000U)
+#define CAN1_BASE			(0x400B8000U)
+#define TRNG_BASE			(0x400BC000U)
+#define ADC_BASE			(0x400C0000U)
+#define DMAC_BASE			(0x400C4000U)
 
 /* --- SAM3X system controller space ------------------------------------- */
-#define SMC_BASE			(0x400E0000)
-#define SDRAM_BASE			(0x400E0200)
-#define MATRIX_BASE			(0x400E0400)
-#define PMC_BASE			(0x400E0600)
-#define UART_BASE			(0x400E0800)
-#define CHIPID_BASE			(0x400E0940)
-#define EEFC0_BASE			(0x400E0A00)
-#define EEFC1_BASE			(0x400E0C00)
-#define PIOA_BASE			(0x400E0E00)
-#define PIOB_BASE			(0x400E1000)
-#define PIOC_BASE			(0x400E1200)
-#define PIOD_BASE			(0x400E1400)
-#define PIOE_BASE			(0x400E1600)
-#define PIOF_BASE			(0x400E1800)
-#define RSTC_BASE			(0x400E1A00)
-#define SUPC_BASE			(0x400E1A10)
-#define RTT_BASE			(0x400E1A30)
-#define WDT_BASE			(0x400E1A50)
-#define RTC_BASE			(0x400E1A60)
-#define GPBR_BASE			(0x400E1A90)
-#define RTC_BASE			(0x400E1A60)
+#define SMC_BASE			(0x400E0000U)
+#define SDRAM_BASE			(0x400E0200U)
+#define MATRIX_BASE			(0x400E0400U)
+#define PMC_BASE			(0x400E0600U)
+#define UART_BASE			(0x400E0800U)
+#define CHIPID_BASE			(0x400E0940U)
+#define EEFC0_BASE			(0x400E0A00U)
+#define EEFC1_BASE			(0x400E0C00U)
+#define PIOA_BASE			(0x400E0E00U)
+#define PIOB_BASE			(0x400E1000U)
+#define PIOC_BASE			(0x400E1200U)
+#define PIOD_BASE			(0x400E1400U)
+#define PIOE_BASE			(0x400E1600U)
+#define PIOF_BASE			(0x400E1800U)
+#define RSTC_BASE			(0x400E1A00U)
+#define SUPC_BASE			(0x400E1A10U)
+#define RTT_BASE			(0x400E1A30U)
+#define WDT_BASE			(0x400E1A50U)
+#define RTC_BASE			(0x400E1A60U)
+#define GPBR_BASE			(0x400E1A90U)
+#define RTC_BASE			(0x400E1A60U)
 
 #endif
diff --git a/include/libopencm3/stm32/f0/memorymap.h b/include/libopencm3/stm32/f0/memorymap.h
index d61c4cde..dedd512d 100644
--- a/include/libopencm3/stm32/f0/memorymap.h
+++ b/include/libopencm3/stm32/f0/memorymap.h
@@ -27,9 +27,9 @@
 /* --- STM32 specific peripheral definitions ------------------------------- */
 
 /* Memory map for all buses */
-#define FLASH_BASE			((uint32_t)0x08000000)
-#define PERIPH_BASE			((uint32_t)0x40000000)
-#define INFO_BASE			((uint32_t)0x1ffff000)
+#define FLASH_BASE			(0x08000000U)
+#define PERIPH_BASE			(0x40000000U)
+#define INFO_BASE			(0x1ffff000U)
 #define PERIPH_BASE_APB			(PERIPH_BASE + 0x00000000)
 #define PERIPH_BASE_AHB1		(PERIPH_BASE + 0x00020000)
 #define PERIPH_BASE_AHB2		(PERIPH_BASE + 0x08000000)
@@ -93,8 +93,8 @@
 #define GPIO_PORT_F_BASE		(PERIPH_BASE_AHB2 + 0x1400)
 
 /* Device Electronic Signature */
-#define DESIG_FLASH_SIZE_BASE		(0x1FFFF7CC)
-#define DESIG_UNIQUE_ID_BASE		(0x1FFFF7AC)
+#define DESIG_FLASH_SIZE_BASE		(0x1FFFF7CCU)
+#define DESIG_UNIQUE_ID_BASE		(0x1FFFF7ACU)
 #define DESIG_UNIQUE_ID0		MMIO32(DESIG_UNIQUE_ID_BASE)
 #define DESIG_UNIQUE_ID1		MMIO32(DESIG_UNIQUE_ID_BASE + 4)
 #define DESIG_UNIQUE_ID2		MMIO32(DESIG_UNIQUE_ID_BASE + 8)
diff --git a/include/libopencm3/stm32/f1/memorymap.h b/include/libopencm3/stm32/f1/memorymap.h
index 29050c03..0fc36399 100644
--- a/include/libopencm3/stm32/f1/memorymap.h
+++ b/include/libopencm3/stm32/f1/memorymap.h
@@ -25,9 +25,9 @@
 /* --- STM32 specific peripheral definitions ------------------------------- */
 
 /* Memory map for all buses */
-#define FLASH_BASE			((uint32_t)0x08000000)
-#define PERIPH_BASE			((uint32_t)0x40000000)
-#define INFO_BASE			((uint32_t)0x1ffff000)
+#define FLASH_BASE			(0x08000000U)
+#define PERIPH_BASE			(0x40000000U)
+#define INFO_BASE			(0x1ffff000U)
 #define PERIPH_BASE_APB1		(PERIPH_BASE + 0x00000)
 #define PERIPH_BASE_APB2		(PERIPH_BASE + 0x10000)
 #define PERIPH_BASE_AHB			(PERIPH_BASE + 0x18000)
diff --git a/include/libopencm3/stm32/f2/memorymap.h b/include/libopencm3/stm32/f2/memorymap.h
index 6aec2379..afd4ae30 100644
--- a/include/libopencm3/stm32/f2/memorymap.h
+++ b/include/libopencm3/stm32/f2/memorymap.h
@@ -25,12 +25,12 @@
 /* --- STM32F20x specific peripheral definitions --------------------------- */
 
 /* Memory map for all busses */
-#define PERIPH_BASE			0x40000000
+#define PERIPH_BASE			(0x40000000U)
 #define PERIPH_BASE_APB1		(PERIPH_BASE + 0x00000)
 #define PERIPH_BASE_APB2		(PERIPH_BASE + 0x10000)
 #define PERIPH_BASE_AHB1		(PERIPH_BASE + 0x20000)
-#define PERIPH_BASE_AHB2		0x50000000
-#define PERIPH_BASE_AHB3		0x60000000
+#define PERIPH_BASE_AHB2		(0x50000000U)
+#define PERIPH_BASE_AHB3		(0x60000000U)
 
 /* Register boundary addresses */
 
@@ -131,8 +131,8 @@
 #define DBGMCU_BASE			(PPBI_BASE + 0x00042000)
 
 /* Device Electronic Signature */
-#define DESIG_FLASH_SIZE_BASE		(0x1FFF7A22)
-#define DESIG_UNIQUE_ID_BASE		(0x1FFF7A10)
+#define DESIG_FLASH_SIZE_BASE		(0x1FFF7A22U)
+#define DESIG_UNIQUE_ID_BASE		(0x1FFF7A10U)
 #define DESIG_UNIQUE_ID0		MMIO32(DESIG_UNIQUE_ID_BASE)
 #define DESIG_UNIQUE_ID1		MMIO32(DESIG_UNIQUE_ID_BASE + 4)
 #define DESIG_UNIQUE_ID2		MMIO32(DESIG_UNIQUE_ID_BASE + 8)
diff --git a/include/libopencm3/stm32/f3/memorymap.h b/include/libopencm3/stm32/f3/memorymap.h
index 44de7652..efaded70 100644
--- a/include/libopencm3/stm32/f3/memorymap.h
+++ b/include/libopencm3/stm32/f3/memorymap.h
@@ -27,12 +27,12 @@
 /* --- STM32F3 specific peripheral definitions ----------------------------- */
 
 /* Memory map for all busses */
-#define PERIPH_BASE			0x40000000
+#define PERIPH_BASE			(0x40000000U)
 #define PERIPH_BASE_APB1		(PERIPH_BASE + 0x00000)
 #define PERIPH_BASE_APB2		(PERIPH_BASE + 0x10000)
 #define PERIPH_BASE_AHB1		(PERIPH_BASE + 0x20000)
-#define PERIPH_BASE_AHB2		0x48000000
-#define PERIPH_BASE_AHB3		0x50000000
+#define PERIPH_BASE_AHB2		(0x48000000U)
+#define PERIPH_BASE_AHB3		(0x50000000U)
 
 /* Register boundary addresses */
 
@@ -115,8 +115,8 @@
 #define DBGMCU_BASE			(PPBI_BASE + 0x00042000)
 
 /* Device Electronic Signature */
-#define DESIG_FLASH_SIZE_BASE		(0x1FFFF7CC)
-#define DESIG_UNIQUE_ID_BASE		(0x1FFFF7AC)
+#define DESIG_FLASH_SIZE_BASE		(0x1FFFF7CCU)
+#define DESIG_UNIQUE_ID_BASE		(0x1FFFF7ACU)
 #define DESIG_UNIQUE_ID0		MMIO32(DESIG_UNIQUE_ID_BASE)
 #define DESIG_UNIQUE_ID1		MMIO32(DESIG_UNIQUE_ID_BASE + 4)
 #define DESIG_UNIQUE_ID2		MMIO32(DESIG_UNIQUE_ID_BASE + 8)
diff --git a/include/libopencm3/stm32/f4/memorymap.h b/include/libopencm3/stm32/f4/memorymap.h
index 136364f9..2d637ebc 100644
--- a/include/libopencm3/stm32/f4/memorymap.h
+++ b/include/libopencm3/stm32/f4/memorymap.h
@@ -25,7 +25,7 @@
 /* --- STM32F4 specific peripheral definitions ----------------------------- */
 
 /* Memory map for all busses */
-#define PERIPH_BASE			0x40000000
+#define PERIPH_BASE			(0x40000000U)
 #define PERIPH_BASE_APB1		(PERIPH_BASE + 0x00000)
 #define PERIPH_BASE_APB2		(PERIPH_BASE + 0x10000)
 #define PERIPH_BASE_AHB1		(PERIPH_BASE + 0x20000)
@@ -141,8 +141,8 @@
 #define DBGMCU_BASE			(PPBI_BASE + 0x00042000)
 
 /* Device Electronic Signature */
-#define DESIG_FLASH_SIZE_BASE		(0x1FFF7A22)
-#define DESIG_UNIQUE_ID_BASE		(0x1FFF7A10)
+#define DESIG_FLASH_SIZE_BASE		(0x1FFF7A22U)
+#define DESIG_UNIQUE_ID_BASE		(0x1FFF7A10U)
 #define DESIG_UNIQUE_ID0		MMIO32(DESIG_UNIQUE_ID_BASE)
 #define DESIG_UNIQUE_ID1		MMIO32(DESIG_UNIQUE_ID_BASE + 4)
 #define DESIG_UNIQUE_ID2		MMIO32(DESIG_UNIQUE_ID_BASE + 8)
diff --git a/include/libopencm3/stm32/fsmc.h b/include/libopencm3/stm32/fsmc.h
index 05773580..c577f334 100644
--- a/include/libopencm3/stm32/fsmc.h
+++ b/include/libopencm3/stm32/fsmc.h
@@ -29,10 +29,10 @@
 
 /* --- Convenience macros -------------------------------------------------- */
 
-#define FSMC_BANK1_BASE			0x60000000 /* NOR / PSRAM */
-#define FSMC_BANK2_BASE			0x70000000 /* NAND flash */
-#define FSMC_BANK3_BASE			0x80000000 /* NAND flash */
-#define FSMC_BANK4_BASE			0x90000000 /* PC card */
+#define FSMC_BANK1_BASE			0x60000000U /* NOR / PSRAM */
+#define FSMC_BANK2_BASE			0x70000000U /* NAND flash */
+#define FSMC_BANK3_BASE			0x80000000U /* NAND flash */
+#define FSMC_BANK4_BASE			0x90000000U /* PC card */
 
 /* --- FSMC registers ------------------------------------------------------ */
 
diff --git a/include/libopencm3/stm32/l1/memorymap.h b/include/libopencm3/stm32/l1/memorymap.h
index 5015032a..abdb34df 100644
--- a/include/libopencm3/stm32/l1/memorymap.h
+++ b/include/libopencm3/stm32/l1/memorymap.h
@@ -26,8 +26,8 @@
 /* --- STM32 specific peripheral definitions ------------------------------- */
 
 /* Memory map for all busses */
-#define PERIPH_BASE			((uint32_t)0x40000000)
-#define INFO_BASE			((uint32_t)0x1ff00000)
+#define PERIPH_BASE			(0x40000000U)
+#define INFO_BASE			(0x1ff00000U)
 #define PERIPH_BASE_APB1		(PERIPH_BASE + 0x00000)
 #define PERIPH_BASE_APB2		(PERIPH_BASE + 0x10000)
 #define PERIPH_BASE_AHB			(PERIPH_BASE + 0x20000)
diff --git a/lib/lpc43xx/m4/vector_chipset.c b/lib/lpc43xx/m4/vector_chipset.c
index ffd02b44..270e30ea 100644
--- a/lib/lpc43xx/m4/vector_chipset.c
+++ b/lib/lpc43xx/m4/vector_chipset.c
@@ -22,7 +22,7 @@
 
 extern unsigned _etext_ram, _text_ram, _etext_rom;
 
-#define CREG_M4MEMMAP   MMIO32((0x40043000 + 0x100))
+#define CREG_M4MEMMAP   MMIO32((0x40043000U + 0x100))
 
 static void pre_main(void)
 {