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Better method of reset and clock handling with RCC, support L1, F1, F2, F3, F4

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This commit is contained in:
BuFran
2013-07-02 20:04:51 +02:00
committed by Piotr Esden-Tempski
parent 33f75a529d
commit 723e1a69bd
19 changed files with 1211 additions and 242 deletions
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67
lib/stm32/f4/rcc.c
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@@ -1,3 +1,21 @@
/** @defgroup rcc_file RCC
*
* @ingroup STM32F4xx
*
* @section rcc_f4_api_ex Reset and Clock Control API.
*
* @brief <b>libopencm3 STM32F4xx Reset and Clock Control</b>
*
* @author @htmlonly &copy; @endhtmlonly 2013 Frantisek Burian <BuFran at seznam.cz>
*
* @date 18 Jun 2013
*
* This library supports the Reset and Clock Control System in the STM32 series
* of ARM Cortex Microcontrollers by ST Microelectronics.
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
@@ -24,6 +42,8 @@
#include <libopencm3/stm32/f4/pwr.h>
#include <libopencm3/stm32/f4/flash.h>
/**@{*/
/* Set the default ppre1 and ppre2 peripheral clock frequencies after reset. */
uint32_t rcc_ppre1_frequency = 16000000;
uint32_t rcc_ppre2_frequency = 16000000;
@@ -160,7 +180,7 @@ const clock_scale_t hse_16mhz_3v3[CLOCK_3V3_END] = {
},
};
void rcc_osc_ready_int_clear(osc_t osc)
void rcc_osc_ready_int_clear(enum rcc_osc osc)
{
switch (osc) {
case PLL:
@@ -181,7 +201,7 @@ void rcc_osc_ready_int_clear(osc_t osc)
}
}
void rcc_osc_ready_int_enable(osc_t osc)
void rcc_osc_ready_int_enable(enum rcc_osc osc)
{
switch (osc) {
case PLL:
@@ -202,7 +222,7 @@ void rcc_osc_ready_int_enable(osc_t osc)
}
}
void rcc_osc_ready_int_disable(osc_t osc)
void rcc_osc_ready_int_disable(enum rcc_osc osc)
{
switch (osc) {
case PLL:
@@ -223,7 +243,7 @@ void rcc_osc_ready_int_disable(osc_t osc)
}
}
int rcc_osc_ready_int_flag(osc_t osc)
int rcc_osc_ready_int_flag(enum rcc_osc osc)
{
switch (osc) {
case PLL:
@@ -256,7 +276,7 @@ int rcc_css_int_flag(void)
return ((RCC_CIR & RCC_CIR_CSSF) != 0);
}
void rcc_wait_for_osc_ready(osc_t osc)
void rcc_wait_for_osc_ready(enum rcc_osc osc)
{
switch (osc) {
case PLL:
@@ -277,7 +297,7 @@ void rcc_wait_for_osc_ready(osc_t osc)
}
}
void rcc_wait_for_sysclk_status(osc_t osc)
void rcc_wait_for_sysclk_status(enum rcc_osc osc)
{
switch (osc) {
case PLL:
@@ -295,7 +315,7 @@ void rcc_wait_for_sysclk_status(osc_t osc)
}
}
void rcc_osc_on(osc_t osc)
void rcc_osc_on(enum rcc_osc osc)
{
switch (osc) {
case PLL:
@@ -316,7 +336,7 @@ void rcc_osc_on(osc_t osc)
}
}
void rcc_osc_off(osc_t osc)
void rcc_osc_off(enum rcc_osc osc)
{
switch (osc) {
case PLL:
@@ -347,7 +367,7 @@ void rcc_css_disable(void)
RCC_CR &= ~RCC_CR_CSSON;
}
void rcc_osc_bypass_enable(osc_t osc)
void rcc_osc_bypass_enable(enum rcc_osc osc)
{
switch (osc) {
case HSE:
@@ -364,7 +384,7 @@ void rcc_osc_bypass_enable(osc_t osc)
}
}
void rcc_osc_bypass_disable(osc_t osc)
void rcc_osc_bypass_disable(enum rcc_osc osc)
{
switch (osc) {
case HSE:
@@ -381,25 +401,7 @@ void rcc_osc_bypass_disable(osc_t osc)
}
}
void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en)
{
*reg |= en;
}
void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en)
{
*reg &= ~en;
}
void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset)
{
*reg |= reset;
}
void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset)
{
*reg &= ~clear_reset;
}
void rcc_set_sysclk_source(uint32_t clk)
{
@@ -532,11 +534,6 @@ void rcc_clock_setup_hse_3v3(const clock_scale_t *clock)
rcc_osc_off(HSI);
}
void rcc_backupdomain_reset(void)
{
/* Set the backup domain software reset. */
RCC_BDCR |= RCC_BDCR_BDRST;
/* Clear the backup domain software reset. */
RCC_BDCR &= ~RCC_BDCR_BDRST;
}
/**@}*/