Better method of reset and clock handling with RCC, support L1, F1, F2, F3, F4
This commit is contained in:
BuFran
committed by
Piotr Esden-Tempski
Piotr Esden-Tempski
parent
33f75a529d
commit
723e1a69bd
@@ -421,6 +421,158 @@ typedef enum {
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PLL, HSE, HSI, MSI, LSE, LSI
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} osc_t;
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#define _REG_BIT(base, bit) (((base) << 5) + (bit))
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enum rcc_periph_clken {
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/* AHB peripherals */
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RCC_GPIOA = _REG_BIT(0x1c, 0),
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RCC_GPIOB = _REG_BIT(0x1c, 1),
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RCC_GPIOC = _REG_BIT(0x1c, 2),
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RCC_GPIOD = _REG_BIT(0x1c, 3),
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RCC_GPIOE = _REG_BIT(0x1c, 4),
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RCC_GPIOH = _REG_BIT(0x1c, 5),
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RCC_GPIOF = _REG_BIT(0x1c, 6),
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RCC_GPIOG = _REG_BIT(0x1c, 7),
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RCC_CRC = _REG_BIT(0x1c, 12),
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RCC_FLITF = _REG_BIT(0x1c, 15),
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RCC_DMA1 = _REG_BIT(0x1c, 24),
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RCC_DMA2 = _REG_BIT(0x1c, 25),
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RCC_AES = _REG_BIT(0x1c, 27),
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RCC_FSMC = _REG_BIT(0x1c, 30),
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/* APB2 peripherals */
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RCC_SYSCFG = _REG_BIT(0x20, 0),
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RCC_TIM9 = _REG_BIT(0x20, 2),
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RCC_TIM10 = _REG_BIT(0x20, 3),
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RCC_TIM11 = _REG_BIT(0x20, 4),
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RCC_ADC1 = _REG_BIT(0x20, 9),
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RCC_SDIO = _REG_BIT(0x20, 11),
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RCC_SPI1 = _REG_BIT(0x20, 12),
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RCC_USART1 = _REG_BIT(0x20, 14),
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/* APB1 peripherals*/
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RCC_TIM2 = _REG_BIT(0x24, 0),
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RCC_TIM3 = _REG_BIT(0x24, 1),
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RCC_TIM4 = _REG_BIT(0x24, 2),
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RCC_TIM5 = _REG_BIT(0x24, 3),
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RCC_TIM6 = _REG_BIT(0x24, 4),
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RCC_TIM7 = _REG_BIT(0x24, 5),
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RCC_LCD = _REG_BIT(0x24, 9),
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RCC_WWDG = _REG_BIT(0x24, 11),
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RCC_SPI2 = _REG_BIT(0x24, 14),
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RCC_SPI3 = _REG_BIT(0x24, 15),
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RCC_USART2 = _REG_BIT(0x24, 17),
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RCC_USART3 = _REG_BIT(0x24, 18),
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RCC_UART4 = _REG_BIT(0x24, 19),
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RCC_UART5 = _REG_BIT(0x24, 20),
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RCC_I2C1 = _REG_BIT(0x24, 21),
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RCC_I2C2 = _REG_BIT(0x24, 22),
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RCC_USB = _REG_BIT(0x24, 23),
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RCC_PWR = _REG_BIT(0x24, 28),
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RCC_DAC = _REG_BIT(0x24, 29),
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RCC_COMP = _REG_BIT(0x24, 31),
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/* AHB peripherals */
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SCC_GPIOA = _REG_BIT(0x28, 0),
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SCC_GPIOB = _REG_BIT(0x28, 1),
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SCC_GPIOC = _REG_BIT(0x28, 2),
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SCC_GPIOD = _REG_BIT(0x28, 3),
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SCC_GPIOE = _REG_BIT(0x28, 4),
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SCC_GPIOH = _REG_BIT(0x28, 5),
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SCC_GPIOF = _REG_BIT(0x28, 6),
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SCC_GPIOG = _REG_BIT(0x28, 7),
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SCC_CRC = _REG_BIT(0x28, 12),
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SCC_FLITF = _REG_BIT(0x28, 15),
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SCC_SRAM = _REG_BIT(0x28, 16),
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SCC_DMA1 = _REG_BIT(0x28, 24),
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SCC_DMA2 = _REG_BIT(0x28, 25),
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SCC_AES = _REG_BIT(0x28, 27),
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SCC_FSMC = _REG_BIT(0x28, 30),
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/* APB2 peripherals */
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SCC_SYSCFG = _REG_BIT(0x2c, 0),
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SCC_TIM9 = _REG_BIT(0x2c, 2),
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SCC_TIM10 = _REG_BIT(0x2c, 3),
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SCC_TIM11 = _REG_BIT(0x2c, 4),
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SCC_ADC1 = _REG_BIT(0x2c, 9),
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SCC_SDIO = _REG_BIT(0x2c, 11),
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SCC_SPI1 = _REG_BIT(0x2c, 12),
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SCC_USART1 = _REG_BIT(0x2c, 14),
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/* APB1 peripherals*/
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SCC_TIM2 = _REG_BIT(0x24, 0),
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SCC_TIM3 = _REG_BIT(0x24, 1),
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SCC_TIM4 = _REG_BIT(0x24, 2),
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SCC_TIM5 = _REG_BIT(0x24, 3),
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SCC_TIM6 = _REG_BIT(0x24, 4),
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SCC_TIM7 = _REG_BIT(0x24, 5),
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SCC_LCD = _REG_BIT(0x24, 9),
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SCC_WWDG = _REG_BIT(0x24, 11),
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SCC_SPI2 = _REG_BIT(0x24, 14),
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SCC_SPI3 = _REG_BIT(0x24, 15),
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SCC_USART2 = _REG_BIT(0x24, 17),
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SCC_USART3 = _REG_BIT(0x24, 18),
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SCC_UART4 = _REG_BIT(0x24, 19),
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SCC_UART5 = _REG_BIT(0x24, 20),
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SCC_I2C1 = _REG_BIT(0x24, 21),
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SCC_I2C2 = _REG_BIT(0x24, 22),
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SCC_USB = _REG_BIT(0x24, 23),
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SCC_PWR = _REG_BIT(0x24, 28),
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SCC_DAC = _REG_BIT(0x24, 29),
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SCC_COMP = _REG_BIT(0x24, 31),
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};
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enum rcc_periph_rst {
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/* AHB peripherals */
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RST_GPIOA = _REG_BIT(0x10, 0),
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RST_GPIOB = _REG_BIT(0x10, 1),
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RST_GPIOC = _REG_BIT(0x10, 2),
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RST_GPIOD = _REG_BIT(0x10, 3),
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RST_GPIOE = _REG_BIT(0x10, 4),
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RST_GPIOH = _REG_BIT(0x10, 5),
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RST_GPIOF = _REG_BIT(0x10, 6),
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RST_GPIOG = _REG_BIT(0x10, 7),
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RST_CRC = _REG_BIT(0x10, 12),
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RST_FLITF = _REG_BIT(0x10, 15),
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RST_DMA1 = _REG_BIT(0x10, 24),
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RST_DMA2 = _REG_BIT(0x10, 25),
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RST_AES = _REG_BIT(0x10, 27),
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RST_FSMC = _REG_BIT(0x10, 30),
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/* APB2 peripherals */
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RST_SYSCFG = _REG_BIT(0x14, 0),
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RST_TIM9 = _REG_BIT(0x14, 2),
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RST_TIM10 = _REG_BIT(0x14, 3),
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RST_TIM11 = _REG_BIT(0x14, 4),
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RST_ADC1 = _REG_BIT(0x14, 9),
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RST_SDIO = _REG_BIT(0x14, 11),
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RST_SPI1 = _REG_BIT(0x14, 12),
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RST_USART1 = _REG_BIT(0x14, 14),
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/* APB1 peripherals*/
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RST_TIM2 = _REG_BIT(0x18, 0),
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RST_TIM3 = _REG_BIT(0x18, 1),
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RST_TIM4 = _REG_BIT(0x18, 2),
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RST_TIM5 = _REG_BIT(0x18, 3),
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RST_TIM6 = _REG_BIT(0x18, 4),
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RST_TIM7 = _REG_BIT(0x18, 5),
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RST_LCD = _REG_BIT(0x18, 9),
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RST_WWDG = _REG_BIT(0x18, 11),
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RST_SPI2 = _REG_BIT(0x18, 14),
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RST_SPI3 = _REG_BIT(0x18, 15),
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RST_USART2 = _REG_BIT(0x18, 17),
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RST_USART3 = _REG_BIT(0x18, 18),
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RST_UART4 = _REG_BIT(0x18, 19),
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RST_UART5 = _REG_BIT(0x18, 20),
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RST_I2C1 = _REG_BIT(0x18, 21),
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RST_I2C2 = _REG_BIT(0x18, 22),
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RST_USB = _REG_BIT(0x18, 23),
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RST_PWR = _REG_BIT(0x18, 28),
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RST_DAC = _REG_BIT(0x18, 29),
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RST_COMP = _REG_BIT(0x18, 31),
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};
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#include <libopencm3/stm32/common/rcc_common_all.h>
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BEGIN_DECLS
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void rcc_osc_ready_int_clear(osc_t osc);
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@@ -437,10 +589,6 @@ void rcc_css_enable(void);
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void rcc_css_disable(void);
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void rcc_osc_bypass_enable(osc_t osc);
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void rcc_osc_bypass_disable(osc_t osc);
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void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en);
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void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en);
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void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset);
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void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset);
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void rcc_set_sysclk_source(uint32_t clk);
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void rcc_set_pll_configuration(uint32_t source, uint32_t multiplier,
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uint32_t divisor);
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