Better method of reset and clock handling with RCC, support L1, F1, F2, F3, F4
This commit is contained in:
BuFran
committed by
Piotr Esden-Tempski
Piotr Esden-Tempski
parent
33f75a529d
commit
723e1a69bd
@@ -495,30 +495,159 @@ extern uint32_t rcc_ppre2_frequency;
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/* --- Function prototypes ------------------------------------------------- */
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typedef enum {
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enum rcc_osc {
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PLL, PLL2, PLL3, HSE, HSI, LSE, LSI
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} osc_t;
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};
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#define _REG_BIT(base, bit) (((base) << 5) + (bit))
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/* V = value line F100
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* N = standard line F101, F102, F103
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* C = communication line F105, F107
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*/
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enum rcc_periph_clken {
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/* AHB peripherals */
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RCC_DMA1 = _REG_BIT(0x14, 0),/*VNC*/
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RCC_DMA2 = _REG_BIT(0x14, 1),/*VNC*/
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RCC_SRAM = _REG_BIT(0x14, 2),/*VNC*/
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RCC_FLTF = _REG_BIT(0x14, 4),/*VNC*/
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RCC_CRC = _REG_BIT(0x14, 6),/*VNC*/
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RCC_FSMC = _REG_BIT(0x14, 8),/*VN-*/
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RCC_SDIO = _REG_BIT(0x14, 10),/*-N-*/
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RCC_OTGFS = _REG_BIT(0x14, 12),/*--C*/
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RCC_ETHMAC = _REG_BIT(0x14, 14),/*--C*/
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RCC_ETHMACTX = _REG_BIT(0x14, 15),/*--C*/
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RCC_ETHMACRX = _REG_BIT(0x14, 16),/*--C*/
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/* APB2 peripherals */
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RCC_AFIO = _REG_BIT(0x18, 0),/*VNC*/
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RCC_GPIOA = _REG_BIT(0x18, 2),/*VNC*/
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RCC_GPIOB = _REG_BIT(0x18, 3),/*VNC*/
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RCC_GPIOC = _REG_BIT(0x18, 4),/*VNC*/
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RCC_GPIOD = _REG_BIT(0x18, 5),/*VNC*/
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RCC_GPIOE = _REG_BIT(0x18, 6),/*VNC*/
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RCC_GPIOF = _REG_BIT(0x18, 7),/*VN-*/
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RCC_GPIOG = _REG_BIT(0x18, 8),/*VN-*/
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RCC_ADC1 = _REG_BIT(0x18, 9),/*VNC*/
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RCC_ADC2 = _REG_BIT(0x18, 10),/*-NC*/
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RCC_TIM1 = _REG_BIT(0x18, 11),/*VNC*/
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RCC_SPI1 = _REG_BIT(0x18, 12),/*VNC*/
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RCC_TIM8 = _REG_BIT(0x18, 13),/*-N-*/
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RCC_USART1 = _REG_BIT(0x18, 14),/*VNC*/
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RCC_ADC3 = _REG_BIT(0x18, 15),/*-N-*/
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RCC_TIM15 = _REG_BIT(0x18, 16),/*V--*/
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RCC_TIM16 = _REG_BIT(0x18, 17),/*V--*/
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RCC_TIM17 = _REG_BIT(0x18, 18),/*V--*/
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RCC_TIM9 = _REG_BIT(0x18, 19),/*-N-*/
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RCC_TIM10 = _REG_BIT(0x18, 20),/*-N-*/
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RCC_TIM11 = _REG_BIT(0x18, 21),/*-N-*/
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/* APB1 peripherals */
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RCC_TIM2 = _REG_BIT(0x1C, 0),/*VNC*/
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RCC_TIM3 = _REG_BIT(0x1C, 1),/*VNC*/
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RCC_TIM4 = _REG_BIT(0x1C, 2),/*VNC*/
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RCC_TIM5 = _REG_BIT(0x1C, 3),/*VNC*/
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RCC_TIM6 = _REG_BIT(0x1C, 4),/*VNC*/
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RCC_TIM7 = _REG_BIT(0x1C, 5),/*VNC*/
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RCC_TIM12 = _REG_BIT(0x1C, 6),/*VN-*/
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RCC_TIM13 = _REG_BIT(0x1C, 7),/*VN-*/
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RCC_TIM14 = _REG_BIT(0x1C, 8),/*VN-*/
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RCC_WWDG = _REG_BIT(0x1C, 11),/*VNC*/
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RCC_SPI2 = _REG_BIT(0x1C, 14),/*VNC*/
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RCC_SPI3 = _REG_BIT(0x1C, 15),/*VNC*/
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RCC_USART2 = _REG_BIT(0x1C, 17),/*VNC*/
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RCC_USART3 = _REG_BIT(0x1C, 18),/*VNC*/
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RCC_UART4 = _REG_BIT(0x1C, 19),/*VNC*/
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RCC_UART5 = _REG_BIT(0x1C, 20),/*VNC*/
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RCC_I2C1 = _REG_BIT(0x1C, 21),/*VNC*/
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RCC_I2C2 = _REG_BIT(0x1C, 22),/*VNC*/
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RCC_USB = _REG_BIT(0x1C, 23),/*-N-*/
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RCC_CAN = _REG_BIT(0x1C, 24),/*-N-*/
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RCC_CAN1 = _REG_BIT(0x1C, 24),/*--C*/
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RCC_CAN2 = _REG_BIT(0x1C, 25),/*--C*/
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RCC_BKP = _REG_BIT(0x1C, 27),/*VNC*/
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RCC_PWR = _REG_BIT(0x1C, 28),/*VNC*/
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RCC_DAC = _REG_BIT(0x1C, 29),/*VNC*/
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RCC_CEC = _REG_BIT(0x1C, 30),/*V--*/
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};
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enum rcc_periph_rst {
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/* AHB peripherals */
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RST_OTGFS = _REG_BIT(0x28, 12),/*--C*/
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RST_ETHMAC = _REG_BIT(0x28, 14),/*--C*/
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/* APB2 peripherals */
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RST_AFIO = _REG_BIT(0x0c, 0),/*VNC*/
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RST_GPIOA = _REG_BIT(0x0c, 2),/*VNC*/
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RST_GPIOB = _REG_BIT(0x0c, 3),/*VNC*/
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RST_GPIOC = _REG_BIT(0x0c, 4),/*VNC*/
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RST_GPIOD = _REG_BIT(0x0c, 5),/*VNC*/
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RST_GPIOE = _REG_BIT(0x0c, 6),/*VNC*/
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RST_GPIOF = _REG_BIT(0x0c, 7),/*VN-*/
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RST_GPIOG = _REG_BIT(0x0c, 8),/*VN-*/
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RST_ADC1 = _REG_BIT(0x0c, 9),/*VNC*/
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RST_ADC2 = _REG_BIT(0x0c, 10),/*-NC*/
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RST_TIM1 = _REG_BIT(0x0c, 11),/*VNC*/
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RST_SPI1 = _REG_BIT(0x0c, 12),/*VNC*/
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RST_TIM8 = _REG_BIT(0x0c, 13),/*-N-*/
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RST_USART1 = _REG_BIT(0x0c, 14),/*VNC*/
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RST_ADC3 = _REG_BIT(0x0c, 15),/*-N-*/
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RST_TIM15 = _REG_BIT(0x0c, 16),/*V--*/
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RST_TIM16 = _REG_BIT(0x0c, 17),/*V--*/
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RST_TIM17 = _REG_BIT(0x0c, 18),/*V--*/
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RST_TIM9 = _REG_BIT(0x0c, 19),/*-N-*/
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RST_TIM10 = _REG_BIT(0x0c, 20),/*-N-*/
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RST_TIM11 = _REG_BIT(0x0c, 21),/*-N-*/
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/* APB1 peripherals */
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RST_TIM2 = _REG_BIT(0x10, 0),/*VNC*/
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RST_TIM3 = _REG_BIT(0x10, 1),/*VNC*/
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RST_TIM4 = _REG_BIT(0x10, 2),/*VNC*/
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RST_TIM5 = _REG_BIT(0x10, 3),/*VNC*/
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RST_TIM6 = _REG_BIT(0x10, 4),/*VNC*/
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RST_TIM7 = _REG_BIT(0x10, 5),/*VNC*/
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RST_TIM12 = _REG_BIT(0x10, 6),/*VN-*/
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RST_TIM13 = _REG_BIT(0x10, 7),/*VN-*/
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RST_TIM14 = _REG_BIT(0x10, 8),/*VN-*/
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RST_WWDG = _REG_BIT(0x10, 11),/*VNC*/
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RST_SPI2 = _REG_BIT(0x10, 14),/*VNC*/
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RST_SPI3 = _REG_BIT(0x10, 15),/*VNC*/
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RST_USART2 = _REG_BIT(0x10, 17),/*VNC*/
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RST_USART3 = _REG_BIT(0x10, 18),/*VNC*/
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RST_UART4 = _REG_BIT(0x10, 19),/*VNC*/
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RST_UART5 = _REG_BIT(0x10, 20),/*VNC*/
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RST_I2C1 = _REG_BIT(0x10, 21),/*VNC*/
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RST_I2C2 = _REG_BIT(0x10, 22),/*VNC*/
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RST_USB = _REG_BIT(0x10, 23),/*-N-*/
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RST_CAN = _REG_BIT(0x10, 24),/*-N-*/
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RST_CAN1 = _REG_BIT(0x10, 24),/*--C*/
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RST_CAN2 = _REG_BIT(0x10, 25),/*--C*/
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RST_BKP = _REG_BIT(0x10, 27),/*VNC*/
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RST_PWR = _REG_BIT(0x10, 28),/*VNC*/
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RST_DAC = _REG_BIT(0x10, 29),/*VNC*/
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RST_CEC = _REG_BIT(0x10, 30),/*V--*/
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};
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#include <libopencm3/stm32/common/rcc_common_all.h>
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BEGIN_DECLS
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void rcc_osc_ready_int_clear(osc_t osc);
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void rcc_osc_ready_int_enable(osc_t osc);
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void rcc_osc_ready_int_disable(osc_t osc);
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int rcc_osc_ready_int_flag(osc_t osc);
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void rcc_osc_ready_int_clear(enum rcc_osc osc);
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void rcc_osc_ready_int_enable(enum rcc_osc osc);
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void rcc_osc_ready_int_disable(enum rcc_osc osc);
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int rcc_osc_ready_int_flag(enum rcc_osc osc);
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void rcc_css_int_clear(void);
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int rcc_css_int_flag(void);
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void rcc_wait_for_osc_ready(osc_t osc);
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void rcc_osc_on(osc_t osc);
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void rcc_osc_off(osc_t osc);
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void rcc_wait_for_osc_ready(enum rcc_osc osc);
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void rcc_osc_on(enum rcc_osc osc);
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void rcc_osc_off(enum rcc_osc osc);
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void rcc_css_enable(void);
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void rcc_css_disable(void);
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void rcc_set_mco(uint32_t mcosrc);
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void rcc_osc_bypass_enable(osc_t osc);
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void rcc_osc_bypass_disable(osc_t osc);
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void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en);
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void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en);
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void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset);
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void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset);
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void rcc_osc_bypass_enable(enum rcc_osc osc);
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void rcc_osc_bypass_disable(enum rcc_osc osc);
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void rcc_set_sysclk_source(uint32_t clk);
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void rcc_set_pll_multiplication_factor(uint32_t mul);
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void rcc_set_pll2_multiplication_factor(uint32_t mul);
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@@ -147,7 +147,7 @@ typedef enum {
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BEGIN_DECLS
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void rtc_awake_from_off(osc_t clock_source);
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void rtc_awake_from_off(enum rcc_osc clock_source);
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void rtc_enter_config_mode(void);
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void rtc_exit_config_mode(void);
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void rtc_set_alarm_time(uint32_t alarm_time);
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@@ -163,7 +163,7 @@ void rtc_interrupt_disable(rtcflag_t flag_val);
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void rtc_clear_flag(rtcflag_t flag_val);
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uint32_t rtc_check_flag(rtcflag_t flag_val);
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void rtc_awake_from_standby(void);
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void rtc_auto_awake(osc_t clock_source, uint32_t prescale_val);
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void rtc_auto_awake(enum rcc_osc clock_source, uint32_t prescale_val);
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END_DECLS
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