diff --git a/include/libopencm3/stm32/common/adc_common_v2.h b/include/libopencm3/stm32/common/adc_common_v2.h
index bd3845a1..cfb5a17d 100644
--- a/include/libopencm3/stm32/common/adc_common_v2.h
+++ b/include/libopencm3/stm32/common/adc_common_v2.h
@@ -150,9 +150,6 @@ specific memorymap.h header before including this header file.*/
 #define ADC_CFGR1_EXTEN_BOTH_EDGES	(0x3 << 10)
 /**@}*/
 
-/** ALIGN: Data alignment */
-#define ADC_CFGR1_ALIGN		(1 << 5)
-
 #define ADC_CFGR1_RES_MASK	(0x3 << 3)
 /** @defgroup adc_cfgr1_res RES: Data resolution
 @{*/
diff --git a/include/libopencm3/stm32/common/adc_common_v2_multi.h b/include/libopencm3/stm32/common/adc_common_v2_multi.h
index 374889b1..901c65a6 100644
--- a/include/libopencm3/stm32/common/adc_common_v2_multi.h
+++ b/include/libopencm3/stm32/common/adc_common_v2_multi.h
@@ -143,11 +143,6 @@ specific memorymap.h header before including this header file.*/
 #define ADC_CFGR1_DISCNUM_MASK  (0x7 << ADC_CFGR1_DISCNUM_SHIFT)
 #define ADC_CFGR1_DISCNUM_VAL(x)	(((x) - 1) << ADC_CFGR1_DISCNUM_SHIFT)
 
-/* EXTSEL[3:0]: External trigger selection for regular group */
-#define ADC_CFGR1_EXTSEL_SHIFT		6
-#define ADC_CFGR1_EXTSEL_MASK		(0xf << ADC_CFGR1_EXTSEL_SHIFT)
-#define ADC_CFGR1_EXTSEL_VAL(x)		((x) << ADC_CFGR1_EXTSEL_SHIFT)
-
 /* ADC_SQRx Values: Regular Sequence ordering------------------------------- */
 
 #define ADC_SQR1_L_SHIFT		0
diff --git a/include/libopencm3/stm32/common/adc_common_v2_single.h b/include/libopencm3/stm32/common/adc_common_v2_single.h
index 32616cf4..71db68d9 100644
--- a/include/libopencm3/stm32/common/adc_common_v2_single.h
+++ b/include/libopencm3/stm32/common/adc_common_v2_single.h
@@ -58,11 +58,6 @@ specific memorymap.h header before including this header file.*/
 /** Auto off mode */
 #define ADC_CFGR1_AUTOFF		(1 << 15)
 
-#define ADC_CFGR1_EXTSEL_SHIFT		6
-#define ADC_CFGR1_EXTSEL		(0x7 << ADC_CFGR1_EXTSEL_SHIFT)
-/** EXTSEL[2:0]: External trigger selection for regular group */
-#define ADC_CFGR1_EXTSEL_VAL(x)		((x) << ADC_CFGR1_EXTSEL_SHIFT)
-
 /** SCANDIR: Scan Sequence Direction: Upwards Scan (0), Downwards(1) */
 #define ADC_CFGR1_SCANDIR		(1 << 2)
 /**@}*/
diff --git a/include/libopencm3/stm32/f0/adc.h b/include/libopencm3/stm32/f0/adc.h
index bc88a578..543bd5ae 100644
--- a/include/libopencm3/stm32/f0/adc.h
+++ b/include/libopencm3/stm32/f0/adc.h
@@ -71,6 +71,16 @@
 /* Register values                                                           */
 /*****************************************************************************/
 
+/* ADC_CFGR1 Values ---------------------------------------------------------*/
+
+/** ALIGN: Data alignment */
+#define ADC_CFGR1_ALIGN			(1 << 5)
+
+/* EXTSEL[2:0]: External trigger selection for regular group */
+#define ADC_CFGR1_EXTSEL_SHIFT		6
+#define ADC_CFGR1_EXTSEL		(0x7 << ADC_CFGR1_EXTSEL_SHIFT)
+#define ADC_CFGR1_EXTSEL_VAL(x)		((x) << ADC_CFGR1_EXTSEL_SHIFT)
+
 /* ADC_CFGR2 Values ---------------------------------------------------------*/
 
 #define ADC_CFGR2_CKMODE_SHIFT		30
diff --git a/include/libopencm3/stm32/f3/adc.h b/include/libopencm3/stm32/f3/adc.h
index 5465cf72..067822f6 100644
--- a/include/libopencm3/stm32/f3/adc.h
+++ b/include/libopencm3/stm32/f3/adc.h
@@ -209,6 +209,16 @@
 #define ADC_CR_ADVREGEN_DISABLE		(0x2 << 28)
 #define ADC_CR_ADVREGEN_MASK		(0x3 << 28)
 
+/* ADC_CFGR1 Values ---------------------------------------------------------*/
+
+/** ALIGN: Data alignment */
+#define ADC_CFGR1_ALIGN			(1 << 5)
+
+/* EXTSEL[2:0]: External trigger selection for regular group */
+#define ADC_CFGR1_EXTSEL_SHIFT		6
+#define ADC_CFGR1_EXTSEL_MASK		(0xf << ADC_CFGR1_EXTSEL_SHIFT)
+#define ADC_CFGR1_EXTSEL_VAL(x)		((x) << ADC_CFGR1_EXTSEL_SHIFT)
+
 /****************************************************************************/
 /* ADC_SMPRx ADC Sample Time Selection for Channels */
 /** @defgroup adc_sample ADC Sample Time Selection values
diff --git a/include/libopencm3/stm32/g0/adc.h b/include/libopencm3/stm32/g0/adc.h
index b40e32b5..e2b65d35 100644
--- a/include/libopencm3/stm32/g0/adc.h
+++ b/include/libopencm3/stm32/g0/adc.h
@@ -121,6 +121,14 @@
 /** @addtogroup adc_cfgr1
 @{*/
 
+/** ALIGN: Data alignment */
+#define ADC_CFGR1_ALIGN				(1 << 5)
+
+/* EXTSEL[2:0]: External trigger selection for regular group */
+#define ADC_CFGR1_EXTSEL_SHIFT			6
+#define ADC_CFGR1_EXTSEL			(0x7 << ADC_CFGR1_EXTSEL_SHIFT)
+#define ADC_CFGR1_EXTSEL_VAL(x)			((x) << ADC_CFGR1_EXTSEL_SHIFT)
+
 /** CHSELRMOD: Mode Selection of the ADC_CHSELR register */
 #define ADC_CFGR1_CHSELRMOD			(1 << 21)
 
diff --git a/include/libopencm3/stm32/l0/adc.h b/include/libopencm3/stm32/l0/adc.h
index 7fd99f38..102ada5e 100644
--- a/include/libopencm3/stm32/l0/adc.h
+++ b/include/libopencm3/stm32/l0/adc.h
@@ -57,6 +57,16 @@
 #define ADC_CALFACT(adc)	MMIO32((adc) + 0xB4)
 
 /* Register values */
+/* ADC_CFGR1 Values ---------------------------------------------------------*/
+
+/** ALIGN: Data alignment */
+#define ADC_CFGR1_ALIGN			(1 << 5)
+
+/* EXTSEL[2:0]: External trigger selection for regular group */
+#define ADC_CFGR1_EXTSEL_SHIFT		6
+#define ADC_CFGR1_EXTSEL		(0x7 << ADC_CFGR1_EXTSEL_SHIFT)
+#define ADC_CFGR1_EXTSEL_VAL(x)		((x) << ADC_CFGR1_EXTSEL_SHIFT)
+
 /* ADC_CFGR2 Values ---------------------------------------------------------*/
 
 #define ADC_CFGR2_CKMODE_SHIFT		30
diff --git a/include/libopencm3/stm32/l4/adc.h b/include/libopencm3/stm32/l4/adc.h
index e01852fd..572c6f31 100644
--- a/include/libopencm3/stm32/l4/adc.h
+++ b/include/libopencm3/stm32/l4/adc.h
@@ -62,6 +62,16 @@
 /* ADVREGEN: Voltage regulator enable bit */
 #define ADC_CR_ADVREGEN		(1 << 28)
 
+/* ADC_CFGR1 Values ---------------------------------------------------------*/
+
+/** ALIGN: Data alignment */
+#define ADC_CFGR1_ALIGN			(1 << 5)
+
+/* EXTSEL[2:0]: External trigger selection for regular group */
+#define ADC_CFGR1_EXTSEL_SHIFT		6
+#define ADC_CFGR1_EXTSEL_MASK		(0xf << ADC_CFGR1_EXTSEL_SHIFT)
+#define ADC_CFGR1_EXTSEL_VAL(x)		((x) << ADC_CFGR1_EXTSEL_SHIFT)
+
 
 /****************************************************************************/
 /* ADC_SMPRx ADC Sample Time Selection for Channels */