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stm32f7: rcc: fixed wrong constants, added more settings, clock setup refactoring

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This commit is contained in:
Matthew Lai
2017-04-22 02:30:54 +01:00
committed by Karl Palsson
parent ba0e0424b5
commit 68fce5a0ab
2 changed files with 144 additions and 13 deletions
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13
include/libopencm3/stm32/f7/rcc.h
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@@ -607,11 +607,16 @@ extern uint32_t rcc_apb2_frequency;
enum rcc_clock_3v3 {
RCC_CLOCK_3V3_216MHZ,
RCC_CLOCK_3V3_168MHZ,
RCC_CLOCK_3V3_120MHZ,
RCC_CLOCK_3V3_72MHZ,
RCC_CLOCK_3V3_48MHZ,
RCC_CLOCK_3V3_24MHZ,
RCC_CLOCK_3V3_END
};
struct rcc_clock_scale {
uint8_t pllm;
// PLLM not specified here because it depends on input clock freq.
uint16_t plln;
uint8_t pllp;
uint8_t pllq;
@@ -621,11 +626,12 @@ struct rcc_clock_scale {
uint8_t ppre2;
enum pwr_vos_scale vos_scale;
uint8_t overdrive;
uint32_t ahb_frequency;
uint32_t apb1_frequency;
uint32_t apb2_frequency;
};
extern const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END];
extern const struct rcc_clock_scale rcc_3v3[RCC_CLOCK_3V3_END];
enum rcc_osc {
RCC_PLL,
@@ -932,7 +938,8 @@ void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp,
void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp,
uint32_t pllq);
uint32_t rcc_system_clock_source(void);
void rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock);
void rcc_clock_setup_hse(const struct rcc_clock_scale *clock, uint32_t hse_mhz);
void rcc_clock_setup_hsi(const struct rcc_clock_scale *clock);
END_DECLS
#endif