diff --git a/include/libopencm3/stm32/f3/crc.h b/include/libopencm3/stm32/f3/crc.h index 8e76f354..96a56d0c 100644 --- a/include/libopencm3/stm32/f3/crc.h +++ b/include/libopencm3/stm32/f3/crc.h @@ -1,15 +1,15 @@ /** @defgroup crc_defines CRC Defines - -@brief libopencm3 Defined Constants and Types for the STM32F3xx CRC -Generator - -@ingroup STM32F3xx_defines - -@version 1.0.0 - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license + * + * @brief libopencm3 Defined Constants and Types for the STM32F3xx CRC + * Generator + * + * @ingroup STM32F3xx_defines + * + * @version 1.0.0 + * + * @date 18 August 2012 + * + * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. diff --git a/include/libopencm3/stm32/f3/dac.h b/include/libopencm3/stm32/f3/dac.h index 8fe241ee..9bb8b160 100644 --- a/include/libopencm3/stm32/f3/dac.h +++ b/include/libopencm3/stm32/f3/dac.h @@ -1,14 +1,14 @@ /** @defgroup dac_defines DAC Defines - -@brief Defined Constants and Types for the STM32F3xx DAC - -@ingroup STM32F3xx_defines - -@version 1.0.0 - -@date 5 December 2012 - -LGPL License Terms @ref lgpl_license + * + * @brief Defined Constants and Types for the STM32F3xx DAC + * + * @ingroup STM32F3xx_defines + * + * @version 1.0.0 + * + * @date 5 December 2012 + * + * LGPL License Terms @ref lgpl_license */ /* diff --git a/include/libopencm3/stm32/f3/dma.h b/include/libopencm3/stm32/f3/dma.h index e96005d9..9b4d4218 100644 --- a/include/libopencm3/stm32/f3/dma.h +++ b/include/libopencm3/stm32/f3/dma.h @@ -1,14 +1,14 @@ /** @defgroup dma_defines DMA Defines - -@ingroup STM32F3xx_defines - -@brief Defined Constants and Types for the STM32F3xx DMA Controller - -@version 1.0.0 - -@date 30 November 2012 - -LGPL License Terms @ref lgpl_license + * + * @ingroup STM32F3xx_defines + * + * @brief Defined Constants and Types for the STM32F3xx DMA Controller + * + * @version 1.0.0 + * + * @date 30 November 2012 + * + * LGPL License Terms @ref lgpl_license */ /* diff --git a/include/libopencm3/stm32/f3/gpio.h b/include/libopencm3/stm32/f3/gpio.h index 4234a523..4a88a33c 100644 --- a/include/libopencm3/stm32/f3/gpio.h +++ b/include/libopencm3/stm32/f3/gpio.h @@ -1,14 +1,15 @@ /** @defgroup gpio_defines GPIO Defines - -@brief Defined Constants and Types for the STM32F3xx General Purpose I/O - -@ingroup STM32F3xx_defines - -@version 1.0.0 - -@date 1 July 2012 - -LGPL License Terms @ref lgpl_license + * + * @brief Defined Constants and Types for the STM32F3xx General Purpose + * I/O + * + * @ingroup STM32F3xx_defines + * + * @version 1.0.0 + * + * @date 1 July 2012 + * + * LGPL License Terms @ref lgpl_license */ /* diff --git a/include/libopencm3/stm32/f3/i2c.h b/include/libopencm3/stm32/f3/i2c.h index 652f57e3..4f91c519 100644 --- a/include/libopencm3/stm32/f3/i2c.h +++ b/include/libopencm3/stm32/f3/i2c.h @@ -1,14 +1,14 @@ /** @defgroup i2c_defines I2C Defines - -@brief Defined Constants and Types for the STM32F4xx I2C - -@ingroup STM32F4xx_defines - -@version 1.0.0 - -@date 12 October 2012 - -LGPL License Terms @ref lgpl_license + * + * @brief Defined Constants and Types for the STM32F4xx I2C + * + * @ingroup STM32F4xx_defines + * + * @version 1.0.0 + * + * @date 12 October 2012 + * + * LGPL License Terms @ref lgpl_license */ /* @@ -41,9 +41,8 @@ LGPL License Terms @ref lgpl_license /* I2C register base addresses (for convenience) */ /*****************************************************************************/ /** @defgroup i2c_reg_base I2C register base address -@ingroup i2c_defines - -@{*/ + * @ingroup i2c_defines + * @{*/ #define I2C1 I2C1_BASE #define I2C2 I2C2_BASE /**@}*/ diff --git a/include/libopencm3/stm32/f3/iwdg.h b/include/libopencm3/stm32/f3/iwdg.h index 24423b76..226c0a2e 100644 --- a/include/libopencm3/stm32/f3/iwdg.h +++ b/include/libopencm3/stm32/f3/iwdg.h @@ -1,15 +1,15 @@ /** @defgroup iwdg_defines IWDG Defines - -@brief Defined Constants and Types for the STM32F3xx Independent Watchdog -Timer - -@ingroup STM32F3xx_defines - -@version 1.0.0 - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license + * + * @brief Defined Constants and Types for the STM32F3xx Independent Watchdog + * Timer + * + * @ingroup STM32F3xx_defines + * + * @version 1.0.0 + * + * @date 18 August 2012 + * + * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. diff --git a/include/libopencm3/stm32/f3/spi.h b/include/libopencm3/stm32/f3/spi.h index 6b13b3a5..51220b4b 100644 --- a/include/libopencm3/stm32/f3/spi.h +++ b/include/libopencm3/stm32/f3/spi.h @@ -1,14 +1,14 @@ /** @defgroup spi_defines SPI Defines - -@brief Defined Constants and Types for the STM32F3xx SPI - -@ingroup STM32F3xx_defines - -@version 1.0.0 - -@date 5 December 2012 - -LGPL License Terms @ref lgpl_license + * + * @brief Defined Constants and Types for the STM32F3xx SPI + * + * @ingroup STM32F3xx_defines + * + * @version 1.0.0 + * + * @date 5 December 2012 + * + * LGPL License Terms @ref lgpl_license */ /* @@ -37,9 +37,9 @@ LGPL License Terms @ref lgpl_license /* DFF: Data frame format */ /****************************************************************************/ /** @defgroup spi_dff SPI data frame format -@ingroup spi_defines - -@{*/ + * @ingroup spi_defines + * + * @{*/ #define SPI_DR8(spi_base) MMIO8(spi_base + 0x0c) #define SPI1_DR8 SPI_DR8(SPI1_BASE) diff --git a/include/libopencm3/stm32/f3/timer.h b/include/libopencm3/stm32/f3/timer.h index 9e44e2ee..f8141026 100644 --- a/include/libopencm3/stm32/f3/timer.h +++ b/include/libopencm3/stm32/f3/timer.h @@ -1,16 +1,16 @@ /** @defgroup timer_defines Timer Defines - -@brief libopencm3 Defined Constants and Types for the STM32F3xx Timers - -@ingroup STM32F3xx_defines - -@version 1.0.0 - -@date 8 March 2013 - -@author @htmlonly © @endhtmlonly 2011 Fergus Noble - -LGPL License Terms @ref lgpl_license + * + * @brief libopencm3 Defined Constants and Types for the STM32F3xx Timers + * + * @ingroup STM32F3xx_defines + * + * @version 1.0.0 + * + * @date 8 March 2013 + * + * @author @htmlonly © @endhtmlonly 2011 Fergus Noble + * + * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. diff --git a/include/libopencm3/stm32/f3/usart.h b/include/libopencm3/stm32/f3/usart.h index 34f68a85..76089632 100644 --- a/include/libopencm3/stm32/f3/usart.h +++ b/include/libopencm3/stm32/f3/usart.h @@ -1,14 +1,14 @@ /** @defgroup usart_defines USART Defines - -@brief Defined Constants and Types for the STM32F3xx USART - -@ingroup STM32F3xx_defines - -@version 1.0.0 - -@date 5 December 2012 - -LGPL License Terms @ref lgpl_license + * + * @brief Defined Constants and Types for the STM32F3xx USART + * + * @ingroup STM32F3xx_defines + * + * @version 1.0.0 + * + * @date 5 December 2012 + * + * LGPL License Terms @ref lgpl_license */ /* diff --git a/lib/stm32/f3/adc.c b/lib/stm32/f3/adc.c index c868457a..e9f95528 100644 --- a/lib/stm32/f3/adc.c +++ b/lib/stm32/f3/adc.c @@ -1,67 +1,69 @@ /** @defgroup STM32F4xx_adc_file ADC - -@ingroup STM32F4xx - -@brief libopencm3 STM32F4xx Analog to Digital Converters - -@author @htmlonly © @endhtmlonly 2012 -Ken Sarkies - -@date 30 August 2012 - -This library supports the A/D Converter Control System in the STM32 series of -ARM Cortex Microcontrollers by ST Microelectronics. - -Devices can have up to three A/D converters each with their own set of -registers. However all the A/D converters share a common clock which is -prescaled from the APB2 clock by default by a minimum factor of 2 to a maximum -of 8. The ADC resolution can be set to 12, 10, 8 or 6 bits. - -Each A/D converter has up to 19 channels: -@li On ADC1 the analog channels 16 is internally connected to the temperature -sensor, channel 17 to VREFINT, and channel 18 to VBATT. -@li On ADC2 and ADC3 the analog channels 16 - 18 are not used. - -The conversions can occur as a one-off conversion whereby the process stops -once conversion is complete. The conversions can also be continuous wherein a -new conversion starts immediately the previous conversion has ended. - -Conversion can occur as a single channel conversion or a scan of a group of -channels in either continuous or one-off mode. If more than one channel is -converted in a scan group, DMA must be used to transfer the data as there is -only one result register available. An interrupt can be set to occur at the end -of conversion, which occurs after all channels have been scanned. - -A discontinuous mode allows a subgroup of group of a channels to be converted -in bursts of a given length. - -Injected conversions allow a second group of channels to be converted -separately from the regular group. An interrupt can be set to occur at the end -of conversion, which occurs after all channels have been scanned. - -@section adc_f4_api_ex Basic ADC Handling API. - -Example 1: Simple single channel conversion polled. Enable the peripheral clock -and ADC, reset ADC and set the prescaler divider. Set multiple mode to -independent. - -@code -gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO1); -rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_ADC1EN); -adc_set_clk_prescale(RCC_CFGR_ADCPRE_BY2); -adc_disable_scan_mode(ADC1); -adc_set_single_conversion_mode(ADC1); -adc_set_sample_time(ADC1, ADC_CHANNEL0, ADC_SMPR1_SMP_1DOT5CYC); -uint8_t channels[] = ADC_CHANNEL0; -adc_set_regular_sequence(ADC1, 1, channels); -adc_set_multi_mode(ADC_CCR_MULTI_INDEPENDENT); -adc_power_on(ADC1); -adc_start_conversion_regular(ADC1); -while (! adc_eoc(ADC1)); -reg16 = adc_read_regular(ADC1); -@endcode - -LGPL License Terms @ref lgpl_license + * + * @ingroup STM32F4xx + * + * @brief libopencm3 STM32F4xx Analog to Digital Converters + * + * @author @htmlonly © @endhtmlonly 2012 + * Ken Sarkies + * + * @date 30 August 2012 + * + * This library supports the A/D Converter Control System in the STM32 series + * of ARM Cortex Microcontrollers by ST Microelectronics. + * + * Devices can have up to three A/D converters each with their own set of + * registers. However all the A/D converters share a common clock which is + * prescaled from the APB2 clock by default by a minimum factor of 2 to a + * maximum of 8. The ADC resolution can be set to 12, 10, 8 or 6 bits. + * + * Each A/D converter has up to 19 channels: + * @li On ADC1 the analog channels 16 is internally connected to the + * temperature sensor, channel 17 to VREFINT, and channel 18 + * to VBATT. + * @li On ADC2 and ADC3 the analog channels 16 - 18 are not used. + * + * The conversions can occur as a one-off conversion whereby the process stops + * once conversion is complete. The conversions can also be continuous wherein + * a new conversion starts immediately the previous conversion has ended. + * + * Conversion can occur as a single channel conversion or a scan of a group of + * channels in either continuous or one-off mode. If more than one channel is + * converted in a scan group, DMA must be used to transfer the data as there is + * only one result register available. An interrupt can be set to occur at the + * end* + * of conversion, which occurs after all channels have been scanned. + * + * A discontinuous mode allows a subgroup of group of a channels to be + * converted in bursts of a given length. + * + * Injected conversions allow a second group of channels to be converted + * separately from the regular group. An interrupt can be set to occur at the + * end of conversion, which occurs after all channels have been scanned. + * + * @section adc_f4_api_ex Basic ADC Handling API. + * + * Example 1: Simple single channel conversion polled. Enable the peripheral + * clock and ADC, reset ADC and set the prescaler divider. Set multiple mode to + * independent. + * + * @code + * gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO1); + * rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_ADC1EN); + * adc_set_clk_prescale(RCC_CFGR_ADCPRE_BY2); + * adc_disable_scan_mode(ADC1); + * adc_set_single_conversion_mode(ADC1); + * adc_set_sample_time(ADC1, ADC_CHANNEL0, ADC_SMPR1_SMP_1DOT5CYC); + * uint8_t channels[] = ADC_CHANNEL0; + * adc_set_regular_sequence(ADC1, 1, channels); + * adc_set_multi_mode(ADC_CCR_MULTI_INDEPENDENT); + * adc_power_on(ADC1); + * adc_start_conversion_regular(ADC1); + * while (! adc_eoc(ADC1)); + * reg16 = adc_read_regular(ADC1); + * @endcode + * + * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. @@ -88,11 +90,11 @@ LGPL License Terms @ref lgpl_license /*---------------------------------------------------------------------------*/ /** @brief ADC Off - -Turn off the ADC to reduce power consumption to a few microamps. - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base + * + * Turn off the ADC to reduce power consumption to a few microamps. + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base */ void adc_off(uint32_t adc) @@ -102,14 +104,14 @@ void adc_off(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog for Regular Conversions - -The analog watchdog allows the monitoring of an analog signal between two -threshold levels. The thresholds must be preset. Comparison is done before data -alignment takes place, so the thresholds are left-aligned. - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -*/ + * + * The analog watchdog allows the monitoring of an analog signal between two + * threshold levels. The thresholds must be preset. Comparison is done before + * data alignment takes place, so the thresholds are left-aligned. + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base + */ void adc_enable_analog_watchdog_regular(uint32_t adc) { @@ -118,14 +120,14 @@ void adc_enable_analog_watchdog_regular(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog for Regular Conversions - -The analog watchdog allows the monitoring of an analog signal between two -threshold levels. The thresholds must be preset. Comparison is done before data -alignment takes place, so the thresholds are left-aligned. - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -*/ + * + * The analog watchdog allows the monitoring of an analog signal between two + * threshold levels. The thresholds must be preset. Comparison is done before + * data alignment takes place, so the thresholds are left-aligned. + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base + */ void adc_disable_analog_watchdog_regular(uint32_t adc) { ADC_CFGR(adc) &= ~ADC_CFGR_AWD1EN; @@ -133,14 +135,14 @@ void adc_disable_analog_watchdog_regular(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog for Injected Conversions - -The analog watchdog allows the monitoring of an analog signal between two -threshold levels. The thresholds must be preset. Comparison is done before data -alignment takes place, so the thresholds are left-aligned. - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -*/ + * + * The analog watchdog allows the monitoring of an analog signal between two + * threshold levels. The thresholds must be preset. Comparison is done before + * data alignment takes place, so the thresholds are left-aligned. + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base + */ void adc_enable_analog_watchdog_injected(uint32_t adc) { @@ -149,10 +151,10 @@ void adc_enable_analog_watchdog_injected(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Analog Watchdog for Injected Conversions - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -*/ + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base + */ void adc_disable_analog_watchdog_injected(uint32_t adc) { @@ -161,19 +163,19 @@ void adc_disable_analog_watchdog_injected(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Discontinuous Mode for Regular Conversions - -In this mode the ADC converts, on each trigger, a subgroup of up to 8 of the -defined regular channel group. The subgroup is defined by the number of -consecutive channels to be converted. After a subgroup has been converted the -next trigger will start conversion of the immediately following subgroup of the -same length or until the whole group has all been converted. When the the whole -group has been converted, the next trigger will restart conversion of the -subgroup at the beginning of the whole group. - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base @param[in] length Unsigned int8. Number of channels in the group -@ref adc_cr1_discnum -*/ + * + * In this mode the ADC converts, on each trigger, a subgroup of up to 8 of the + * defined regular channel group. The subgroup is defined by the number of + * consecutive channels to be converted. After a subgroup has been converted + * the next trigger will start conversion of the immediately following subgroup + * of the same length or until the whole group has all been converted. When the + * whole group has been converted, the next trigger will restart conversion of + * the subgroup at the beginning of the whole group. + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base @param[in] length Unsigned int8. Number of channels in the + * group @ref adc_cr1_discnum + */ void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length) { @@ -186,10 +188,10 @@ void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length) /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Discontinuous Mode for Regular Conversions - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -*/ + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base + */ void adc_disable_discontinuous_mode_regular(uint32_t adc) { @@ -198,14 +200,14 @@ void adc_disable_discontinuous_mode_regular(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Discontinuous Mode for Injected Conversions - -In this mode the ADC converts sequentially one channel of the defined group of -injected channels, cycling back to the first channel in the group once the -entire group has been converted. - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -*/ + * + * In this mode the ADC converts sequentially one channel of the defined group + * of injected channels, cycling back to the first channel in the group once + * the entire group has been converted. + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base + */ void adc_enable_discontinuous_mode_injected(uint32_t adc) { @@ -214,10 +216,10 @@ void adc_enable_discontinuous_mode_injected(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Discontinuous Mode for Injected Conversions - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -*/ + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base + */ void adc_disable_discontinuous_mode_injected(uint32_t adc) { @@ -226,14 +228,14 @@ void adc_disable_discontinuous_mode_injected(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Automatic Injected Conversions - -The ADC converts a defined injected group of channels immediately after the -regular channels have been converted. The external trigger on the injected -channels is disabled as required. - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -*/ + * + * The ADC converts a defined injected group of channels immediately after the + * regular channels have been converted. The external trigger on the injected + * channels is disabled as required. + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base + */ void adc_enable_automatic_injected_group_conversion(uint32_t adc) { @@ -243,10 +245,10 @@ void adc_enable_automatic_injected_group_conversion(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Automatic Injected Conversions - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -*/ + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base + */ void adc_disable_automatic_injected_group_conversion(uint32_t adc) { @@ -254,20 +256,21 @@ void adc_disable_automatic_injected_group_conversion(uint32_t adc) } /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog for All Regular and/or Injected Channels - -The analog watchdog allows the monitoring of an analog signal between two -threshold levels. The thresholds must be preset. Comparison is done before data -alignment takes place, so the thresholds are left-aligned. - -@note The analog watchdog must be enabled for either or both of the regular or -injected channels. If neither are enabled, the analog watchdog feature will be -disabled. -@ref adc_enable_analog_watchdog_injected, @ref -adc_enable_analog_watchdog_regular. - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -*/ + * + * The analog watchdog allows the monitoring of an analog signal between two + * threshold levels. The thresholds must be preset. Comparison is done before + * data alignment takes place, so the thresholds are left-aligned. + * + * @note The analog watchdog must be enabled for either or both of the regular + * or injected channels. If neither are enabled, the analog watchdog feature + * will be disabled. + * + * @ref adc_enable_analog_watchdog_injected, @ref + * adc_enable_analog_watchdog_regular. + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base + */ void adc_enable_analog_watchdog_on_all_channels(uint32_t adc) { @@ -276,21 +279,22 @@ void adc_enable_analog_watchdog_on_all_channels(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog for a Selected Channel - -The analog watchdog allows the monitoring of an analog signal between two -threshold levels. The thresholds must be preset. Comparison is done before data -alignment takes place, so the thresholds are left-aligned. - -@note The analog watchdog must be enabled for either or both of the regular or -injected channels. If neither are enabled, the analog watchdog feature will be -disabled. If both are enabled, the same channel number is monitored. -@ref adc_enable_analog_watchdog_injected, @ref -adc_enable_analog_watchdog_regular. - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -@param[in] channel Unsigned int8. ADC channel number @ref adc_watchdog_channel -*/ + * + * The analog watchdog allows the monitoring of an analog signal between two + * threshold levels. The thresholds must be preset. Comparison is done before + * data alignment takes place, so the thresholds are left-aligned. + * + * @note The analog watchdog must be enabled for either or both of the regular + * or injected channels. If neither are enabled, the analog watchdog feature + * will be disabled. If both are enabled, the same channel number is monitored + * @ref adc_enable_analog_watchdog_injected, @ref + * adc_enable_analog_watchdog_regular. + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base + * @param[in] channel Unsigned int8. ADC channel numbe + * @ref adc_watchdog_channel + */ void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t channel) @@ -306,14 +310,15 @@ void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, /*---------------------------------------------------------------------------*/ /** @brief ADC Set Scan Mode - -In this mode a conversion consists of a scan of the predefined set of channels, -regular and injected, each channel conversion immediately following the -previous one. It can use single, continuous or discontinuous mode. - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -*/ + * + * In this mode a conversion consists of a scan of the predefined set of + * channels, regular and injected, each channel conversion immediately + * following the previous one. It can use single, continuous or discontinuous + * mode. + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base + */ /* void adc_enable_scan_mode(uint32_t adc) @@ -324,10 +329,10 @@ void adc_enable_scan_mode(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Scan Mode - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -*/ + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base + */ /* void adc_disable_scan_mode(uint32_t adc) @@ -338,10 +343,10 @@ void adc_disable_scan_mode(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Injected End-Of-Conversion Interrupt - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -*/ + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base + */ void adc_enable_eoc_interrupt_injected(uint32_t adc) { @@ -350,10 +355,10 @@ void adc_enable_eoc_interrupt_injected(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Injected End-Of-Conversion Interrupt - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -*/ + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base + */ void adc_disable_eoc_interrupt_injected(uint32_t adc) { @@ -362,10 +367,10 @@ void adc_disable_eoc_interrupt_injected(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog Interrupt - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -*/ + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base + */ void adc_enable_all_awd_interrupt(uint32_t adc) { @@ -376,10 +381,10 @@ void adc_enable_all_awd_interrupt(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Analog Watchdog Interrupt - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -*/ + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base + */ void adc_disable_all_awd_interrupt(uint32_t adc) { @@ -390,10 +395,10 @@ void adc_disable_all_awd_interrupt(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Regular End-Of-Conversion Interrupt - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -*/ + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base + */ void adc_enable_eoc_interrupt(uint32_t adc) { @@ -402,10 +407,10 @@ void adc_enable_eoc_interrupt(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Disable Regular End-Of-Conversion Interrupt - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -*/ + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base + */ void adc_disable_eoc_interrupt(uint32_t adc) { @@ -414,13 +419,13 @@ void adc_disable_eoc_interrupt(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Software Triggered Conversion on Regular Channels - -This starts conversion on a set of defined regular channels. It is cleared by -hardware once conversion starts. - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -*/ + * + * This starts conversion on a set of defined regular channels. It is cleared + * by hardware once conversion starts. + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base + */ void adc_start_conversion_regular(uint32_t adc) { @@ -433,13 +438,13 @@ void adc_start_conversion_regular(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Software Triggered Conversion on Injected Channels - -This starts conversion on a set of defined injected channels. It is cleared by -hardware once conversion starts. - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -*/ + * + * This starts conversion on a set of defined injected channels. It is cleared + * by hardware once conversion starts. + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base + */ void adc_start_conversion_injected(uint32_t adc) { @@ -452,10 +457,10 @@ void adc_start_conversion_injected(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Set the Data as Left Aligned - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -*/ + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base + */ void adc_set_left_aligned(uint32_t adc) { @@ -464,10 +469,10 @@ void adc_set_left_aligned(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Set the Data as Right Aligned - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -*/ + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base + */ void adc_set_right_aligned(uint32_t adc) { @@ -476,9 +481,10 @@ void adc_set_right_aligned(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Enable DMA Transfers - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -*/ + * + * @param[in] adc Unsigned int32. ADC block register address base + * @ref adc_reg_base + */ void adc_enable_dma(uint32_t adc) { @@ -487,9 +493,10 @@ void adc_enable_dma(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Disable DMA Transfers - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -*/ + * + * @param[in] adc Unsigned int32. ADC block register address base + * @ref adc_reg_base + */ void adc_disable_dma(uint32_t adc) { @@ -498,12 +505,14 @@ void adc_disable_dma(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Continuous Conversion Mode - -In this mode the ADC starts a new conversion of a single channel or a channel -group immediately following completion of the previous channel group conversion. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -*/ + * + * In this mode the ADC starts a new conversion of a single channel or a channel + * group immediately following completion of the previous channel group + * conversion. + * + * @param[in] adc Unsigned int32. ADC block register address base + * @ref adc_reg_base + */ void adc_set_continuous_conversion_mode(uint32_t adc) { @@ -512,12 +521,13 @@ void adc_set_continuous_conversion_mode(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Enable Single Conversion Mode - -In this mode the ADC performs a conversion of one channel or a channel group -and stops. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -*/ + * + * In this mode the ADC performs a conversion of one channel or a channel group + * and stops. + * + * @param[in] adc Unsigned int32. ADC block register address base + * @ref adc_reg_base + */ void adc_set_single_conversion_mode(uint32_t adc) { @@ -526,14 +536,16 @@ void adc_set_single_conversion_mode(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Set the Sample Time for a Single Channel - -The sampling time can be selected in ADC clock cycles from 1.5 to 239.5. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@param[in] channel Unsigned int8. ADC Channel integer 0..18 or from @ref -adc_channel -@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg -*/ + * + * The sampling time can be selected in ADC clock cycles from 1.5 to 239.5. + * + * @param[in] adc Unsigned int32. ADC block register address base + * @ref adc_reg_base + * @param[in] channel Unsigned int8. ADC Channel integer 0..18 or from + * @ref adc_channel + * @param[in] time Unsigned int8. Sampling time selection from + * @ref adc_sample_rg + */ void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time) { @@ -554,14 +566,15 @@ void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time) /*---------------------------------------------------------------------------*/ /** @brief ADC Set the Sample Time for All Channels - -The sampling time can be selected in ADC clock cycles from 1.5 to 239.5, same -for all channels. - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg -*/ + * + * The sampling time can be selected in ADC clock cycles from 1.5 to 239.5, + * same for all channels. + * + * @param[in] adc Unsigned int32. ADC block register address base + * @ref adc_reg_base + * @param[in] time Unsigned int8. Sampling time selection from + * @ref adc_sample_rg + */ void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time) { @@ -579,11 +592,11 @@ void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time) /*---------------------------------------------------------------------------*/ /** @brief ADC Set Analog Watchdog Upper Threshold - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -@param[in] threshold Unsigned int8. Upper threshold value -*/ + * + * @param[in] adc Unsigned int32. ADC block register address base + * @ref adc_reg_base + * @param[in] threshold Unsigned int8. Upper threshold value + */ void adc_set_watchdog_high_threshold(uint32_t adc, uint8_t threshold) { @@ -598,10 +611,11 @@ void adc_set_watchdog_high_threshold(uint32_t adc, uint8_t threshold) /*---------------------------------------------------------------------------*/ /** @brief ADC Set Analog Watchdog Lower Threshold - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@param[in] threshold Unsigned int8. Lower threshold value -*/ + * + * @param[in] adc Unsigned int32. ADC block register address base + * @ref adc_reg_base + * @param[in] threshold Unsigned int8. Lower threshold value + */ void adc_set_watchdog_low_threshold(uint32_t adc, uint8_t threshold) { @@ -616,15 +630,18 @@ void adc_set_watchdog_low_threshold(uint32_t adc, uint8_t threshold) /*---------------------------------------------------------------------------*/ /** @brief ADC Set a Regular Channel Conversion Sequence - -Define a sequence of channels to be converted as a regular group with a length -from 1 to 16 channels. If this is called during conversion, the current -conversion is reset and conversion begins again with the newly defined group. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@param[in] length Unsigned int8. Number of channels in the group. -@param[in] channel Unsigned int8[]. Set of channels in sequence, integers 0..18. -*/ + * + * Define a sequence of channels to be converted as a regular group with a + * length from 1 to 16 channels. If this is called during conversion, the + * current conversion is reset and conversion begins again with the newly + * defined group. + * + * @param[in] adc Unsigned int32. ADC block register address base + * @ref adc_reg_base + * @param[in] length Unsigned int8. Number of channels in the group. + * @param[in] channel Unsigned int8[]. Set of channels in sequence, integers + * 0..18. + */ void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[]) { @@ -660,15 +677,17 @@ void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[]) /*---------------------------------------------------------------------------*/ /** @brief ADC Set an Injected Channel Conversion Sequence - -Defines a sequence of channels to be converted as an injected group with a -length from 1 to 4 channels. If this is called during conversion, the current -conversion is reset and conversion begins again with the newly defined group. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@param[in] length Unsigned int8. Number of channels in the group. -@param[in] channel Unsigned int8[]. Set of channels in sequence, integers 0..18 -*/ + * + * Defines a sequence of channels to be converted as an injected group with a + * length from 1 to 4 channels. If this is called during conversion, the current + * conversion is reset and conversion begins again with the newly defined group. + * + * @param[in] adc Unsigned int32. ADC block register address base + * @ref adc_reg_base + * @param[in] length Unsigned int8. Number of channels in the group. + * @param[in] channel Unsigned int8[]. Set of channels in sequence, integers + * 0..18 + */ void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[]) { @@ -691,13 +710,14 @@ void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[]) /*---------------------------------------------------------------------------*/ /** @brief ADC Read the End-of-Conversion Flag - -This flag is set after all channels of a regular or injected group have been -converted. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@returns bool. End of conversion flag. -*/ + * + * This flag is set after all channels of a regular or injected group have been + * converted. + * + * @param[in] adc Unsigned int32. ADC block register address base + * @ref adc_reg_base + * @returns bool. End of conversion flag. + */ bool adc_eoc(uint32_t adc) { @@ -706,12 +726,14 @@ bool adc_eoc(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Read the End-of-Conversion Flag for Injected Conversion - -This flag is set after all channels of an injected group have been converted. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@returns bool. End of conversion flag. -*/ + * + * This flag is set after all channels of an injected group have been + * converted. + * + * @param[in] adc Unsigned int32. ADC block register address base + * @ref adc_reg_base + * @returns bool. End of conversion flag. + */ bool adc_eoc_injected(uint32_t adc) { @@ -720,14 +742,15 @@ bool adc_eoc_injected(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Read from the Regular Conversion Result Register - -The result read back is 12 bits, right or left aligned within the first 16 bits. -For ADC1 only, the higher 16 bits will hold the result from ADC2 if -an appropriate dual mode has been set @see adc_set_dual_mode. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@returns Unsigned int32 conversion result. -*/ + * + * The result read back is 12 bits, right or left aligned within the first + * 16 bits. For ADC1 only, the higher 16 bits will hold the result from ADC2 if + * an appropriate dual mode has been set @see adc_set_dual_mode. + * + * @param[in] adc Unsigned int32. ADC block register address base + * @ref adc_reg_base + * @returns Unsigned int32 conversion result. + */ uint32_t adc_read_regular(uint32_t adc) { @@ -736,17 +759,17 @@ uint32_t adc_read_regular(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Read from an Injected Conversion Result Register - -The result read back from the selected injected result register (one of four) -is 12 bits, right or left aligned within the first 16 bits. The result can have -a negative value if the injected channel offset has been set @see -adc_set_injected_offset. - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -@param[in] reg Unsigned int8. Register number (1 ... 4). -@returns Unsigned int32 conversion result. -*/ + * + * The result read back from the selected injected result register (one of four) + * is 12 bits, right or left aligned within the first 16 bits. The result can + * have a negative value if the injected channel offset has been set @see + * adc_set_injected_offset. + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base + * @param[in] reg Unsigned int8. Register number (1 ... 4). + * @returns Unsigned int32 conversion result. + */ uint32_t adc_read_injected(uint32_t adc, uint8_t reg) { @@ -765,14 +788,15 @@ uint32_t adc_read_injected(uint32_t adc, uint8_t reg) /*---------------------------------------------------------------------------*/ /** @brief ADC Set the Injected Channel Data Offset - -This value is subtracted from the injected channel results after conversion is -complete, and can result in negative results. A separate value can be specified -for each injected data register. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@param[in] reg Unsigned int8. Register number (1 ... 4). -@param[in] offset Unsigned int32. + * + * This value is subtracted from the injected channel results after conversion + * is complete, and can result in negative results. A separate value can be + * specified for each injected data register. + * + * @param[in] adc Unsigned int32. ADC block register address base + * @ref adc_reg_base + * @param[in] reg Unsigned int8. Register number (1 ... 4). + * @param[in] offset Unsigned int32. */ void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset) @@ -799,14 +823,14 @@ void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset) /*---------------------------------------------------------------------------*/ /** @brief ADC Power On - -If the ADC is in power-down mode then it is powered up. The application needs -to wait a time of about 3 microseconds for stabilization before using the ADC. -If the ADC is already on this function call will have no effect. - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -*/ + * + * If the ADC is in power-down mode then it is powered up. The application + * needs to wait a time of about 3 microseconds for stabilization before using + * the ADC. If the ADC is already on this function call will have no effect. + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base + */ void adc_power_on(uint32_t adc) { @@ -816,11 +840,11 @@ void adc_power_on(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Set Clock Prescale - -The ADC clock taken from the APB2 clock can be scaled down by 2, 4, 6 or 8. - -@param[in] prescale Unsigned int32. Prescale value for ADC Clock @ref -adc_ccr_adcpre + * + * The ADC clock taken from the APB2 clock can be scaled down by 2, 4, 6 or 8. + * + * @param[in] prescale Unsigned int32. Prescale value for ADC Clock @ref + * adc_ccr_adcpre */ void adc_set_clk_prescale(uint32_t prescale) @@ -831,14 +855,14 @@ void adc_set_clk_prescale(uint32_t prescale) /*---------------------------------------------------------------------------*/ /** @brief ADC Set Dual/Triple Mode - -The multiple mode uses ADC1 as master, ADC2 and optionally ADC3 in a slave -arrangement. This setting is applied to ADC1 only. - -The various modes possible are described in the reference manual. - -@param[in] mode Unsigned int32. Multiple mode selection from @ref -adc_multi_mode + * + * The multiple mode uses ADC1 as master, ADC2 and optionally ADC3 in a slave + * arrangement. This setting is applied to ADC1 only. + * + * The various modes possible are described in the reference manual. + * + * @param[in] mode Unsigned int32. Multiple mode selection from @ref + * adc_multi_mode */ void adc_set_multi_mode(uint32_t mode) @@ -848,17 +872,18 @@ void adc_set_multi_mode(uint32_t mode) /*---------------------------------------------------------------------------*/ /** @brief ADC Enable an External Trigger for Regular Channels - -This enables an external trigger for set of defined regular channels, and sets -the polarity of the trigger event: rising or falling edge or both. Note that if -the trigger polarity is zero, triggering is disabled. - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -@param[in] trigger Unsigned int32. Trigger identifier @ref adc_trigger_regular -@param[in] polarity Unsigned int32. Trigger polarity @ref -adc_trigger_polarity_regular -*/ + * + * This enables an external trigger for set of defined regular channels, and + * sets the polarity of the trigger event: rising or falling edge or both. Note + * that if the trigger polarity is zero, triggering is disabled. + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base + * @param[in] trigger Unsigned int32. Trigger identifier + * @ref adc_trigger_regular + * @param[in] polarity Unsigned int32. Trigger polarity @ref + * adc_trigger_polarity_regular + */ void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, uint32_t polarity) @@ -872,9 +897,10 @@ void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, /*---------------------------------------------------------------------------*/ /** @brief ADC Disable an External Trigger for Regular Channels - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -*/ + * + * @param[in] adc Unsigned int32. ADC block register address base + * @ref adc_reg_base + */ void adc_disable_external_trigger_regular(uint32_t adc) { @@ -883,14 +909,16 @@ void adc_disable_external_trigger_regular(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Enable an External Trigger for Injected Channels - -This enables an external trigger for set of defined injected channels, and sets -the polarity of the trigger event: rising or falling edge or both. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@param[in] trigger Unsigned int8. Trigger identifier @ref adc_trigger_injected -@param[in] polarity Unsigned int32. Trigger polarity @ref -adc_trigger_polarity_injected + * + * This enables an external trigger for set of defined injected channels, and + * sets the polarity of the trigger event: rising or falling edge or both. + * + * @param[in] adc Unsigned int32. ADC block register address base + * @ref adc_reg_base + * @param[in] trigger Unsigned int8. Trigger identifier + * @ref adc_trigger_injected + * @param[in] polarity Unsigned int32. Trigger polarity + * @ref adc_trigger_polarity_injected */ void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, @@ -905,10 +933,10 @@ void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, /*---------------------------------------------------------------------------*/ /** @brief ADC Disable an External Trigger for Injected Channels - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -*/ + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base + */ void adc_disable_external_trigger_injected(uint32_t adc) { @@ -917,14 +945,14 @@ void adc_disable_external_trigger_injected(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Set Resolution - -ADC Resolution can be reduced from 12 bits to 10, 8 or 6 bits for a -corresponding reduction in conversion time (resolution + 3 ADC clock cycles). - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -@param[in] resolution Unsigned int8. Resolution value @ref adc_cr1_res -*/ + * + * ADC Resolution can be reduced from 12 bits to 10, 8 or 6 bits for a + * corresponding reduction in conversion time (resolution + 3 ADC clock cycles). + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base + * @param[in] resolution Unsigned int8. Resolution value @ref adc_cr1_res + */ void adc_set_resolution(uint32_t adc, uint16_t resolution) { @@ -937,14 +965,14 @@ void adc_set_resolution(uint32_t adc, uint16_t resolution) /*---------------------------------------------------------------------------*/ /** @brief ADC Enable the Overrun Interrupt - -The overrun interrupt is generated when data is not read from a result register -before the next conversion is written. If DMA is enabled, all transfers are -terminated and any conversion sequence is aborted. - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -*/ + * + * The overrun interrupt is generated when data is not read from a result + * register before the next conversion is written. If DMA is enabled, all + * transfers are terminated and any conversion sequence is aborted. + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base + */ void adc_enable_overrun_interrupt(uint32_t adc) { @@ -953,10 +981,10 @@ void adc_enable_overrun_interrupt(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Disable the Overrun Interrupt - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -*/ + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base + */ void adc_disable_overrun_interrupt(uint32_t adc) { @@ -965,15 +993,15 @@ void adc_disable_overrun_interrupt(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Read the Overrun Flag - -The overrun flag is set when data is not read from a result register before the -next conversion is written. If DMA is enabled, all transfers are terminated and -any conversion sequence is aborted. - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -@returns Unsigned int32 conversion result. -*/ + * + * The overrun flag is set when data is not read from a result register before + * the next conversion is written. If DMA is enabled, all transfers are + * terminated and any conversion sequence is aborted. + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base + * @returns Unsigned int32 conversion result. + */ bool adc_get_overrun_flag(uint32_t adc) { @@ -982,14 +1010,16 @@ bool adc_get_overrun_flag(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Clear Overrun Flags - -The overrun flag is cleared. Note that if an overrun occurs, DMA is terminated. -The flag must be cleared and the DMA stream and ADC reinitialised to resume -conversions (see the reference manual). - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@returns Unsigned int32 conversion result. -*/ + * + * The overrun flag is cleared. Note that if an overrun occurs, DMA is + * terminated. + * The flag must be cleared and the DMA stream and ADC reinitialised to resume + * conversions (see the reference manual). + * + * @param[in] adc Unsigned int32. ADC block register address base + * @ref adc_reg_base + * @returns Unsigned int32 conversion result. + */ void adc_clear_overrun_flag(uint32_t adc) { @@ -999,12 +1029,13 @@ void adc_clear_overrun_flag(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Enable an EOC for Each Conversion - -The EOC is set after each conversion in a sequence rather than at the end of the -sequence. Overrun detection is enabled only if DMA is enabled. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -*/ + * + * The EOC is set after each conversion in a sequence rather than at the end of + * the sequence. Overrun detection is enabled only if DMA is enabled. + * + * @param[in] adc Unsigned int32. ADC block register address base + * @ref adc_reg_base + */ void adc_eoc_after_each(uint32_t adc) { @@ -1013,13 +1044,13 @@ void adc_eoc_after_each(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Disable the EOC for Each Conversion - -The EOC is set at the end of each sequence rather than after each conversion in -the sequence. Overrun detection is enabled always. - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -*/ + * + * The EOC is set at the end of each sequence rather than after each conversion + * in the sequence. Overrun detection is enabled always. + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base + */ void adc_eoc_after_group(uint32_t adc) { @@ -1028,13 +1059,14 @@ void adc_eoc_after_group(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Set DMA to Continue - -This must be set to allow DMA to continue to operate after the last conversion -in the DMA sequence. This allows DMA to be used in continuous circular mode. - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -*/ + * + * This must be set to allow DMA to continue to operate after the last + * conversion in the DMA sequence. This allows DMA to be used in continuous + * circular mode. + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base + */ /* void adc_set_dma_continue(uint32_t adc) @@ -1045,12 +1077,13 @@ void adc_set_dma_continue(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Set DMA to Terminate - -This must be set to allow DMA to terminate after the last conversion in the DMA -sequence. This can avoid overrun errors. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -*/ + * + * This must be set to allow DMA to terminate after the last conversion in the + * DMA sequence. This can avoid overrun errors. + * + * @param[in] adc Unsigned int32. ADC block register address base + * @ref adc_reg_base + */ /* void adc_set_dma_terminate(uint32_t adc) @@ -1061,12 +1094,14 @@ void adc_set_dma_terminate(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Read the Analog Watchdog Flag - -This flag is set when the converted voltage crosses the high or low thresholds. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@returns bool. AWD flag. -*/ + * + * This flag is set when the converted voltage crosses the high or low + * thresholds. + * + * @param[in] adc Unsigned int32. ADC block register address base + * @ref adc_reg_base + * @returns bool. AWD flag. + */ bool adc_awd(uint32_t adc) { @@ -1077,13 +1112,14 @@ bool adc_awd(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Enable The Temperature Sensor - -This enables both the sensor and the reference voltage measurements on channels -16 and 17. These are only available on ADC1 channel 16 and 17 respectively. - -@param[in] adc Unsigned int32. ADC block register address base @ref -adc_reg_base -*/ + * + * This enables both the sensor and the reference voltage measurements on + * channels + * 16 and 17. These are only available on ADC1 channel 16 and 17 respectively. + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base + */ void adc_enable_temperature_sensor() { @@ -1092,12 +1128,13 @@ void adc_enable_temperature_sensor() /*---------------------------------------------------------------------------*/ /** @brief ADC Disable The Temperature Sensor - -Disabling this will reduce power consumption from the sensor and the reference -voltage measurements. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -*/ + * + * Disabling this will reduce power consumption from the sensor and the + * reference voltage measurements. + * + * @param[in] adc Unsigned int32. ADC block register address base @ref + * adc_reg_base + */ void adc_disable_temperature_sensor() { diff --git a/lib/stm32/f3/crc.c b/lib/stm32/f3/crc.c index d9c8dad6..2c7c6dd4 100644 --- a/lib/stm32/f3/crc.c +++ b/lib/stm32/f3/crc.c @@ -1,15 +1,15 @@ /** @defgroup crc_file CRC - -@ingroup STM32F3xx - -@brief libopencm3 STM32F3xx CRC - -@version 1.0.0 - -@date 15 October 2012 - -LGPL License Terms @ref lgpl_license -*/ + * + * @ingroup STM32F3xx + * + * @brief libopencm3 STM32F3xx CRC + * + * @version 1.0.0 + * + * @date 15 October 2012 + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. diff --git a/lib/stm32/f3/dac.c b/lib/stm32/f3/dac.c index 4f681174..5dc95ac3 100644 --- a/lib/stm32/f3/dac.c +++ b/lib/stm32/f3/dac.c @@ -1,15 +1,15 @@ /** @defgroup dac_file DAC - -@ingroup STM32F3xx - -@brief libopencm3 STM32F3xx DAC - -@version 1.0.0 - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license -*/ + * + * @ingroup STM32F3xx + * + * @brief libopencm3 STM32F3xx DAC + * + * @version 1.0.0 + * + * @date 18 August 2012 + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. diff --git a/lib/stm32/f3/i2c.c b/lib/stm32/f3/i2c.c index e0fc54ad..b5d39cfc 100644 --- a/lib/stm32/f3/i2c.c +++ b/lib/stm32/f3/i2c.c @@ -1,15 +1,15 @@ /** @defgroup i2c_file I2C - -@ingroup STM32F3xx - -@brief libopencm3 STM32F3xx I2C - -@version 1.0.0 - -@date 15 October 2012 - -LGPL License Terms @ref lgpl_license -*/ + * + * @ingroup STM32F3xx + * + * @brief libopencm3 STM32F3xx I2C + * + * @version 1.0.0 + * + * @date 15 October 2012 + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. @@ -35,12 +35,13 @@ LGPL License Terms @ref lgpl_license /*---------------------------------------------------------------------------*/ /** @brief I2C Reset. - -The I2C peripheral and all its associated configuration registers are placed in -the reset condition. The reset is effected via the RCC peripheral reset system. - -@param[in] i2c Unsigned int32. I2C peripheral identifier @ref i2c_reg_base. -*/ + * + * The I2C peripheral and all its associated configuration registers are placed + * in the reset condition. The reset is effected via the RCC peripheral reset + * system. + * + * @param[in] i2c Unsigned int32. I2C peripheral identifier @ref i2c_reg_base. + */ void i2c_reset(uint32_t i2c) { @@ -58,9 +59,9 @@ void i2c_reset(uint32_t i2c) /*---------------------------------------------------------------------------*/ /** @brief I2C Peripheral Enable. - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ + * + * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. + */ void i2c_peripheral_enable(uint32_t i2c) { @@ -69,12 +70,13 @@ void i2c_peripheral_enable(uint32_t i2c) /*---------------------------------------------------------------------------*/ /** @brief I2C Peripheral Disable. - -This must not be reset while in Master mode until a communication has finished. -In Slave mode, the peripheral is disabled only after communication has ended. - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ + * + * This must not be reset while in Master mode until a communication has + * finished. In Slave mode, the peripheral is disabled only after communication + * has ended. + * + * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. + */ void i2c_peripheral_disable(uint32_t i2c) { @@ -83,13 +85,13 @@ void i2c_peripheral_disable(uint32_t i2c) /*---------------------------------------------------------------------------*/ /** @brief I2C Send Start Condition. - -If in Master mode this will cause a restart condition to occur at the end of the -current transmission. If in Slave mode, this will initiate a start condition -when the current bus activity is completed. - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ + * + * If in Master mode this will cause a restart condition to occur at the end of + * the current transmission. If in Slave mode, this will initiate a start + * condition when the current bus activity is completed. + * + * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. + */ void i2c_send_start(uint32_t i2c) { @@ -98,12 +100,12 @@ void i2c_send_start(uint32_t i2c) /*---------------------------------------------------------------------------*/ /** @brief I2C Send Stop Condition. - -After the current byte transfer this will initiate a stop condition if in Master -mode, or simply release the bus if in Slave mode. - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ + * + * After the current byte transfer this will initiate a stop condition if in + * Master mode, or simply release the bus if in Slave mode. + * + * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. + */ void i2c_send_stop(uint32_t i2c) { @@ -112,11 +114,11 @@ void i2c_send_stop(uint32_t i2c) /*---------------------------------------------------------------------------*/ /** @brief I2C Clear Stop Flag. - -Clear the "Send Stop" flag in the I2C config register - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ + * + * Clear the "Send Stop" flag in the I2C config register + * + * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. + */ void i2c_clear_stop(uint32_t i2c) { I2C_ICR(i2c) |= I2C_ICR_STOPCF; @@ -124,12 +126,12 @@ void i2c_clear_stop(uint32_t i2c) /*---------------------------------------------------------------------------*/ /** @brief I2C Set the 7 bit Slave Address for the Peripheral. - -This sets an address for Slave mode operation, in 7 bit form. - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -@param[in] slave Unsigned int8. Slave address 0...127. -*/ + * + * This sets an address for Slave mode operation, in 7 bit form. + * + * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. + * @param[in] slave Unsigned int8. Slave address 0...127. + */ void i2c_set_own_7bit_slave_address(uint32_t i2c, uint8_t slave) { @@ -140,14 +142,14 @@ void i2c_set_own_7bit_slave_address(uint32_t i2c, uint8_t slave) /*---------------------------------------------------------------------------*/ /** @brief I2C Set the 10 bit Slave Address for the Peripheral. - -This sets an address for Slave mode operation, in 10 bit form. - -@todo add "I2C_OAR1(i2c) |= (1 << 14);" as above - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -@param[in] slave Unsigned int16. Slave address 0...1023. -*/ + * + * This sets an address for Slave mode operation, in 10 bit form. + * + * @todo add "I2C_OAR1(i2c) |= (1 << 14);" as above + * + * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. + * @param[in] slave Unsigned int16. Slave address 0...1023. + */ void i2c_set_own_10bit_slave_address(uint32_t i2c, uint16_t slave) { @@ -156,10 +158,10 @@ void i2c_set_own_10bit_slave_address(uint32_t i2c, uint16_t slave) /*---------------------------------------------------------------------------*/ /** @brief I2C Send Data. - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -@param[in] data Unsigned int8. Byte to send. -*/ + * + * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. + * @param[in] data Unsigned int8. Byte to send. + */ void i2c_send_data(uint32_t i2c, uint8_t data) { @@ -168,9 +170,9 @@ void i2c_send_data(uint32_t i2c, uint8_t data) /*---------------------------------------------------------------------------*/ /** @brief I2C Get Data. - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ + * + * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. + */ uint8_t i2c_get_data(uint32_t i2c) { return I2C_RXDR(i2c) & 0xff; @@ -346,10 +348,10 @@ uint8_t i2c_received_data(uint32_t i2c) /*---------------------------------------------------------------------------*/ /** @brief I2C Enable Interrupt - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -@param[in] interrupt Unsigned int32. Interrupt to enable. -*/ + * + * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. + * @param[in] interrupt Unsigned int32. Interrupt to enable. + */ void i2c_enable_interrupt(uint32_t i2c, uint32_t interrupt) { I2C_CR1(i2c) |= interrupt; @@ -357,10 +359,10 @@ void i2c_enable_interrupt(uint32_t i2c, uint32_t interrupt) /*---------------------------------------------------------------------------*/ /** @brief I2C Disable Interrupt - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -@param[in] interrupt Unsigned int32. Interrupt to disable. -*/ + * + * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. + * @param[in] interrupt Unsigned int32. Interrupt to disable. + */ void i2c_disable_interrupt(uint32_t i2c, uint32_t interrupt) { I2C_CR1(i2c) &= ~interrupt; @@ -368,9 +370,9 @@ void i2c_disable_interrupt(uint32_t i2c, uint32_t interrupt) /*---------------------------------------------------------------------------*/ /** @brief I2C Enable reception DMA - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ + * + * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. + */ void i2c_enable_rxdma(uint32_t i2c) { I2C_CR1(i2c) |= I2C_CR1_RXDMAEN; @@ -378,9 +380,9 @@ void i2c_enable_rxdma(uint32_t i2c) /*---------------------------------------------------------------------------*/ /** @brief I2C Disable reception DMA - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ + * + * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. + */ void i2c_disable_rxdma(uint32_t i2c) { I2C_CR1(i2c) &= ~I2C_CR1_RXDMAEN; @@ -388,9 +390,9 @@ void i2c_disable_rxdma(uint32_t i2c) /*---------------------------------------------------------------------------*/ /** @brief I2C Enable transmission DMA - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ + * + * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. + */ void i2c_enable_txdma(uint32_t i2c) { I2C_CR1(i2c) |= I2C_CR1_TXDMAEN; @@ -398,9 +400,9 @@ void i2c_enable_txdma(uint32_t i2c) /*---------------------------------------------------------------------------*/ /** @brief I2C Disable transmission DMA - -@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. -*/ + * + * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. + */ void i2c_disable_txdma(uint32_t i2c) { I2C_CR1(i2c) &= ~I2C_CR1_TXDMAEN; diff --git a/lib/stm32/f3/iwdg.c b/lib/stm32/f3/iwdg.c index 1cead19f..d69f0362 100644 --- a/lib/stm32/f3/iwdg.c +++ b/lib/stm32/f3/iwdg.c @@ -1,15 +1,15 @@ /** @defgroup iwdg_file IWDG - -@ingroup STM32F3xx - -@brief libopencm3 STM32F3xx Independent Watchdog Timer - -@version 1.0.0 - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license -*/ + * + * @ingroup STM32F3xx + * + * @brief libopencm3 STM32F3xx Independent Watchdog Timer + * + * @version 1.0.0 + * + * @date 18 August 2012 + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. diff --git a/lib/stm32/f3/usart.c b/lib/stm32/f3/usart.c index be474542..d44eb9f4 100644 --- a/lib/stm32/f3/usart.c +++ b/lib/stm32/f3/usart.c @@ -1,15 +1,15 @@ /** @defgroup usart_file USART - -@ingroup STM32F3xx - -@brief libopencm3 STM32F3xx USART - -@version 1.0.0 - -@date 30 August 2012 - -LGPL License Terms @ref lgpl_license -*/ + * + * @ingroup STM32F3xx + * + * @brief libopencm3 STM32F3xx USART + * + * @version 1.0.0 + * + * @date 30 August 2012 + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. @@ -33,11 +33,11 @@ LGPL License Terms @ref lgpl_license /*---------------------------------------------------------------------------*/ /** @brief USART Send a Data Word. - -@param[in] usart unsigned 32 bit. USART block register address base @ref -usart_reg_base -@param[in] data unsigned 16 bit. -*/ + * + * @param[in] usart unsigned 32 bit. USART block register address base @ref + * usart_reg_base + * @param[in] data unsigned 16 bit. + */ void usart_send(uint32_t usart, uint16_t data) { @@ -47,14 +47,14 @@ void usart_send(uint32_t usart, uint16_t data) /*---------------------------------------------------------------------------*/ /** @brief USART Read a Received Data Word. - -If parity is enabled the MSB (bit 7 or 8 depending on the word length) is the -parity bit. - -@param[in] usart unsigned 32 bit. USART block register address base @ref -usart_reg_base -@returns unsigned 16 bit data word. -*/ + * + * If parity is enabled the MSB (bit 7 or 8 depending on the word length) is + * the parity bit. + * + * @param[in] usart unsigned 32 bit. USART block register address base @ref + * usart_reg_base + * @returns unsigned 16 bit data word. + */ uint16_t usart_recv(uint32_t usart) { @@ -64,13 +64,13 @@ uint16_t usart_recv(uint32_t usart) /*---------------------------------------------------------------------------*/ /** @brief USART Wait for Transmit Data Buffer Empty - -Blocks until the transmit data buffer becomes empty and is ready to accept the -next data word. - -@param[in] usart unsigned 32 bit. USART block register address base @ref -usart_reg_base -*/ + * + * Blocks until the transmit data buffer becomes empty and is ready to accept + * the next data word. + * + * @param[in] usart unsigned 32 bit. USART block register address base @ref + * usart_reg_base + */ void usart_wait_send_ready(uint32_t usart) { @@ -80,12 +80,12 @@ void usart_wait_send_ready(uint32_t usart) /*---------------------------------------------------------------------------*/ /** @brief USART Wait for Received Data Available - -Blocks until the receive data buffer holds a valid received data word. - -@param[in] usart unsigned 32 bit. USART block register address base @ref -usart_reg_base -*/ + * + * Blocks until the receive data buffer holds a valid received data word. + * + * @param[in] usart unsigned 32 bit. USART block register address base @ref + * usart_reg_base + */ void usart_wait_recv_ready(uint32_t usart) { @@ -95,12 +95,12 @@ void usart_wait_recv_ready(uint32_t usart) /*---------------------------------------------------------------------------*/ /** @brief USART Read a Status Flag. - -@param[in] usart unsigned 32 bit. USART block register address base @ref -usart_reg_base -@param[in] flag Unsigned int32. Status register flag @ref usart_sr_flags. -@returns boolean: flag set. -*/ + * + * @param[in] usart unsigned 32 bit. USART block register address base @ref + * usart_reg_base + * @param[in] flag Unsigned int32. Status register flag @ref usart_sr_flags. + * @returns boolean: flag set. + */ bool usart_get_flag(uint32_t usart, uint32_t flag) { @@ -109,20 +109,20 @@ bool usart_get_flag(uint32_t usart, uint32_t flag) /*---------------------------------------------------------------------------*/ /** @brief USART Return Interrupt Source. - -Returns true if the specified interrupt flag (IDLE, RXNE, TC, TXE or OE) was -set and the interrupt was enabled. If the specified flag is not an interrupt -flag, the function returns false. - -@todo These are the most important interrupts likely to be used. Others -relating to LIN break, and error conditions in multibuffer communication, need -to be added for completeness. - -@param[in] usart unsigned 32 bit. USART block register address base @ref -usart_reg_base -@param[in] flag Unsigned int32. Status register flag @ref usart_sr_flags. -@returns boolean: flag and interrupt enable both set. -*/ + * + * Returns true if the specified interrupt flag (IDLE, RXNE, TC, TXE or OE) was + * set and the interrupt was enabled. If the specified flag is not an interrupt + * flag, the function returns false. + * + * @todo These are the most important interrupts likely to be used. Others + * relating to LIN break, and error conditions in multibuffer communication, + * need to be added for completeness. + * + * @param[in] usart unsigned 32 bit. USART block register address base @ref + * usart_reg_base + * @param[in] flag Unsigned int32. Status register flag @ref usart_sr_flags. + * @returns boolean: flag and interrupt enable both set. + */ bool usart_get_interrupt_source(uint32_t usart, uint32_t flag) {