[Style] checked and corrected
This commit is contained in:
BuFran
committed by
Piotr Esden-Tempski
Piotr Esden-Tempski
parent
c6f861139d
commit
65eaad938f
@@ -36,70 +36,71 @@
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#define UART_SRC_IDIVE 0x10
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#define UART_CGU_AUTOBLOCK_CLOCK_BIT 11
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#define UART_CGU_BASE_CLK_SEL_SHIFT 24 /* clock source selection (5 bits) */
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/* clock source selection (5 bits) */
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#define UART_CGU_BASE_CLK_SEL_SHIFT 24
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uint32_t dummy_read;
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/*
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* UART Init function
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*/
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void uart_init(uart_num_t uart_num,
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uart_databit_t data_nb_bits,
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uart_stopbit_t data_nb_stop,
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uart_parity_t data_parity,
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uint16_t uart_divisor,
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uint8_t uart_divaddval,
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uint8_t uart_mulval)
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void uart_init(uart_num_t uart_num, uart_databit_t data_nb_bits,
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uart_stopbit_t data_nb_stop, uart_parity_t data_parity,
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uint16_t uart_divisor, uint8_t uart_divaddval, uint8_t uart_mulval)
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{
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uint32_t lcr_config;
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uint32_t uart_port;
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uart_port = uart_num;
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switch(uart_num)
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{
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case UART0_NUM:
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/* use PLL1 as clock source for UART0 */
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CGU_BASE_UART0_CLK = (CGU_SRC_PLL1<<UART_CGU_BASE_CLK_SEL_SHIFT) | (1<<UART_CGU_AUTOBLOCK_CLOCK_BIT);
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break;
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switch (uart_num) {
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case UART0_NUM:
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/* use PLL1 as clock source for UART0 */
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CGU_BASE_UART0_CLK = (1<<UART_CGU_AUTOBLOCK_CLOCK_BIT) |
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(CGU_SRC_PLL1<<UART_CGU_BASE_CLK_SEL_SHIFT);
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break;
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case UART1_NUM:
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/* use PLL1 as clock source for UART1 */
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CGU_BASE_UART1_CLK = (CGU_SRC_PLL1<<UART_CGU_BASE_CLK_SEL_SHIFT) | (1<<UART_CGU_AUTOBLOCK_CLOCK_BIT);
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break;
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case UART1_NUM:
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/* use PLL1 as clock source for UART1 */
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CGU_BASE_UART1_CLK = (1<<UART_CGU_AUTOBLOCK_CLOCK_BIT) |
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(CGU_SRC_PLL1<<UART_CGU_BASE_CLK_SEL_SHIFT);
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break;
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case UART2_NUM:
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/* use PLL1 as clock source for UART2 */
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CGU_BASE_UART2_CLK = (CGU_SRC_PLL1<<UART_CGU_BASE_CLK_SEL_SHIFT) | (1<<UART_CGU_AUTOBLOCK_CLOCK_BIT);
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break;
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case UART2_NUM:
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/* use PLL1 as clock source for UART2 */
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CGU_BASE_UART2_CLK = (1<<UART_CGU_AUTOBLOCK_CLOCK_BIT) |
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(CGU_SRC_PLL1<<UART_CGU_BASE_CLK_SEL_SHIFT);
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break;
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case UART3_NUM:
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/* use PLL1 as clock source for UART3 */
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CGU_BASE_UART3_CLK = (CGU_SRC_PLL1<<UART_CGU_BASE_CLK_SEL_SHIFT) | (1<<UART_CGU_AUTOBLOCK_CLOCK_BIT);
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break;
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case UART3_NUM:
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/* use PLL1 as clock source for UART3 */
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CGU_BASE_UART3_CLK = (1<<UART_CGU_AUTOBLOCK_CLOCK_BIT) |
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(CGU_SRC_PLL1<<UART_CGU_BASE_CLK_SEL_SHIFT);
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break;
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default:
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return; /* error */
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default:
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return; /* error */
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}
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/* FIFOs RX/TX Enabled and Reset RX/TX FIFO (DMA Mode is also cleared) */
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UART_FCR(uart_port) = ( UART_FCR_FIFO_EN | UART_FCR_RX_RS | UART_FCR_TX_RS);
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/* FIFOs RX/TX Enabled and Reset RX/TX FIFO (DMA Mode is also cleared)*/
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UART_FCR(uart_port) = (UART_FCR_FIFO_EN | UART_FCR_RX_RS |
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UART_FCR_TX_RS);
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/* Disable FIFO */
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UART_FCR(uart_port) = 0;
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// Dummy read (to clear existing data)
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while (UART_LSR(uart_port) & UART_LSR_RDR ) {
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/* Dummy read (to clear existing data) */
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while (UART_LSR(uart_port) & UART_LSR_RDR) {
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dummy_read = UART_RBR(uart_port);
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}
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/* Wait end of TX & disable TX */
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UART_TER(uart_port) = UART_TER_TXEN;
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UART_TER(uart_port) = UART_TER_TXEN;
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/* Wait for current transmit complete */
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while (!(UART_LSR(uart_port) & UART_LSR_THRE));
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/* Wait for current transmit complete */
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while (!(UART_LSR(uart_port) & UART_LSR_THRE));
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/* Disable Tx */
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UART_TER(uart_port) = 0;
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/* Disable Tx */
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UART_TER(uart_port) = 0;
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/* Disable interrupt */
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UART_IER(uart_port) = 0;
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@@ -114,12 +115,13 @@ void uart_init(uart_num_t uart_num,
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dummy_read = UART_LSR(uart_port);
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/*
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Table 835. USART Fractional Divider Register:
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UARTbaudrate = PCLK / ( 16* (((256*DLM)+ DLL)*(1+(DivAddVal/MulVal))) )
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The value of MULVAL and DIVADDVAL should comply to the following conditions:
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1. 1 <= MULVAL <= 15
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2. 0 <= DIVADDVAL <= 14
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3. DIVADDVAL < MULVAL
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Table 835. USART Fractional Divider Register:
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UARTbaudrate = PCLK / ( 16* (((256*DLM)+ DLL)*(1+(DivAddVal/MulVal))) )
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The value of MULVAL and DIVADDVAL should comply to the following
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conditions:
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1. 1 <= MULVAL <= 15
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2. 0 <= DIVADDVAL <= 14
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3. DIVADDVAL < MULVAL
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*/
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/* Set DLAB Bit */
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@@ -128,10 +130,12 @@ void uart_init(uart_num_t uart_num,
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UART_DLL(uart_port) = UART_LOAD_DLL(uart_divisor);
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/* Clear DLAB Bit */
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UART_LCR(uart_port) &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK;
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UART_FDR(uart_port) = (UART_FDR_MULVAL(uart_mulval) | UART_FDR_DIVADDVAL(uart_divaddval)) & UART_FDR_BITMASK;
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UART_FDR(uart_port) = UART_FDR_BITMASK &
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(UART_FDR_MULVAL(uart_mulval) | UART_FDR_DIVADDVAL(uart_divaddval));
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/* Read LCR config & Force Enable of Divisor Latches Access */
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lcr_config = (UART_LCR(uart_port) & UART_LCR_DLAB_EN) & UART_LCR_BITMASK;
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lcr_config = (UART_LCR(uart_port) & UART_LCR_DLAB_EN) &
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UART_LCR_BITMASK;
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lcr_config |= data_nb_bits; /* Set Nb Data Bits */
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lcr_config |= data_nb_stop; /* Set Nb Stop Bits */
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lcr_config |= data_parity; /* Set Data Parity */
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@@ -140,7 +144,7 @@ void uart_init(uart_num_t uart_num,
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UART_LCR(uart_port) = (lcr_config & UART_LCR_BITMASK);
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/* Enable TX */
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UART_TER(uart_port) = UART_TER_TXEN;
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UART_TER(uart_port) = UART_TER_TXEN;
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}
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/*
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@@ -193,7 +197,8 @@ uint8_t uart_read(uart_num_t uart_num)
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/*
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* This Function Wait until Data RX Ready, and return Data Read from UART.
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*/
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uint8_t uart_read_timeout(uart_num_t uart_num, uint32_t rx_timeout_nb_cycles, uart_error_t* error)
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uint8_t uart_read_timeout(uart_num_t uart_num, uint32_t rx_timeout_nb_cycles,
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uart_error_t *error)
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{
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uint32_t uart_port;
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uint8_t uart_val;
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@@ -203,11 +208,10 @@ uint8_t uart_read_timeout(uart_num_t uart_num, uint32_t rx_timeout_nb_cycles, ua
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/* Wait Until Data Received (Rx Data Not Ready) */
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counter = 0;
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while ((UART_LSR(uart_port) & UART_LSR_RDR) == 0)
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{
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if (rx_timeout_nb_cycles>0) {
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while ((UART_LSR(uart_port) & UART_LSR_RDR) == 0) {
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if (rx_timeout_nb_cycles > 0) {
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counter++;
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if (counter>=rx_timeout_nb_cycles) {
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if (counter >= rx_timeout_nb_cycles) {
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*error = UART_TIMEOUT_ERROR;
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return 0;
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}
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@@ -222,7 +226,7 @@ uint8_t uart_read_timeout(uart_num_t uart_num, uint32_t rx_timeout_nb_cycles, ua
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return uart_val;
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}
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/* This Function Wait Data TX Ready, and Write Data to UART
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/* This Function Wait Data TX Ready, and Write Data to UART
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if rx_timeout_nb_cycles = 0 Infinite wait
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*/
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void uart_write(uart_num_t uart_num, uint8_t data)
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