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stm32/usb: otg_fs and otg_hs register definitions

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* USB host register definitions added.
* Extracted common register and bitfield definitions
	from 'otg_fs.h' and 'otg_hs.h'
	into new file 'otg_common.h'.
	Modified usb low-level drivers to adopt to new style of bitfields.
* Fixed typo OTG_GOTGIN -> OTG_GOTGINT (according to the datasheet)

Signed-off-by: Amir Hammad <amir.hammad@hotmail.com>
This commit is contained in:
Amir Hammad
2015-02-03 23:49:38 +01:00
committed by Karl Palsson
parent f4d6da9554
commit 6357630a90
6 changed files with 692 additions and 693 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
lib/usb/usb_f107.c
View File

@@ -52,23 +52,23 @@ const struct _usbd_driver stm32f107_usb_driver = {
/** Initialize the USB device controller hardware of the STM32. */
static usbd_device *stm32f107_usbd_init(void)
{
OTG_FS_GINTSTS = OTG_FS_GINTSTS_MMIS;
OTG_FS_GINTSTS = OTG_GINTSTS_MMIS;
OTG_FS_GUSBCFG |= OTG_FS_GUSBCFG_PHYSEL;
OTG_FS_GUSBCFG |= OTG_GUSBCFG_PHYSEL;
/* Enable VBUS sensing in device mode and power down the PHY. */
OTG_FS_GCCFG |= OTG_FS_GCCFG_VBUSBSEN | OTG_FS_GCCFG_PWRDWN;
OTG_FS_GCCFG |= OTG_GCCFG_VBUSBSEN | OTG_GCCFG_PWRDWN;
/* Wait for AHB idle. */
while (!(OTG_FS_GRSTCTL & OTG_FS_GRSTCTL_AHBIDL));
while (!(OTG_FS_GRSTCTL & OTG_GRSTCTL_AHBIDL));
/* Do core soft reset. */
OTG_FS_GRSTCTL |= OTG_FS_GRSTCTL_CSRST;
while (OTG_FS_GRSTCTL & OTG_FS_GRSTCTL_CSRST);
OTG_FS_GRSTCTL |= OTG_GRSTCTL_CSRST;
while (OTG_FS_GRSTCTL & OTG_GRSTCTL_CSRST);
/* Force peripheral only mode. */
OTG_FS_GUSBCFG |= OTG_FS_GUSBCFG_FDMOD | OTG_FS_GUSBCFG_TRDT_MASK;
OTG_FS_GUSBCFG |= OTG_GUSBCFG_FDMOD | OTG_GUSBCFG_TRDT_MASK;
/* Full speed device. */
OTG_FS_DCFG |= OTG_FS_DCFG_DSPD;
OTG_FS_DCFG |= OTG_DCFG_DSPD;
/* Restart the PHY clock. */
OTG_FS_PCGCCTL = 0;
@@ -77,14 +77,14 @@ static usbd_device *stm32f107_usbd_init(void)
usbd_dev.fifo_mem_top = stm32f107_usb_driver.rx_fifo_size;
/* Unmask interrupts for TX and RX. */
OTG_FS_GAHBCFG |= OTG_FS_GAHBCFG_GINT;
OTG_FS_GINTMSK = OTG_FS_GINTMSK_ENUMDNEM |
OTG_FS_GINTMSK_RXFLVLM |
OTG_FS_GINTMSK_IEPINT |
OTG_FS_GINTMSK_USBSUSPM |
OTG_FS_GINTMSK_WUIM;
OTG_FS_GAHBCFG |= OTG_GAHBCFG_GINT;
OTG_FS_GINTMSK = OTG_GINTMSK_ENUMDNEM |
OTG_GINTMSK_RXFLVLM |
OTG_GINTMSK_IEPINT |
OTG_GINTMSK_USBSUSPM |
OTG_GINTMSK_WUIM;
OTG_FS_DAINTMSK = 0xF;
OTG_FS_DIEPMSK = OTG_FS_DIEPMSK_XFRCM;
OTG_FS_DIEPMSK = OTG_DIEPMSK_XFRCM;
return &usbd_dev;
}

30
lib/usb/usb_f207.c
View File

@@ -52,23 +52,23 @@ const struct _usbd_driver stm32f207_usb_driver = {
/** Initialize the USB device controller hardware of the STM32. */
static usbd_device *stm32f207_usbd_init(void)
{
OTG_HS_GINTSTS = OTG_HS_GINTSTS_MMIS;
OTG_HS_GINTSTS = OTG_GINTSTS_MMIS;
OTG_HS_GUSBCFG |= OTG_HS_GUSBCFG_PHYSEL;
OTG_HS_GUSBCFG |= OTG_GUSBCFG_PHYSEL;
/* Enable VBUS sensing in device mode and power down the PHY. */
OTG_HS_GCCFG |= OTG_HS_GCCFG_VBUSBSEN | OTG_HS_GCCFG_PWRDWN;
OTG_HS_GCCFG |= OTG_GCCFG_VBUSBSEN | OTG_GCCFG_PWRDWN;
/* Wait for AHB idle. */
while (!(OTG_HS_GRSTCTL & OTG_HS_GRSTCTL_AHBIDL));
while (!(OTG_HS_GRSTCTL & OTG_GRSTCTL_AHBIDL));
/* Do core soft reset. */
OTG_HS_GRSTCTL |= OTG_HS_GRSTCTL_CSRST;
while (OTG_HS_GRSTCTL & OTG_HS_GRSTCTL_CSRST);
OTG_HS_GRSTCTL |= OTG_GRSTCTL_CSRST;
while (OTG_HS_GRSTCTL & OTG_GRSTCTL_CSRST);
/* Force peripheral only mode. */
OTG_HS_GUSBCFG |= OTG_HS_GUSBCFG_FDMOD | OTG_HS_GUSBCFG_TRDT_MASK;
OTG_HS_GUSBCFG |= OTG_GUSBCFG_FDMOD | OTG_GUSBCFG_TRDT_MASK;
/* Full speed device. */
OTG_HS_DCFG |= OTG_HS_DCFG_DSPD;
OTG_HS_DCFG |= OTG_DCFG_DSPD;
/* Restart the PHY clock. */
OTG_HS_PCGCCTL = 0;
@@ -77,14 +77,14 @@ static usbd_device *stm32f207_usbd_init(void)
usbd_dev.fifo_mem_top = stm32f207_usb_driver.rx_fifo_size;
/* Unmask interrupts for TX and RX. */
OTG_HS_GAHBCFG |= OTG_HS_GAHBCFG_GINT;
OTG_HS_GINTMSK = OTG_HS_GINTMSK_ENUMDNEM |
OTG_HS_GINTMSK_RXFLVLM |
OTG_HS_GINTMSK_IEPINT |
OTG_HS_GINTMSK_USBSUSPM |
OTG_HS_GINTMSK_WUIM;
OTG_HS_GAHBCFG |= OTG_GAHBCFG_GINT;
OTG_HS_GINTMSK = OTG_GINTMSK_ENUMDNEM |
OTG_GINTMSK_RXFLVLM |
OTG_GINTMSK_IEPINT |
OTG_GINTMSK_USBSUSPM |
OTG_GINTMSK_WUIM;
OTG_HS_DAINTMSK = 0xF;
OTG_HS_DIEPMSK = OTG_HS_DIEPMSK_XFRCM;
OTG_HS_DIEPMSK = OTG_DIEPMSK_XFRCM;
return &usbd_dev;
}

118
lib/usb/usb_fx07_common.c
View File

@@ -35,7 +35,7 @@
void stm32fx07_set_address(usbd_device *usbd_dev, uint8_t addr)
{
REBASE(OTG_DCFG) = (REBASE(OTG_DCFG) & ~OTG_FS_DCFG_DAD) | (addr << 4);
REBASE(OTG_DCFG) = (REBASE(OTG_DCFG) & ~OTG_DCFG_DAD) | (addr << 4);
}
void stm32fx07_ep_setup(usbd_device *usbd_dev, uint8_t addr, uint8_t type,
@@ -52,27 +52,27 @@ void stm32fx07_ep_setup(usbd_device *usbd_dev, uint8_t addr, uint8_t type,
if (addr == 0) { /* For the default control endpoint */
/* Configure IN part. */
if (max_size >= 64) {
REBASE(OTG_DIEPCTL0) = OTG_FS_DIEPCTL0_MPSIZ_64;
REBASE(OTG_DIEPCTL0) = OTG_DIEPCTL0_MPSIZ_64;
} else if (max_size >= 32) {
REBASE(OTG_DIEPCTL0) = OTG_FS_DIEPCTL0_MPSIZ_32;
REBASE(OTG_DIEPCTL0) = OTG_DIEPCTL0_MPSIZ_32;
} else if (max_size >= 16) {
REBASE(OTG_DIEPCTL0) = OTG_FS_DIEPCTL0_MPSIZ_16;
REBASE(OTG_DIEPCTL0) = OTG_DIEPCTL0_MPSIZ_16;
} else {
REBASE(OTG_DIEPCTL0) = OTG_FS_DIEPCTL0_MPSIZ_8;
REBASE(OTG_DIEPCTL0) = OTG_DIEPCTL0_MPSIZ_8;
}
REBASE(OTG_DIEPTSIZ0) =
(max_size & OTG_FS_DIEPSIZ0_XFRSIZ_MASK);
(max_size & OTG_DIEPSIZ0_XFRSIZ_MASK);
REBASE(OTG_DIEPCTL0) |=
OTG_FS_DIEPCTL0_EPENA | OTG_FS_DIEPCTL0_SNAK;
OTG_DIEPCTL0_EPENA | OTG_DIEPCTL0_SNAK;
/* Configure OUT part. */
usbd_dev->doeptsiz[0] = OTG_FS_DIEPSIZ0_STUPCNT_1 |
OTG_FS_DIEPSIZ0_PKTCNT |
(max_size & OTG_FS_DIEPSIZ0_XFRSIZ_MASK);
usbd_dev->doeptsiz[0] = OTG_DIEPSIZ0_STUPCNT_1 |
OTG_DIEPSIZ0_PKTCNT |
(max_size & OTG_DIEPSIZ0_XFRSIZ_MASK);
REBASE(OTG_DOEPTSIZ(0)) = usbd_dev->doeptsiz[0];
REBASE(OTG_DOEPCTL(0)) |=
OTG_FS_DOEPCTL0_EPENA | OTG_FS_DIEPCTL0_SNAK;
OTG_DOEPCTL0_EPENA | OTG_DIEPCTL0_SNAK;
REBASE(OTG_GNPTXFSIZ) = ((max_size / 4) << 16) |
usbd_dev->driver->rx_fifo_size;
@@ -88,10 +88,10 @@ void stm32fx07_ep_setup(usbd_device *usbd_dev, uint8_t addr, uint8_t type,
usbd_dev->fifo_mem_top += max_size / 4;
REBASE(OTG_DIEPTSIZ(addr)) =
(max_size & OTG_FS_DIEPSIZ0_XFRSIZ_MASK);
(max_size & OTG_DIEPSIZ0_XFRSIZ_MASK);
REBASE(OTG_DIEPCTL(addr)) |=
OTG_FS_DIEPCTL0_EPENA | OTG_FS_DIEPCTL0_SNAK | (type << 18)
| OTG_FS_DIEPCTL0_USBAEP | OTG_FS_DIEPCTLX_SD0PID
OTG_DIEPCTL0_EPENA | OTG_DIEPCTL0_SNAK | (type << 18)
| OTG_DIEPCTL0_USBAEP | OTG_DIEPCTLX_SD0PID
| (addr << 22) | max_size;
if (callback) {
@@ -101,12 +101,12 @@ void stm32fx07_ep_setup(usbd_device *usbd_dev, uint8_t addr, uint8_t type,
}
if (!dir) {
usbd_dev->doeptsiz[addr] = OTG_FS_DIEPSIZ0_PKTCNT |
(max_size & OTG_FS_DIEPSIZ0_XFRSIZ_MASK);
usbd_dev->doeptsiz[addr] = OTG_DIEPSIZ0_PKTCNT |
(max_size & OTG_DIEPSIZ0_XFRSIZ_MASK);
REBASE(OTG_DOEPTSIZ(addr)) = usbd_dev->doeptsiz[addr];
REBASE(OTG_DOEPCTL(addr)) |= OTG_FS_DOEPCTL0_EPENA |
OTG_FS_DOEPCTL0_USBAEP | OTG_FS_DIEPCTL0_CNAK |
OTG_FS_DOEPCTLX_SD0PID | (type << 18) | max_size;
REBASE(OTG_DOEPCTL(addr)) |= OTG_DOEPCTL0_EPENA |
OTG_DOEPCTL0_USBAEP | OTG_DIEPCTL0_CNAK |
OTG_DOEPCTLX_SD0PID | (type << 18) | max_size;
if (callback) {
usbd_dev->user_callback_ctr[addr][USB_TRANSACTION_OUT] =
@@ -125,9 +125,9 @@ void stm32fx07_ep_stall_set(usbd_device *usbd_dev, uint8_t addr, uint8_t stall)
{
if (addr == 0) {
if (stall) {
REBASE(OTG_DIEPCTL(addr)) |= OTG_FS_DIEPCTL0_STALL;
REBASE(OTG_DIEPCTL(addr)) |= OTG_DIEPCTL0_STALL;
} else {
REBASE(OTG_DIEPCTL(addr)) &= ~OTG_FS_DIEPCTL0_STALL;
REBASE(OTG_DIEPCTL(addr)) &= ~OTG_DIEPCTL0_STALL;
}
}
@@ -135,17 +135,17 @@ void stm32fx07_ep_stall_set(usbd_device *usbd_dev, uint8_t addr, uint8_t stall)
addr &= 0x7F;
if (stall) {
REBASE(OTG_DIEPCTL(addr)) |= OTG_FS_DIEPCTL0_STALL;
REBASE(OTG_DIEPCTL(addr)) |= OTG_DIEPCTL0_STALL;
} else {
REBASE(OTG_DIEPCTL(addr)) &= ~OTG_FS_DIEPCTL0_STALL;
REBASE(OTG_DIEPCTL(addr)) |= OTG_FS_DIEPCTLX_SD0PID;
REBASE(OTG_DIEPCTL(addr)) &= ~OTG_DIEPCTL0_STALL;
REBASE(OTG_DIEPCTL(addr)) |= OTG_DIEPCTLX_SD0PID;
}
} else {
if (stall) {
REBASE(OTG_DOEPCTL(addr)) |= OTG_FS_DOEPCTL0_STALL;
REBASE(OTG_DOEPCTL(addr)) |= OTG_DOEPCTL0_STALL;
} else {
REBASE(OTG_DOEPCTL(addr)) &= ~OTG_FS_DOEPCTL0_STALL;
REBASE(OTG_DOEPCTL(addr)) |= OTG_FS_DOEPCTLX_SD0PID;
REBASE(OTG_DOEPCTL(addr)) &= ~OTG_DOEPCTL0_STALL;
REBASE(OTG_DOEPCTL(addr)) |= OTG_DOEPCTLX_SD0PID;
}
}
}
@@ -155,10 +155,10 @@ uint8_t stm32fx07_ep_stall_get(usbd_device *usbd_dev, uint8_t addr)
/* Return non-zero if STALL set. */
if (addr & 0x80) {
return (REBASE(OTG_DIEPCTL(addr & 0x7f)) &
OTG_FS_DIEPCTL0_STALL) ? 1 : 0;
OTG_DIEPCTL0_STALL) ? 1 : 0;
} else {
return (REBASE(OTG_DOEPCTL(addr)) &
OTG_FS_DOEPCTL0_STALL) ? 1 : 0;
OTG_DOEPCTL0_STALL) ? 1 : 0;
}
}
@@ -172,9 +172,9 @@ void stm32fx07_ep_nak_set(usbd_device *usbd_dev, uint8_t addr, uint8_t nak)
usbd_dev->force_nak[addr] = nak;
if (nak) {
REBASE(OTG_DOEPCTL(addr)) |= OTG_FS_DOEPCTL0_SNAK;
REBASE(OTG_DOEPCTL(addr)) |= OTG_DOEPCTL0_SNAK;
} else {
REBASE(OTG_DOEPCTL(addr)) |= OTG_FS_DOEPCTL0_CNAK;
REBASE(OTG_DOEPCTL(addr)) |= OTG_DOEPCTL0_CNAK;
}
}
@@ -187,14 +187,14 @@ uint16_t stm32fx07_ep_write_packet(usbd_device *usbd_dev, uint8_t addr,
addr &= 0x7F;
/* Return if endpoint is already enabled. */
if (REBASE(OTG_DIEPTSIZ(addr)) & OTG_FS_DIEPSIZ0_PKTCNT) {
if (REBASE(OTG_DIEPTSIZ(addr)) & OTG_DIEPSIZ0_PKTCNT) {
return 0;
}
/* Enable endpoint for transmission. */
REBASE(OTG_DIEPTSIZ(addr)) = OTG_FS_DIEPSIZ0_PKTCNT | len;
REBASE(OTG_DIEPCTL(addr)) |= OTG_FS_DIEPCTL0_EPENA |
OTG_FS_DIEPCTL0_CNAK;
REBASE(OTG_DIEPTSIZ(addr)) = OTG_DIEPSIZ0_PKTCNT | len;
REBASE(OTG_DIEPCTL(addr)) |= OTG_DIEPCTL0_EPENA |
OTG_DIEPCTL0_CNAK;
volatile uint32_t *fifo = REBASE_FIFO(addr);
/* Copy buffer to endpoint FIFO, note - memcpy does not work */
@@ -226,9 +226,9 @@ uint16_t stm32fx07_ep_read_packet(usbd_device *usbd_dev, uint8_t addr,
}
REBASE(OTG_DOEPTSIZ(addr)) = usbd_dev->doeptsiz[addr];
REBASE(OTG_DOEPCTL(addr)) |= OTG_FS_DOEPCTL0_EPENA |
REBASE(OTG_DOEPCTL(addr)) |= OTG_DOEPCTL0_EPENA |
(usbd_dev->force_nak[addr] ?
OTG_FS_DOEPCTL0_SNAK : OTG_FS_DOEPCTL0_CNAK);
OTG_DOEPCTL0_SNAK : OTG_DOEPCTL0_CNAK);
return len;
}
@@ -239,34 +239,34 @@ void stm32fx07_poll(usbd_device *usbd_dev)
uint32_t intsts = REBASE(OTG_GINTSTS);
int i;
if (intsts & OTG_FS_GINTSTS_ENUMDNE) {
if (intsts & OTG_GINTSTS_ENUMDNE) {
/* Handle USB RESET condition. */
REBASE(OTG_GINTSTS) = OTG_FS_GINTSTS_ENUMDNE;
REBASE(OTG_GINTSTS) = OTG_GINTSTS_ENUMDNE;
usbd_dev->fifo_mem_top = usbd_dev->driver->rx_fifo_size;
_usbd_reset(usbd_dev);
return;
}
/* Note: RX and TX handled differently in this device. */
if (intsts & OTG_FS_GINTSTS_RXFLVL) {
if (intsts & OTG_GINTSTS_RXFLVL) {
/* Receive FIFO non-empty. */
uint32_t rxstsp = REBASE(OTG_GRXSTSP);
uint32_t pktsts = rxstsp & OTG_FS_GRXSTSP_PKTSTS_MASK;
if ((pktsts != OTG_FS_GRXSTSP_PKTSTS_OUT) &&
(pktsts != OTG_FS_GRXSTSP_PKTSTS_SETUP)) {
uint32_t pktsts = rxstsp & OTG_GRXSTSP_PKTSTS_MASK;
if ((pktsts != OTG_GRXSTSP_PKTSTS_OUT) &&
(pktsts != OTG_GRXSTSP_PKTSTS_SETUP)) {
return;
}
uint8_t ep = rxstsp & OTG_FS_GRXSTSP_EPNUM_MASK;
uint8_t ep = rxstsp & OTG_GRXSTSP_EPNUM_MASK;
uint8_t type;
if (pktsts == OTG_FS_GRXSTSP_PKTSTS_SETUP) {
if (pktsts == OTG_GRXSTSP_PKTSTS_SETUP) {
type = USB_TRANSACTION_SETUP;
} else {
type = USB_TRANSACTION_OUT;
}
/* Save packet size for stm32f107_ep_read_packet(). */
usbd_dev->rxbcnt = (rxstsp & OTG_FS_GRXSTSP_BCNT_MASK) >> 4;
usbd_dev->rxbcnt = (rxstsp & OTG_GRXSTSP_BCNT_MASK) >> 4;
/*
* FIXME: Why is a delay needed here?
@@ -291,10 +291,10 @@ void stm32fx07_poll(usbd_device *usbd_dev)
/*
* There is no global interrupt flag for transmit complete.
* The XFRC bit must be checked in each OTG_FS_DIEPINT(x).
* The XFRC bit must be checked in each OTG_DIEPINT(x).
*/
for (i = 0; i < 4; i++) { /* Iterate over endpoints. */
if (REBASE(OTG_DIEPINT(i)) & OTG_FS_DIEPINTX_XFRC) {
if (REBASE(OTG_DIEPINT(i)) & OTG_DIEPINTX_XFRC) {
/* Transfer complete. */
if (usbd_dev->user_callback_ctr[i]
[USB_TRANSACTION_IN]) {
@@ -302,43 +302,43 @@ void stm32fx07_poll(usbd_device *usbd_dev)
[USB_TRANSACTION_IN](usbd_dev, i);
}
REBASE(OTG_DIEPINT(i)) = OTG_FS_DIEPINTX_XFRC;
REBASE(OTG_DIEPINT(i)) = OTG_DIEPINTX_XFRC;
}
}
if (intsts & OTG_FS_GINTSTS_USBSUSP) {
if (intsts & OTG_GINTSTS_USBSUSP) {
if (usbd_dev->user_callback_suspend) {
usbd_dev->user_callback_suspend();
}
REBASE(OTG_GINTSTS) = OTG_FS_GINTSTS_USBSUSP;
REBASE(OTG_GINTSTS) = OTG_GINTSTS_USBSUSP;
}
if (intsts & OTG_FS_GINTSTS_WKUPINT) {
if (intsts & OTG_GINTSTS_WKUPINT) {
if (usbd_dev->user_callback_resume) {
usbd_dev->user_callback_resume();
}
REBASE(OTG_GINTSTS) = OTG_FS_GINTSTS_WKUPINT;
REBASE(OTG_GINTSTS) = OTG_GINTSTS_WKUPINT;
}
if (intsts & OTG_FS_GINTSTS_SOF) {
if (intsts & OTG_GINTSTS_SOF) {
if (usbd_dev->user_callback_sof) {
usbd_dev->user_callback_sof();
}
REBASE(OTG_GINTSTS) = OTG_FS_GINTSTS_SOF;
REBASE(OTG_GINTSTS) = OTG_GINTSTS_SOF;
}
if (usbd_dev->user_callback_sof) {
REBASE(OTG_GINTMSK) |= OTG_FS_GINTMSK_SOFM;
REBASE(OTG_GINTMSK) |= OTG_GINTMSK_SOFM;
} else {
REBASE(OTG_GINTMSK) &= ~OTG_FS_GINTMSK_SOFM;
REBASE(OTG_GINTMSK) &= ~OTG_GINTMSK_SOFM;
}
}
void stm32fx07_disconnect(usbd_device *usbd_dev, bool disconnected)
{
if (disconnected) {
REBASE(OTG_DCTL) |= OTG_FS_DCTL_SDIS;
REBASE(OTG_DCTL) |= OTG_DCTL_SDIS;
} else {
REBASE(OTG_DCTL) &= ~OTG_FS_DCTL_SDIS;
REBASE(OTG_DCTL) &= ~OTG_DCTL_SDIS;
}
}