stm32/usb: otg_fs and otg_hs register definitions
* USB host register definitions added. * Extracted common register and bitfield definitions from 'otg_fs.h' and 'otg_hs.h' into new file 'otg_common.h'. Modified usb low-level drivers to adopt to new style of bitfields. * Fixed typo OTG_GOTGIN -> OTG_GOTGINT (according to the datasheet) Signed-off-by: Amir Hammad <amir.hammad@hotmail.com>
This commit is contained in:
Amir Hammad
committed by
Karl Palsson
Karl Palsson
parent
f4d6da9554
commit
6357630a90
@@ -22,66 +22,23 @@
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/stm32/otg_common.h>
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/* Core Global Control and Status Registers */
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#define OTG_GOTGCTL 0x000
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#define OTG_GOTGIN 0x004
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#define OTG_GAHBCFG 0x008
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#define OTG_GUSBCFG 0x00C
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#define OTG_GRSTCTL 0x010
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#define OTG_GINTSTS 0x014
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#define OTG_GINTMSK 0x018
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#define OTG_GRXSTSR 0x01C
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#define OTG_GRXSTSP 0x020
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#define OTG_GRXFSIZ 0x024
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#define OTG_GNPTXFSIZ 0x028
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#define OTG_GNPTXSTS 0x02C
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#define OTG_GCCFG 0x038
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#define OTG_CID 0x03C
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#define OTG_HPTXFSIZ 0x100
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#define OTG_DIEPTXF(x) (0x104 + 4*(x-1))
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/* OTG_HS specific registers */
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/* Host-mode Control and Status Registers */
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#define OTG_HCFG 0x400
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#define OTG_HFIR 0x404
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#define OTG_HFNUM 0x408
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#define OTG_HPTXSTS 0x410
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#define OTG_HAINT 0x414
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#define OTG_HAINTMSK 0x418
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#define OTG_HPRT 0x440
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#define OTG_HCCHARx 0x500
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#define OTG_HCINTx 0x508
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#define OTG_HCINTMSKx 0x50C
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#define OTG_HCTSIZx 0x510
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#define OTG_HCSPLT(x) (0x504 + 0x20*(x))
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#define OTG_HCDMA(x) (0x514 + 0x20*(x))
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/* Device-mode Control and Status Registers */
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#define OTG_DCFG 0x800
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#define OTG_DCTL 0x804
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#define OTG_DSTS 0x808
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#define OTG_DIEPMSK 0x810
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#define OTG_DOEPMSK 0x814
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#define OTG_DAINT 0x818
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#define OTG_DAINTMSK 0x81C
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#define OTG_DVBUSDIS 0x828
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#define OTG_DVBUSPULSE 0x82C
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#define OTG_DIEPEMPMSK 0x834
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#define OTG_DIEPCTL0 0x900
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#define OTG_DIEPCTL(x) (0x900 + 0x20*(x))
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#define OTG_DOEPCTL0 0xB00
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#define OTG_DOEPCTL(x) (0xB00 + 0x20*(x))
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#define OTG_DIEPINT(x) (0x908 + 0x20*(x))
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#define OTG_DOEPINT(x) (0xB08 + 0x20*(x))
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#define OTG_DIEPTSIZ0 0x910
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#define OTG_DOEPTSIZ0 0xB10
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#define OTG_DIEPTSIZ(x) (0x910 + 0x20*(x))
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#define OTG_DTXFSTS(x) (0x918 + 0x20*(x))
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#define OTG_DOEPTSIZ(x) (0xB10 + 0x20*(x))
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#define OTG_DEACHHINT 0x838
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#define OTG_DEACHHINTMSK 0x83C
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#define OTG_DIEPEACHMSK1 0x844
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#define OTG_DOEPEACHMSK1 0x884
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#define OTG_DIEPDMA(x) (0x914 + 0x20*(x))
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#define OTG_DOEPDMA(x) (0xB14 + 0x20*(x))
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/* Power and clock gating control and status register */
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#define OTG_PCGCCTL 0xE00
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/* Data FIFO */
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#define OTG_FIFO(x) (((x) + 1) << 12)
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/***********************************************************************/
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@@ -111,10 +68,12 @@
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#define OTG_HS_HAINT MMIO32(USB_OTG_HS_BASE + OTG_HAINT)
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#define OTG_HS_HAINTMSK MMIO32(USB_OTG_HS_BASE + OTG_HAINTMSK)
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#define OTG_HS_HPRT MMIO32(USB_OTG_HS_BASE + OTG_HPRT)
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#define OTG_HS_HCCHARx MMIO32(USB_OTG_HS_BASE + OTG_HCCHARx)
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#define OTG_HS_HCINTx MMIO32(USB_OTG_HS_BASE + OTG_HCINTx)
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#define OTG_HS_HCINTMSKx MMIO32(USB_OTG_HS_BASE + OTG_HCINTMSKx)
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#define OTG_HS_HCTSIZx MMIO32(USB_OTG_HS_BASE + OTG_HCTSIZx)
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#define OTG_HS_HCCHAR(x) MMIO32(USB_OTG_HS_BASE + OTG_HCCHAR(x))
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#define OTG_HS_HCSPLT(x) MMIO32(USB_OTG_HS_BASE + OTG_HCSPLT(x))
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#define OTG_HS_HCINT(x) MMIO32(USB_OTG_HS_BASE + OTG_HCINT(x))
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#define OTG_HS_HCINTMSK(x) MMIO32(USB_OTG_HS_BASE + OTG_HCINTMSK(x))
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#define OTG_HS_HCTSIZ(x) MMIO32(USB_OTG_HS_BASE + OTG_HCTSIZ(x))
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#define OTG_HS_HCDMA(x) MMIO32(USB_OTG_HS_BASE + OTG_HCDMA(x))
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/* Device-mode Control and Status Registers */
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#define OTG_HS_DCFG MMIO32(USB_OTG_HS_BASE + OTG_DCFG)
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@@ -140,6 +99,12 @@
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#define OTG_HS_DTXFSTS(x) MMIO32(USB_OTG_HS_BASE + OTG_DTXFSTS(x))
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#define OTG_HS_DOEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + \
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OTG_DOEPTSIZ(x))
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#define OTG_HS_DEACHHINT MMIO32(USB_OTG_HS_BASE + OTG_DEACHHINT)
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#define OTG_HS_DEACHHINTMSK MMIO32(USB_OTG_HS_BASE + OTG_DEACHHINTMSK)
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#define OTG_HS_DIEPEACHMSK MMIO32(USB_OTG_HS_BASE + OTG_DIEPEACHMSK1)
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#define OTG_HS_DOEPEACHMSK MMIO32(USB_OTG_HS_BASE + OTG_DOEPEACHMSK1)
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#define OTG_HS_DIEPDMA(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPDMA(x))
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#define OTG_HS_DOEPDMA(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPDMA(x))
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/* Power and clock gating control and status register */
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#define OTG_HS_PCGCCTL MMIO32(USB_OTG_HS_BASE + OTG_PCGCCTL)
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@@ -147,252 +112,52 @@
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/* Data FIFO */
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#define OTG_HS_FIFO(x) (&MMIO32(USB_OTG_HS_BASE + OTG_FIFO(x)))
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/* Global CSRs */
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/* OTG_HS USB control registers (OTG_FS_GOTGCTL) */
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#define OTG_HS_GOTGCTL_BSVLD (1 << 19)
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#define OTG_HS_GOTGCTL_ASVLD (1 << 18)
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#define OTG_HS_GOTGCTL_DBCT (1 << 17)
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#define OTG_HS_GOTGCTL_CIDSTS (1 << 16)
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#define OTG_HS_GOTGCTL_DHNPEN (1 << 11)
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#define OTG_HS_GOTGCTL_HSHNPEN (1 << 10)
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#define OTG_HS_GOTGCTL_HNPRQ (1 << 9)
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#define OTG_HS_GOTGCTL_HNGSCS (1 << 8)
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#define OTG_HS_GOTGCTL_SRQ (1 << 1)
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#define OTG_HS_GOTGCTL_SRQSCS (1 << 0)
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/* Device-mode CSRs*/
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/* OTG device each endpoint interrupt register (OTG_DEACHINT) */
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/* Bits 31:18 - Reserved */
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#define OTG_DEACHHINT_OEP1INT (1 << 17)
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/* Bits 16:2 - Reserved */
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#define OTG_DEACHHINT_IEP1INT (1 << 1)
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/* Bit 0 - Reserved */
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/* OTG_FS AHB configuration register (OTG_HS_GAHBCFG) */
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#define OTG_HS_GAHBCFG_GINT 0x0001
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#define OTG_HS_GAHBCFG_TXFELVL 0x0080
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#define OTG_HS_GAHBCFG_PTXFELVL 0x0100
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/* OTG_FS USB configuration register (OTG_HS_GUSBCFG) */
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#define OTG_HS_GUSBCFG_TOCAL 0x00000003
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#define OTG_HS_GUSBCFG_SRPCAP 0x00000100
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#define OTG_HS_GUSBCFG_HNPCAP 0x00000200
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#define OTG_HS_GUSBCFG_TRDT_MASK (0xf << 10)
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#define OTG_HS_GUSBCFG_TRDT_16BIT (0x5 << 10)
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#define OTG_HS_GUSBCFG_TRDT_8BIT (0x9 << 10)
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#define OTG_HS_GUSBCFG_NPTXRWEN 0x00004000
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#define OTG_HS_GUSBCFG_FHMOD 0x20000000
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#define OTG_HS_GUSBCFG_FDMOD 0x40000000
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#define OTG_HS_GUSBCFG_CTXPKT 0x80000000
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#define OTG_HS_GUSBCFG_PHYSEL (1 << 6)
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/* OTG_FS reset register (OTG_HS_GRSTCTL) */
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#define OTG_HS_GRSTCTL_AHBIDL (1 << 31)
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/* Bits 30:11 - Reserved */
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#define OTG_HS_GRSTCTL_TXFNUM_MASK (0x1f << 6)
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#define OTG_HS_GRSTCTL_TXFFLSH (1 << 5)
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#define OTG_HS_GRSTCTL_RXFFLSH (1 << 4)
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/* Bit 3 - Reserved */
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#define OTG_HS_GRSTCTL_FCRST (1 << 2)
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#define OTG_HS_GRSTCTL_HSRST (1 << 1)
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#define OTG_HS_GRSTCTL_CSRST (1 << 0)
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/* OTG_FS interrupt status register (OTG_HS_GINTSTS) */
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#define OTG_HS_GINTSTS_WKUPINT (1 << 31)
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#define OTG_HS_GINTSTS_SRQINT (1 << 30)
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#define OTG_HS_GINTSTS_DISCINT (1 << 29)
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#define OTG_HS_GINTSTS_CIDSCHG (1 << 28)
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/* Bit 27 - Reserved */
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#define OTG_HS_GINTSTS_PTXFE (1 << 26)
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#define OTG_HS_GINTSTS_HCINT (1 << 25)
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#define OTG_HS_GINTSTS_HPRTINT (1 << 24)
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/* Bits 23:22 - Reserved */
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#define OTG_HS_GINTSTS_IPXFR (1 << 21)
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#define OTG_HS_GINTSTS_INCOMPISOOUT (1 << 21)
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#define OTG_HS_GINTSTS_IISOIXFR (1 << 20)
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#define OTG_HS_GINTSTS_OEPINT (1 << 19)
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#define OTG_HS_GINTSTS_IEPINT (1 << 18)
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/* Bits 17:16 - Reserved */
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#define OTG_HS_GINTSTS_EOPF (1 << 15)
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#define OTG_HS_GINTSTS_ISOODRP (1 << 14)
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#define OTG_HS_GINTSTS_ENUMDNE (1 << 13)
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#define OTG_HS_GINTSTS_USBRST (1 << 12)
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#define OTG_HS_GINTSTS_USBSUSP (1 << 11)
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#define OTG_HS_GINTSTS_ESUSP (1 << 10)
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/* Bits 9:8 - Reserved */
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#define OTG_HS_GINTSTS_GONAKEFF (1 << 7)
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#define OTG_HS_GINTSTS_GINAKEFF (1 << 6)
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#define OTG_HS_GINTSTS_NPTXFE (1 << 5)
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#define OTG_HS_GINTSTS_RXFLVL (1 << 4)
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#define OTG_HS_GINTSTS_SOF (1 << 3)
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#define OTG_HS_GINTSTS_OTGINT (1 << 2)
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#define OTG_HS_GINTSTS_MMIS (1 << 1)
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#define OTG_HS_GINTSTS_CMOD (1 << 0)
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/* OTG_FS interrupt mask register (OTG_HS_GINTMSK) */
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#define OTG_HS_GINTMSK_MMISM 0x00000002
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#define OTG_HS_GINTMSK_OTGINT 0x00000004
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#define OTG_HS_GINTMSK_SOFM 0x00000008
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#define OTG_HS_GINTMSK_RXFLVLM 0x00000010
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#define OTG_HS_GINTMSK_NPTXFEM 0x00000020
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#define OTG_HS_GINTMSK_GINAKEFFM 0x00000040
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#define OTG_HS_GINTMSK_GONAKEFFM 0x00000080
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#define OTG_HS_GINTMSK_ESUSPM 0x00000400
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#define OTG_HS_GINTMSK_USBSUSPM 0x00000800
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#define OTG_HS_GINTMSK_USBRST 0x00001000
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#define OTG_HS_GINTMSK_ENUMDNEM 0x00002000
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#define OTG_HS_GINTMSK_ISOODRPM 0x00004000
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#define OTG_HS_GINTMSK_EOPFM 0x00008000
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#define OTG_HS_GINTMSK_EPMISM 0x00020000
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#define OTG_HS_GINTMSK_IEPINT 0x00040000
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#define OTG_HS_GINTMSK_OEPINT 0x00080000
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#define OTG_HS_GINTMSK_IISOIXFRM 0x00100000
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#define OTG_HS_GINTMSK_IISOOXFRM 0x00200000
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#define OTG_HS_GINTMSK_IPXFRM 0x00200000
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#define OTG_HS_GINTMSK_PRTIM 0x01000000
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#define OTG_HS_GINTMSK_HCIM 0x02000000
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#define OTG_HS_GINTMSK_PTXFEM 0x04000000
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#define OTG_HS_GINTMSK_CIDSCHGM 0x10000000
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#define OTG_HS_GINTMSK_DISCINT 0x20000000
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#define OTG_HS_GINTMSK_SRQIM 0x40000000
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#define OTG_HS_GINTMSK_WUIM 0x80000000
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/* OTG_FS Receive Status Pop Register (OTG_HS_GRXSTSP) */
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/* Bits 31:25 - Reserved */
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#define OTG_HS_GRXSTSP_FRMNUM_MASK (0xf << 21)
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#define OTG_HS_GRXSTSP_PKTSTS_MASK (0xf << 17)
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#define OTG_HS_GRXSTSP_PKTSTS_GOUTNAK (0x1 << 17)
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#define OTG_HS_GRXSTSP_PKTSTS_OUT (0x2 << 17)
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#define OTG_HS_GRXSTSP_PKTSTS_OUT_COMP (0x3 << 17)
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#define OTG_HS_GRXSTSP_PKTSTS_SETUP_COMP (0x4 << 17)
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#define OTG_HS_GRXSTSP_PKTSTS_SETUP (0x6 << 17)
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#define OTG_HS_GRXSTSP_DPID_MASK (0x3 << 15)
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#define OTG_HS_GRXSTSP_DPID_DATA0 (0x0 << 15)
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#define OTG_HS_GRXSTSP_DPID_DATA1 (0x2 << 15)
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#define OTG_HS_GRXSTSP_DPID_DATA2 (0x1 << 15)
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#define OTG_HS_GRXSTSP_DPID_MDATA (0x3 << 15)
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#define OTG_HS_GRXSTSP_BCNT_MASK (0x7ff << 4)
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#define OTG_HS_GRXSTSP_EPNUM_MASK (0xf << 0)
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/* OTG_FS general core configuration register (OTG_HS_GCCFG) */
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/* Bits 31:21 - Reserved */
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#define OTG_HS_GCCFG_SOFOUTEN (1 << 20)
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#define OTG_HS_GCCFG_VBUSBSEN (1 << 19)
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#define OTG_HS_GCCFG_VBUSASEN (1 << 18)
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/* Bit 17 - Reserved */
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#define OTG_HS_GCCFG_PWRDWN (1 << 16)
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/* Bits 15:0 - Reserved */
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/* Device-mode CSRs */
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/* OTG_FS device control register (OTG_HS_DCTL) */
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/* Bits 31:12 - Reserved */
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#define OTG_HS_DCTL_POPRGDNE (1 << 11)
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#define OTG_HS_DCTL_CGONAK (1 << 10)
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#define OTG_HS_DCTL_SGONAK (1 << 9)
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#define OTG_HS_DCTL_SGINAK (1 << 8)
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#define OTG_HS_DCTL_TCTL_MASK (7 << 4)
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#define OTG_HS_DCTL_GONSTS (1 << 3)
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#define OTG_HS_DCTL_GINSTS (1 << 2)
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#define OTG_HS_DCTL_SDIS (1 << 1)
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#define OTG_HS_DCTL_RWUSIG (1 << 0)
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/* OTG_FS device configuration register (OTG_HS_DCFG) */
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#define OTG_HS_DCFG_DSPD 0x0003
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#define OTG_HS_DCFG_NZLSOHSK 0x0004
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#define OTG_HS_DCFG_DAD 0x07F0
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#define OTG_HS_DCFG_PFIVL 0x1800
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/* OTG_FS Device IN Endpoint Common Interrupt Mask Register (OTG_HS_DIEPMSK) */
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/* Bits 31:10 - Reserved */
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#define OTG_HS_DIEPMSK_BIM (1 << 9)
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#define OTG_HS_DIEPMSK_TXFURM (1 << 8)
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/* OTG device each in endpoint-1 interrupt register (OTG_DIEPEACHMSK1) */
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/* Bits 31:14 - Reserved */
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#define OTG_DIEPEACHMSK1_NAKM (1 << 13)
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/* Bits 12:10 - Reserved */
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#define OTG_DIEPEACHMSK1_BIM (1 << 9)
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#define OTG_DIEPEACHMSK1_TXFURM (1 << 8)
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/* Bit 7 - Reserved */
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#define OTG_HS_DIEPMSK_INEPNEM (1 << 6)
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#define OTG_HS_DIEPMSK_INEPNMM (1 << 5)
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#define OTG_HS_DIEPMSK_ITTXFEMSK (1 << 4)
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#define OTG_HS_DIEPMSK_TOM (1 << 3)
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#define OTG_DIEPEACHMSK1_INEPNEM (1 << 6)
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#define OTG_DIEPEACHMSK1_INEPNMM (1 << 5)
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#define OTG_DIEPEACHMSK1_ITTXFEMSK (1 << 4)
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#define OTG_DIEPEACHMSK1_TOM (1 << 3)
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/* Bit 2 - Reserved */
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#define OTG_HS_DIEPMSK_EPDM (1 << 1)
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#define OTG_HS_DIEPMSK_XFRCM (1 << 0)
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#define OTG_DIEPEACHMSK1_EPDM (1 << 1)
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#define OTG_DIEPEACHMSK1_XFRCM (1 << 0)
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/* OTG_FS Device OUT Endpoint Common Interrupt Mask Register (OTG_HS_DOEPMSK) */
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/* Bits 31:10 - Reserved */
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#define OTG_HS_DOEPMSK_BOIM (1 << 9)
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#define OTG_HS_DOEPMSK_OPEM (1 << 8)
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/* Bit 7 - Reserved */
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#define OTG_HS_DOEPMSK_B2BSTUP (1 << 6)
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/* Bit 5 - Reserved */
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#define OTG_HS_DOEPMSK_OTEPDM (1 << 4)
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#define OTG_HS_DOEPMSK_STUPM (1 << 3)
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/* Bit 2 - Reserved */
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#define OTG_HS_DOEPMSK_EPDM (1 << 1)
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#define OTG_HS_DOEPMSK_XFRCM (1 << 0)
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/* OTG device each OUT endpoint-1 interrupt register (OTG_DOEPEACHMSK1) */
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/* Bits 31:15 - Reserved */
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#define OTG_DOEPEACHMSK1_NYETM (1 << 14)
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#define OTG_DOEPEACHMSK1_NAKM (1 << 13)
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#define OTG_DOEPEACHMSK1_BERRM (1 << 12)
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/* Bits 11:10 - Reserved */
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||||
#define OTG_DOEPEACHMSK1_BIM (1 << 9)
|
||||
#define OTG_DOEPEACHMSK1_OPEM (1 << 8)
|
||||
/* Bits 7:3 - Reserved */
|
||||
#define OTG_DOEPEACHMSK1_AHBERRM (1 << 2)
|
||||
#define OTG_DOEPEACHMSK1_EPDM (1 << 1)
|
||||
#define OTG_DOEPEACHMSK1_XFRCM (1 << 0)
|
||||
|
||||
/* OTG_FS Device Control IN Endpoint 0 Control Register (OTG_HS_DIEPCTL0) */
|
||||
#define OTG_HS_DIEPCTL0_EPENA (1 << 31)
|
||||
#define OTG_HS_DIEPCTL0_EPDIS (1 << 30)
|
||||
/* Bits 29:28 - Reserved */
|
||||
#define OTG_HS_DIEPCTLX_SD0PID (1 << 28)
|
||||
#define OTG_HS_DIEPCTL0_SNAK (1 << 27)
|
||||
#define OTG_HS_DIEPCTL0_CNAK (1 << 26)
|
||||
#define OTG_HS_DIEPCTL0_TXFNUM_MASK (0xf << 22)
|
||||
#define OTG_HS_DIEPCTL0_STALL (1 << 21)
|
||||
/* Bit 20 - Reserved */
|
||||
#define OTG_HS_DIEPCTL0_EPTYP_MASK (0x3 << 18)
|
||||
#define OTG_HS_DIEPCTL0_NAKSTS (1 << 17)
|
||||
/* Bit 16 - Reserved */
|
||||
#define OTG_HS_DIEPCTL0_USBAEP (1 << 15)
|
||||
/* Bits 14:2 - Reserved */
|
||||
#define OTG_HS_DIEPCTL0_MPSIZ_MASK (0x3 << 0)
|
||||
#define OTG_HS_DIEPCTL0_MPSIZ_64 (0x0 << 0)
|
||||
#define OTG_HS_DIEPCTL0_MPSIZ_32 (0x1 << 0)
|
||||
#define OTG_HS_DIEPCTL0_MPSIZ_16 (0x2 << 0)
|
||||
#define OTG_HS_DIEPCTL0_MPSIZ_8 (0x3 << 0)
|
||||
|
||||
/* OTG_FS Device Control OUT Endpoint 0 Control Register (OTG_HS_DOEPCTL0) */
|
||||
#define OTG_HS_DOEPCTL0_EPENA (1 << 31)
|
||||
#define OTG_HS_DOEPCTL0_EPDIS (1 << 30)
|
||||
/* Bits 29:28 - Reserved */
|
||||
#define OTG_HS_DOEPCTLX_SD0PID (1 << 28)
|
||||
#define OTG_HS_DOEPCTL0_SNAK (1 << 27)
|
||||
#define OTG_HS_DOEPCTL0_CNAK (1 << 26)
|
||||
/* Bits 25:22 - Reserved */
|
||||
#define OTG_HS_DOEPCTL0_STALL (1 << 21)
|
||||
#define OTG_HS_DOEPCTL0_SNPM (1 << 20)
|
||||
#define OTG_HS_DOEPCTL0_EPTYP_MASK (0x3 << 18)
|
||||
#define OTG_HS_DOEPCTL0_NAKSTS (1 << 17)
|
||||
/* Bit 16 - Reserved */
|
||||
#define OTG_HS_DOEPCTL0_USBAEP (1 << 15)
|
||||
/* Bits 14:2 - Reserved */
|
||||
#define OTG_HS_DOEPCTL0_MPSIZ_MASK (0x3 << 0)
|
||||
#define OTG_HS_DOEPCTL0_MPSIZ_64 (0x0 << 0)
|
||||
#define OTG_HS_DOEPCTL0_MPSIZ_32 (0x1 << 0)
|
||||
#define OTG_HS_DOEPCTL0_MPSIZ_16 (0x2 << 0)
|
||||
#define OTG_HS_DOEPCTL0_MPSIZ_8 (0x3 << 0)
|
||||
|
||||
/* OTG_FS Device IN Endpoint Interrupt Register (OTG_HS_DIEPINTx) */
|
||||
/* Bits 31:8 - Reserved */
|
||||
#define OTG_HS_DIEPINTX_TXFE (1 << 7)
|
||||
#define OTG_HS_DIEPINTX_INEPNE (1 << 6)
|
||||
/* Bit 5 - Reserved */
|
||||
#define OTG_HS_DIEPINTX_ITTXFE (1 << 4)
|
||||
#define OTG_HS_DIEPINTX_TOC (1 << 3)
|
||||
/* Bit 2 - Reserved */
|
||||
#define OTG_HS_DIEPINTX_EPDISD (1 << 1)
|
||||
#define OTG_HS_DIEPINTX_XFRC (1 << 0)
|
||||
|
||||
/* OTG_FS Device IN Endpoint Interrupt Register (OTG_HS_DOEPINTx) */
|
||||
/* Bits 31:7 - Reserved */
|
||||
#define OTG_HS_DOEPINTX_B2BSTUP (1 << 6)
|
||||
/* Bit 5 - Reserved */
|
||||
#define OTG_HS_DOEPINTX_OTEPDIS (1 << 4)
|
||||
#define OTG_HS_DOEPINTX_STUP (1 << 3)
|
||||
/* Bit 2 - Reserved */
|
||||
#define OTG_HS_DOEPINTX_EPDISD (1 << 1)
|
||||
#define OTG_HS_DOEPINTX_XFRC (1 << 0)
|
||||
|
||||
/* OTG_FS Device OUT Endpoint 0 Transfer Size Register (OTG_HS_DOEPTSIZ0) */
|
||||
/* Bit 31 - Reserved */
|
||||
#define OTG_HS_DIEPSIZ0_STUPCNT_1 (0x1 << 29)
|
||||
#define OTG_HS_DIEPSIZ0_STUPCNT_2 (0x2 << 29)
|
||||
#define OTG_HS_DIEPSIZ0_STUPCNT_3 (0x3 << 29)
|
||||
#define OTG_HS_DIEPSIZ0_STUPCNT_MASK (0x3 << 29)
|
||||
/* Bits 28:20 - Reserved */
|
||||
#define OTG_HS_DIEPSIZ0_PKTCNT (1 << 19)
|
||||
/* Bits 18:7 - Reserved */
|
||||
#define OTG_HS_DIEPSIZ0_XFRSIZ_MASK (0x7f << 0)
|
||||
/* Host-mode CSRs */
|
||||
/* OTG host channel-x split control register (OTG_HCSPLTx) */
|
||||
#define OTG_HCSPLT_SPLITEN (1 << 31)
|
||||
/* Bits 30:17 - Reserved */
|
||||
#define OTG_HCSPLT_COMPLSPLT (1 << 16)
|
||||
#define OTG_HCSPLT_XACTPOS_ALL (0x3 << 14)
|
||||
#define OTG_HCSPLT_XACTPOS_BEGIN (0x2 << 14)
|
||||
#define OTG_HCSPLT_XACTPOS_MID (0x0 << 14)
|
||||
#define OTG_HCSPLT_XACTPOS_END (0x1 << 14)
|
||||
#define OTG_HCSPLT_HUBADDR_MASK (0x7f << 7)
|
||||
#define OTG_HCSPLT_PORTADDR_MASK (0x7f << 0)
|
||||
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user