From 62e66359921247a3f758bc302345f536eea6fb85 Mon Sep 17 00:00:00 2001 From: Piotr Esden-Tempski Date: Thu, 4 Jul 2013 21:10:56 -0700 Subject: [PATCH] [Style] Fixed style in the newly added F3 code. --- .../stm32/common/gpio_common_f234.h | 2 +- .../libopencm3/stm32/common/gpio_common_f24.h | 4 +- include/libopencm3/stm32/f3/adc.h | 60 +- include/libopencm3/stm32/f3/crc.h | 6 +- include/libopencm3/stm32/f3/i2c.h | 25 +- include/libopencm3/stm32/f3/rcc.h | 142 ++--- include/libopencm3/stm32/f3/spi.h | 4 +- include/libopencm3/stm32/f3/usart.h | 8 +- lib/sam/common/usart.c | 1 - lib/stm32/f1/spi.c | 1 - lib/stm32/f3/adc.c | 545 ++++++++++-------- lib/stm32/f3/gpio.c | 30 +- lib/stm32/f3/i2c.c | 257 +++++---- lib/stm32/f3/rcc.c | 186 +++--- lib/stm32/f3/spi.c | 2 +- lib/stm32/f3/usart.c | 4 +- 16 files changed, 693 insertions(+), 584 deletions(-) diff --git a/include/libopencm3/stm32/common/gpio_common_f234.h b/include/libopencm3/stm32/common/gpio_common_f234.h index 5d52635e..0b4191db 100644 --- a/include/libopencm3/stm32/common/gpio_common_f234.h +++ b/include/libopencm3/stm32/common/gpio_common_f234.h @@ -54,7 +54,7 @@ specific memorymap.h header before including this header file.*/ /**@}*/ -/* --- GPIO registers for STM32F2, STM32F3 and STM32F4 --------------------------- */ +/* --- GPIO registers for STM32F2, STM32F3 and STM32F4 --------------------- */ /* Port mode register (GPIOx_MODER) */ #define GPIO_MODER(port) MMIO32(port + 0x00) diff --git a/include/libopencm3/stm32/common/gpio_common_f24.h b/include/libopencm3/stm32/common/gpio_common_f24.h index d9f7ecf7..2b37b97f 100644 --- a/include/libopencm3/stm32/common/gpio_common_f24.h +++ b/include/libopencm3/stm32/common/gpio_common_f24.h @@ -51,7 +51,7 @@ specific memorymap.h header before including this header file.*/ #define GPIOI GPIO_PORT_I_BASE /**@}*/ -/* --- GPIO registers for STM32F2, STM32F3 and STM32F4 --------------------------- */ +/* --- GPIO registers for STM32F2, STM32F3 and STM32F4 --------------------- */ /* Port mode register (GPIOx_MODER) */ #define GPIOG_MODER GPIO_MODER(GPIOG) @@ -108,4 +108,4 @@ specific memorymap.h header before including this header file.*/ #else #warning "gpio_common_f24.h should not be included explicitly, only via gpio.h" #endif -/** @endcond */ \ No newline at end of file +/** @endcond */ diff --git a/include/libopencm3/stm32/f3/adc.h b/include/libopencm3/stm32/f3/adc.h index dacba8d7..6bac5acc 100644 --- a/include/libopencm3/stm32/f3/adc.h +++ b/include/libopencm3/stm32/f3/adc.h @@ -416,7 +416,10 @@ /* OVRMOD: Overrun Mode */ #define ADC_CFGR_OVRMOD (1 << 12) -/* EXTEN[1:0]: External trigger enable and polarity selection for regular channels */ +/* + * EXTEN[1:0]: External trigger enable and polarity selection for regular + * channels + */ #define ADC_CFGR_EXTEN_DISABLED (0x0 << 10) #define ADC_CFGR_EXTEN_RISING_EDGE (0x1 << 10) #define ADC_CFGR_EXTEN_FALLING_EDGE (0x2 << 10) @@ -619,7 +622,10 @@ /* Bits 12:8 JSQ1[4:0]: 1st conversion in the injected sequence */ -/* JEXTEN[1:0]: External Trigger Enable and Polarity Selection for injected channels */ +/* + * JEXTEN[1:0]: External Trigger Enable and Polarity Selection for injected + * channels + */ #define ADC_JSQR_JEXTEN_DISABLED (0x0 << 6) #define ADC_JSQR_JEXTEN_RISING_EDGE (0x1 << 6) #define ADC_JSQR_JEXTEN_FALLING_EDGE (0x2 << 6) @@ -661,7 +667,10 @@ /* Bits 30:26 OFFSET1_CH[4:0]: Channel selection for the Data offset 1 */ -/* Bits 11:0 OFFSET1[11:0]: Data offset y for the channel programmed into bits OFFSET1_CH[4:0] */ +/* + * Bits 11:0 OFFSET1[11:0]: Data offset y for the channel programmed into bits + * OFFSET1_CH[4:0] + */ /*------- ADC_OFR2 values ---------*/ @@ -671,7 +680,10 @@ /* Bits 30:26 OFFSET2_CH[4:0]: Channel selection for the Data offset 2 */ -/* Bits 11:0 OFFSET2[11:0]: Data offset y for the channel programmed into bits OFFSET2_CH[4:0] */ +/* + * Bits 11:0 OFFSET2[11:0]: Data offset y for the channel programmed into bits + * OFFSET2_CH[4:0] + */ /*------- ADC_OFR3 values ---------*/ @@ -681,7 +693,10 @@ /* Bits 30:26 OFFSET3_CH[4:0]: Channel selection for the Data offset 3 */ -/* Bits 11:0 OFFSET3[11:0]: Data offset y for the channel programmed into bits OFFSET3_CH[4:0] */ +/* + * Bits 11:0 OFFSET3[11:0]: Data offset y for the channel programmed into bits + * OFFSET3_CH[4:0] + */ /*------- ADC_OFR4 values ---------*/ @@ -691,7 +706,10 @@ /* Bits 30:26 OFFSET4_CH[4:0]: Channel selection for the Data offset 4 */ -/* Bits 11:0 OFFSET4[11:0]: Data offset y for the channel programmed into bits OFFSET4_CH[4:0] */ +/* + * Bits 11:0 OFFSET4[11:0]: Data offset y for the channel programmed into bits + * OFFSET4_CH[4:0] + */ /*------- ADC_JDRy, y= 1..4 values -------*/ @@ -795,13 +813,13 @@ /*-------- ADC_CCR values ------------*/ /* VBATEN: VBAT enable */ -#define ADC_CCR_VBATEN (1 << 24) +#define ADC_CCR_VBATEN (1 << 24) /* TSEN: Temperature sensor enable */ -#define ADC_CCR_TSEN (1 << 23) +#define ADC_CCR_TSEN (1 << 23) /* VREFEN: VREFINT enable */ -#define ADC_CCR_VREFEN (1 << 22) +#define ADC_CCR_VREFEN (1 << 22) /* CKMODE[1:0]: ADC clock mode */ #define ADC_CCR_CKMODE_CKX (0x0 << 16) @@ -813,7 +831,7 @@ /* MDMA[1:0]: Direct memory access mode for dual ADC mode */ #define ADC_CCR_MDMA_DISABLE (0x0 << 14) -//#define ADC_CCR_MDMA_RESERVED (0x1 << 14) +/*#define ADC_CCR_MDMA_RESERVED (0x1 << 14)*/ #define ADC_CCR_MDMA_12_10_BIT (0x2 << 14) #define ADC_CCR_MDMA_8_6_BIT (0x3 << 14) @@ -850,9 +868,10 @@ void adc_disable_discontinuous_mode_injected(uint32_t adc); void adc_enable_automatic_injected_group_conversion(uint32_t adc); void adc_disable_automatic_injected_group_conversion(uint32_t adc); void adc_enable_analog_watchdog_on_all_channels(uint32_t adc); -void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t channel); -//void adc_enable_scan_mode(uint32_t adc); -//void adc_disable_scan_mode(uint32_t adc); +void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, + uint8_t channel); +/*void adc_enable_scan_mode(uint32_t adc);*/ +/*void adc_disable_scan_mode(uint32_t adc);*/ void adc_enable_eoc_interrupt_injected(uint32_t adc); void adc_disable_eoc_interrupt_injected(uint32_t adc); void adc_enable_all_awd_interrupt(uint32_t adc); @@ -883,8 +902,10 @@ void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset); void adc_set_clk_prescale(uint32_t prescaler); void adc_set_multi_mode(uint32_t mode); -void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, uint32_t polarity); -void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, uint32_t polarity); +void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, + uint32_t polarity); +void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, + uint32_t polarity); void adc_set_resolution(uint32_t adc, uint16_t resolution); void adc_enable_overrun_interrupt(uint32_t adc); void adc_disable_overrun_interrupt(uint32_t adc); @@ -893,15 +914,12 @@ void adc_clear_overrun_flag(uint32_t adc); bool adc_awd(uint32_t adc); void adc_eoc_after_each(uint32_t adc); void adc_eoc_after_group(uint32_t adc); -//void adc_set_dma_continue(uint32_t adc); -//void adc_set_dma_terminate(uint32_t adc); +/*void adc_set_dma_continue(uint32_t adc);*/ +/*void adc_set_dma_terminate(uint32_t adc);*/ void adc_enable_temperature_sensor(void); void adc_disable_temperature_sensor(void); END_DECLS -#endif - - - +#endif diff --git a/include/libopencm3/stm32/f3/crc.h b/include/libopencm3/stm32/f3/crc.h index b6c66109..8e76f354 100644 --- a/include/libopencm3/stm32/f3/crc.h +++ b/include/libopencm3/stm32/f3/crc.h @@ -36,7 +36,7 @@ LGPL License Terms @ref lgpl_license #include #include -/* --- CRC registers ------------------------------------------------------- */ +/* --- CRC registers ------------------------------------------------------- */ /* Initial CRC value (CRC_INIT) */ #define CRC_INIT MMIO32(CRC_BASE + 0x10) @@ -61,11 +61,11 @@ LGPL License Terms @ref lgpl_license #define CRC_CR_POLYSIZE_8 (0x2 << 3) #define CRC_CR_POLYSIZE_7 (0x3 << 3) -/* --- CRC_INIT values ------------------------------------------------------- */ +/* --- CRC_INIT values ----------------------------------------------------- */ /* Bits 31:0 CRC_INIT: Programmable initial CRC value */ -/* --- CRC_POL values ------------------------------------------------------- */ +/* --- CRC_POL values ------------------------------------------------------ */ /* Bits 31:0 POL[31:0]: Programmable polynomial */ diff --git a/include/libopencm3/stm32/f3/i2c.h b/include/libopencm3/stm32/f3/i2c.h index 09cc9677..652f57e3 100644 --- a/include/libopencm3/stm32/f3/i2c.h +++ b/include/libopencm3/stm32/f3/i2c.h @@ -39,7 +39,7 @@ LGPL License Terms @ref lgpl_license /* --- Convenience macros -------------------------------------------------- */ /* I2C register base addresses (for convenience) */ -/****************************************************************************/ +/*****************************************************************************/ /** @defgroup i2c_reg_base I2C register base address @ingroup i2c_defines @@ -225,7 +225,7 @@ LGPL License Terms @ref lgpl_license /* OA1EN: Own Address 1 enable */ #define I2C_OAR1_OA1EN_DISABLE (0x0 << 15) -#define I2C_OAR1_OA1EN_ENABLE (0x1 <<15) +#define I2C_OAR1_OA1EN_ENABLE (0x1 << 15) /* OA1MODE Own Address 1 10-bit mode */ #define I2C_OAR1_OA1MODE (1 << 10) @@ -258,7 +258,7 @@ LGPL License Terms @ref lgpl_license /* OA2[7:1]: Interface address */ -/* --- I2Cx_TIMINGR values ---------------------------------------------------- */ +/* --- I2Cx_TIMINGR values ------------------------------------------------- */ /* PRESC[3:0]: Timing prescaler (31,28) */ #define I2C_TIMINGR_PRESC_SHIFT 28 @@ -280,12 +280,12 @@ LGPL License Terms @ref lgpl_license #define I2C_TIMINGR_SCLL_SHIFT 0 #define I2C_TIMINGR_SCLL_MASK (0xFF << I2C_TIMINGR_SCLL_SHIFT) -/* --- I2Cx_TIEMOUTR values ---------------------------------------------------- */ +/* --- I2Cx_TIEMOUTR values ------------------------------------------------ */ /* TEXTEN: Extended clock timeout enable */ #define I2C_TIEMOUTR_TEXTEN (1 << 31) -//Not clear yet. +/* XXX: Not clear yet. */ /* TIMEOUTB[11:0]: Bus timeout B */ /* TIMOUTEN: Clock timeout enable */ @@ -295,14 +295,14 @@ LGPL License Terms @ref lgpl_license #define I2C_TIEMOUTR_TIDLE_SCL_LOW (0x0 << 12) #define I2C_TIEMOUTR_TIDLE_SCL_SDA_HIGH (0x1 << 12) -//Not clear yet. +/* XXX: Not clear yet. */ /* TIMEOUTA[11:0]: Bus Timeout A */ -/* --- I2Cx_ISR values ---------------------------------------------------- */ +/* --- I2Cx_ISR values ----------------------------------------------------- */ /* Bits 31:24 Reserved, must be kept at reset value */ -//Not clear yet. +/* XXX: Not clear yet. */ /* ADDCODE[6:0]: Address match code (Slave mode) */ /* DIR: Transfer direction (Slave mode) */ @@ -354,7 +354,7 @@ LGPL License Terms @ref lgpl_license /* TXE: Transmit data register empty (transmitters) */ #define I2C_ISR_TXE (1 << 0) -/* --- I2Cx_ICR values ---------------------------------------------------- */ +/* --- I2Cx_ICR values ----------------------------------------------------- */ /* ALERTCF: Alert flag clear */ #define I2C_ICR_ALERTCF (1 << 13) @@ -435,12 +435,13 @@ void i2c_enable_rxdma(uint32_t i2c); void i2c_disable_rxdma(uint32_t i2c); void i2c_enable_txdma(uint32_t i2c); void i2c_disable_txdma(uint32_t i2c); -void write_i2c(uint32_t i2c, uint8_t i2c_addr, uint8_t reg, uint8_t size, uint8_t *data); -void read_i2c(uint32_t i2c, uint8_t i2c_addr, uint8_t reg, uint8_t size, uint8_t *data); +void write_i2c(uint32_t i2c, uint8_t i2c_addr, uint8_t reg, + uint8_t size, uint8_t *data); +void read_i2c(uint32_t i2c, uint8_t i2c_addr, uint8_t reg, + uint8_t size, uint8_t *data); END_DECLS /**@}*/ #endif - diff --git a/include/libopencm3/stm32/f3/rcc.h b/include/libopencm3/stm32/f3/rcc.h index d03826a4..45683499 100644 --- a/include/libopencm3/stm32/f3/rcc.h +++ b/include/libopencm3/stm32/f3/rcc.h @@ -67,7 +67,7 @@ /* MCO: Microcontroller clock output */ #define RCC_CFGR_MCO_SHIFT 24 #define RCC_CFGR_MCO_DISABLED 0x0 -//Reserve RCC_CFGR_MCO 0x1 +/*Reserve RCC_CFGR_MCO 0x1*/ #define RCC_CFGR_MCO_LSI 0x2 #define RCC_CFGR_MCO_LSE 0x3 #define RCC_CFGR_MCO_SYSCLK 0x4 @@ -100,47 +100,47 @@ /* PPRE2: APB high-speed prescaler (APB2) */ #define RCC_CFGR_PPRE2_SHIFT 11 -// 0XX: HCLK not divided -#define RCC_CFGR_PPRE2_DIV_NONE 0x0 +/* 0XX: HCLK not divided */ +#define RCC_CFGR_PPRE2_DIV_NONE 0x0 -#define RCC_CFGR_PPRE2_DIV_2 0x4 -#define RCC_CFGR_PPRE2_DIV_4 0x5 -#define RCC_CFGR_PPRE2_DIV_8 0x6 -#define RCC_CFGR_PPRE2_DIV_16 0x7 +#define RCC_CFGR_PPRE2_DIV_2 0x4 +#define RCC_CFGR_PPRE2_DIV_4 0x5 +#define RCC_CFGR_PPRE2_DIV_8 0x6 +#define RCC_CFGR_PPRE2_DIV_16 0x7 /* PPRE1:APB Low-speed prescaler (APB1) */ #define RCC_CFGR_PPRE1_SHIFT 8 -// 0XX: HCLK not divided -#define RCC_CFGR_PPRE1_DIV_NONE 0x0 -#define RCC_CFGR_PPRE1_DIV_2 0x4 -#define RCC_CFGR_PPRE1_DIV_4 0x5 -#define RCC_CFGR_PPRE1_DIV_8 0x6 -#define RCC_CFGR_PPRE1_DIV_16 0x7 +/* 0XX: HCLK not divided */ +#define RCC_CFGR_PPRE1_DIV_NONE 0x0 +#define RCC_CFGR_PPRE1_DIV_2 0x4 +#define RCC_CFGR_PPRE1_DIV_4 0x5 +#define RCC_CFGR_PPRE1_DIV_8 0x6 +#define RCC_CFGR_PPRE1_DIV_16 0x7 /* HPRE: HLCK prescaler */ -#define RCC_CFGR_HPRE_SHIFT 4 -// 0XXX: SYSCLK not divided -#define RCC_CFGR_HPRE_DIV_NONE 0x0 -#define RCC_CFGR_HPRE_DIV_2 0x8 -#define RCC_CFGR_HPRE_DIV_4 0x9 -#define RCC_CFGR_HPRE_DIV_8 0xA -#define RCC_CFGR_HPRE_DIV_16 0xB -#define RCC_CFGR_HPRE_DIV_64 0xC -#define RCC_CFGR_HPRE_DIV_128 0xD -#define RCC_CFGR_HPRE_DIV_256 0xE -#define RCC_CFGR_HPRE_DIV_512 0xF +#define RCC_CFGR_HPRE_SHIFT 4 +/* 0XXX: SYSCLK not divided */ +#define RCC_CFGR_HPRE_DIV_NONE 0x0 +#define RCC_CFGR_HPRE_DIV_2 0x8 +#define RCC_CFGR_HPRE_DIV_4 0x9 +#define RCC_CFGR_HPRE_DIV_8 0xA +#define RCC_CFGR_HPRE_DIV_16 0xB +#define RCC_CFGR_HPRE_DIV_64 0xC +#define RCC_CFGR_HPRE_DIV_128 0xD +#define RCC_CFGR_HPRE_DIV_256 0xE +#define RCC_CFGR_HPRE_DIV_512 0xF /* SWS: System clock switch status */ -#define RCC_CFGR_SWS_SHIFT 2 -#define RCC_CFGR_SWS_HSI 0x0 -#define RCC_CFGR_SWS_HSE 0x1 -#define RCC_CFGR_SWS_PLL 0x2 +#define RCC_CFGR_SWS_SHIFT 2 +#define RCC_CFGR_SWS_HSI 0x0 +#define RCC_CFGR_SWS_HSE 0x1 +#define RCC_CFGR_SWS_PLL 0x2 /* SW: System clock switch */ -#define RCC_CFGR_SW_SHIFT 0 -#define RCC_CFGR_SW_HSI 0x0 -#define RCC_CFGR_SW_HSE 0x1 -#define RCC_CFGR_SW_PLL 0x2 +#define RCC_CFGR_SW_SHIFT 0 +#define RCC_CFGR_SW_HSI 0x0 +#define RCC_CFGR_SW_HSE 0x1 +#define RCC_CFGR_SW_PLL 0x2 /* --- RCC_CIR values ------------------------------------------------------ */ @@ -203,7 +203,7 @@ #define RCC_APB1RSTR_TIM3RST (1 << 1) #define RCC_APB1RSTR_TIM2RST (1 << 0) -/* --- RCC_AHBENR values ------------------------------------------------- */ +/* --- RCC_AHBENR values --------------------------------------------------- */ #define RCC_AHBENR_ADC34EN (1 << 29) #define RCC_AHBENR_ADC12EN (1 << 28) #define RCC_AHBENR_TSCEN (1 << 24) @@ -215,7 +215,7 @@ #define RCC_AHBENR_IOPAEN (1 << 17) #define RCC_AHBENR_CRCEN (1 << 1) -/* --- RCC_APB2ENR values ------------------------------------------------- */ +/* --- RCC_APB2ENR values -------------------------------------------------- */ #define RCC_APB2ENR_TIM17EN (1 << 18) #define RCC_APB2ENR_TIM16EN (1 << 17) @@ -226,7 +226,7 @@ #define RCC_APB2ENR_TIM1EN (1 << 11) #define RCC_APB2ENR_SYSCFGEN (1 << 0) -/* --- RCC_APB1ENR values ------------------------------------------------- */ +/* --- RCC_APB1ENR values -------------------------------------------------- */ #define RCC_APB1ENR_DACEN (1 << 29) #define RCC_APB1ENR_PWREN (1 << 28) @@ -267,7 +267,7 @@ #define RCC_CSR_LSIRDY (1 << 1) #define RCC_CSR_LSION (1 << 0) -/* --- RCC_AHBRSTR values ------------------------------------------------------ */ +/* --- RCC_AHBRSTR values -------------------------------------------------- */ #define RCC_AHBRSTR_ADC34RST (1 << 29) #define RCC_AHBRSTR_ADC12RST (1 << 28) #define RCC_AHBRSTR_TSCRST (1 << 24) @@ -278,7 +278,7 @@ #define RCC_AHBRSTR_IOPBRST (1 << 18) #define RCC_AHBRSTR_IOPARST (1 << 17) -/* --- RCC_CFGR2 values ------------------------------------------------------ */ +/* --- RCC_CFGR2 values ---------------------------------------------------- */ /* ADC34PRES: ADC34 prescaler */ #define RCC_CFGR2_ADC34PRES_SHIFT 9 #define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_1 0x10 @@ -293,11 +293,11 @@ #define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_64 0x19 #define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_128 0x1A #define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_256 0x1B -//OTHERS -//#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV256 0x +/* OTHERS */ +/* #define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV256 0x */ /* ADC12PRES ADC prescaler */ -//REVISAR DIRECCIONES +/* REVISAR DIRECCIONES */ #define RCC_CFGR2_ADC12PRES_SHIFT 4 #define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_1 0x10 #define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_2 0x11 @@ -311,11 +311,11 @@ #define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_64 0x19 #define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_128 0x1A #define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_256 0x1B -//OTHERS -//#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV256 0x +/* OTHERS */ +/* #define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV256 0x */ /* PREDIV[3:0] PREDIV division factor */ -//REVISAR DIRECCIONES +/* REVISAR DIRECCIONES */ #define RCC_CFGR2_PREDIV_SHIFT 0 #define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_NONE 0x0 #define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_2 0x1 @@ -334,7 +334,7 @@ #define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_15 0xE #define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_16 0xF -/* --- RCC_CFGR3 values ------------------------------------------------------ */ +/* --- RCC_CFGR3 values ---------------------------------------------------- */ #define RCC_CFGR3_TIM8SW (1 << 9) #define RCC_CFGR3_TIM1SW (1 << 8) #define RCC_CFGR3_I2C2SW (1 << 5) @@ -377,48 +377,48 @@ extern uint32_t rcc_ppre2_frequency; /* --- Function prototypes ------------------------------------------------- */ -typedef enum { - CLOCK_44MHZ, - CLOCK_48MHZ, - CLOCK_64MHZ, - CLOCK_END -} rcc_clock_t; +enum rcc_clock { + CLOCK_44MHZ, + CLOCK_48MHZ, + CLOCK_64MHZ, + CLOCK_END +}; typedef struct { - uint8_t pll; - uint8_t pllsrc; - uint32_t flash_config; - uint8_t hpre; - uint8_t ppre1; - uint8_t ppre2; - uint8_t power_save; - uint32_t apb1_frequency; - uint32_t apb2_frequency; + uint8_t pll; + uint8_t pllsrc; + uint32_t flash_config; + uint8_t hpre; + uint8_t ppre1; + uint8_t ppre2; + uint8_t power_save; + uint32_t apb1_frequency; + uint32_t apb2_frequency; } clock_scale_t; extern const clock_scale_t hsi_8mhz[CLOCK_END]; -typedef enum { +enum osc { PLL, HSE, HSI, LSE, LSI } osc_t; BEGIN_DECLS -void rcc_osc_ready_int_clear(osc_t osc); -void rcc_osc_ready_int_enable(osc_t osc); -void rcc_osc_ready_int_disable(osc_t osc); -int rcc_osc_ready_int_flag(osc_t osc); +void rcc_osc_ready_int_clear(enum osc osc); +void rcc_osc_ready_int_enable(enum osc osc); +void rcc_osc_ready_int_disable(enum osc osc); +int rcc_osc_ready_int_flag(enum osc osc); void rcc_css_int_clear(void); int rcc_css_int_flag(void); -void rcc_wait_for_osc_ready(osc_t osc); -void rcc_wait_for_osc_not_ready(osc_t osc); -void rcc_wait_for_sysclk_status(osc_t osc); -void rcc_osc_on(osc_t osc); -void rcc_osc_off(osc_t osc); +void rcc_wait_for_osc_ready(enum osc osc); +void rcc_wait_for_osc_not_ready(enum osc osc); +void rcc_wait_for_sysclk_status(enum osc osc); +void rcc_osc_on(enum osc osc); +void rcc_osc_off(enum osc osc); void rcc_css_enable(void); void rcc_css_disable(void); -void rcc_osc_bypass_enable(osc_t osc); -void rcc_osc_bypass_disable(osc_t osc); +void rcc_osc_bypass_enable(enum osc osc); +void rcc_osc_bypass_disable(enum osc osc); void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en); void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en); void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset); diff --git a/include/libopencm3/stm32/f3/spi.h b/include/libopencm3/stm32/f3/spi.h index e4bbf277..6b13b3a5 100644 --- a/include/libopencm3/stm32/f3/spi.h +++ b/include/libopencm3/stm32/f3/spi.h @@ -63,7 +63,7 @@ LGPL License Terms @ref lgpl_license #define SPI_CR2_FRXTH (1 << 12) /* DS [3:0]: Data size */ -// 0x0 - 0x2 NOT USED +/* 0x0 - 0x2 NOT USED */ #define SPI_CR2_DS_4BIT (0x3 << 8) #define SPI_CR2_DS_5BIT (0x4 << 8) #define SPI_CR2_DS_6BIT (0x5 << 8) @@ -109,4 +109,4 @@ uint8_t spi_read8(uint32_t spi); END_DECLS -#endif \ No newline at end of file +#endif diff --git a/include/libopencm3/stm32/f3/usart.h b/include/libopencm3/stm32/f3/usart.h index 42b846c7..34f68a85 100644 --- a/include/libopencm3/stm32/f3/usart.h +++ b/include/libopencm3/stm32/f3/usart.h @@ -253,7 +253,7 @@ LGPL License Terms @ref lgpl_license /* ADDM7:7-bit Address Detection/4-bit Address Detection */ #define USART_CR2_ADDM7 (1 << 4) -/* ADD[3:0]: Addres of the usart node +/* ADD[3:0]: Addres of the usart node #define USART_CR2_ADD_MASK 0xF */ /* --- USART_CR3 values ---------------------------------------------------- */ @@ -263,13 +263,13 @@ LGPL License Terms @ref lgpl_license /* WUS[1:0]: Wakeup from Stop mode interrupt flag selectio */ #define USART_CR3_WUS_ON (0x0 << 20) -// RESERVE #define USART_CR3_WUS (0x1 << 20) +/* RESERVE #define USART_CR3_WUS (0x1 << 20) */ #define USART_CR3_WUS_START_BIT (0x2 << 20) #define USART_CR3_WUS_RXNE (0x3 << 20) /* SCARCNT[2:0]: Smartcard auto-retry count */ #define USART_CR3_SCARCNT_OFF (0x0 << 17) -// 0x1 to 0x7: number of automatic retransmission attempts +/* 0x1 to 0x7: number of automatic retransmission attempts */ /* DEP: Driver enable polarity selection */ #define USART_CR3_DEP (1 << 15) @@ -345,7 +345,7 @@ LGPL License Terms @ref lgpl_license /* --- USART_RTOR values --------------------------------------------------- */ -//Preguntar +/* XXX: Preguntar */ /* BLEN[7:0]: Block Length */ #define USART_RTOR_BLEN1_MASK (0xFF << 24) diff --git a/lib/sam/common/usart.c b/lib/sam/common/usart.c index 94543d21..75b836dd 100644 --- a/lib/sam/common/usart.c +++ b/lib/sam/common/usart.c @@ -106,4 +106,3 @@ void usart_disable_rx_interrupt(uint32_t usart) { USART_IDR(usart) = USART_CSR_RXRDY; } - diff --git a/lib/stm32/f1/spi.c b/lib/stm32/f1/spi.c index f3f36e32..07d6d39b 100644 --- a/lib/stm32/f1/spi.c +++ b/lib/stm32/f1/spi.c @@ -30,4 +30,3 @@ LGPL License Terms @ref lgpl_license #include #include - diff --git a/lib/stm32/f3/adc.c b/lib/stm32/f3/adc.c index ed0ed8f2..c868457a 100644 --- a/lib/stm32/f3/adc.c +++ b/lib/stm32/f3/adc.c @@ -4,44 +4,46 @@ @brief libopencm3 STM32F4xx Analog to Digital Converters -@author @htmlonly © @endhtmlonly 2012 Ken Sarkies +@author @htmlonly © @endhtmlonly 2012 +Ken Sarkies @date 30 August 2012 -This library supports the A/D Converter Control System in the STM32 series -of ARM Cortex Microcontrollers by ST Microelectronics. +This library supports the A/D Converter Control System in the STM32 series of +ARM Cortex Microcontrollers by ST Microelectronics. -Devices can have up to three A/D converters each with their own set of registers. -However all the A/D converters share a common clock which is prescaled from the APB2 -clock by default by a minimum factor of 2 to a maximum of 8. The ADC resolution -can be set to 12, 10, 8 or 6 bits. +Devices can have up to three A/D converters each with their own set of +registers. However all the A/D converters share a common clock which is +prescaled from the APB2 clock by default by a minimum factor of 2 to a maximum +of 8. The ADC resolution can be set to 12, 10, 8 or 6 bits. Each A/D converter has up to 19 channels: @li On ADC1 the analog channels 16 is internally connected to the temperature sensor, channel 17 to VREFINT, and channel 18 to VBATT. @li On ADC2 and ADC3 the analog channels 16 - 18 are not used. -The conversions can occur as a one-off conversion whereby the process stops once -conversion is complete. The conversions can also be continuous wherein a new -conversion starts immediately the previous conversion has ended. +The conversions can occur as a one-off conversion whereby the process stops +once conversion is complete. The conversions can also be continuous wherein a +new conversion starts immediately the previous conversion has ended. Conversion can occur as a single channel conversion or a scan of a group of -channels in either continuous or one-off mode. If more than one channel is converted -in a scan group, DMA must be used to transfer the data as there is only one -result register available. An interrupt can be set to occur at the end of -conversion, which occurs after all channels have been scanned. +channels in either continuous or one-off mode. If more than one channel is +converted in a scan group, DMA must be used to transfer the data as there is +only one result register available. An interrupt can be set to occur at the end +of conversion, which occurs after all channels have been scanned. -A discontinuous mode allows a subgroup of group of a channels to be converted in -bursts of a given length. +A discontinuous mode allows a subgroup of group of a channels to be converted +in bursts of a given length. -Injected conversions allow a second group of channels to be converted separately -from the regular group. An interrupt can be set to occur at the end of -conversion, which occurs after all channels have been scanned. +Injected conversions allow a second group of channels to be converted +separately from the regular group. An interrupt can be set to occur at the end +of conversion, which occurs after all channels have been scanned. @section adc_f4_api_ex Basic ADC Handling API. Example 1: Simple single channel conversion polled. Enable the peripheral clock -and ADC, reset ADC and set the prescaler divider. Set multiple mode to independent. +and ADC, reset ADC and set the prescaler divider. Set multiple mode to +independent. @code gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO1); @@ -84,12 +86,13 @@ LGPL License Terms @ref lgpl_license /**@{*/ -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Off Turn off the ADC to reduce power consumption to a few microamps. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base */ void adc_off(uint32_t adc) @@ -97,14 +100,15 @@ void adc_off(uint32_t adc) ADC_CR(adc) &= ~ADC_CR_ADEN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog for Regular Conversions -The analog watchdog allows the monitoring of an analog signal between two threshold -levels. The thresholds must be preset. Comparison is done before data alignment -takes place, so the thresholds are left-aligned. +The analog watchdog allows the monitoring of an analog signal between two +threshold levels. The thresholds must be preset. Comparison is done before data +alignment takes place, so the thresholds are left-aligned. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base */ void adc_enable_analog_watchdog_regular(uint32_t adc) @@ -112,28 +116,30 @@ void adc_enable_analog_watchdog_regular(uint32_t adc) ADC_CFGR(adc) |= ADC_CFGR_AWD1EN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog for Regular Conversions -The analog watchdog allows the monitoring of an analog signal between two threshold -levels. The thresholds must be preset. Comparison is done before data alignment -takes place, so the thresholds are left-aligned. +The analog watchdog allows the monitoring of an analog signal between two +threshold levels. The thresholds must be preset. Comparison is done before data +alignment takes place, so the thresholds are left-aligned. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base */ void adc_disable_analog_watchdog_regular(uint32_t adc) { ADC_CFGR(adc) &= ~ADC_CFGR_AWD1EN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog for Injected Conversions -The analog watchdog allows the monitoring of an analog signal between two threshold -levels. The thresholds must be preset. Comparison is done before data alignment -takes place, so the thresholds are left-aligned. +The analog watchdog allows the monitoring of an analog signal between two +threshold levels. The thresholds must be preset. Comparison is done before data +alignment takes place, so the thresholds are left-aligned. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base */ void adc_enable_analog_watchdog_injected(uint32_t adc) @@ -141,10 +147,11 @@ void adc_enable_analog_watchdog_injected(uint32_t adc) ADC_CFGR(adc) |= ADC_CFGR_JAWD1EN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable Analog Watchdog for Injected Conversions -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base */ void adc_disable_analog_watchdog_injected(uint32_t adc) @@ -152,32 +159,36 @@ void adc_disable_analog_watchdog_injected(uint32_t adc) ADC_CFGR(adc) &= ~ADC_CFGR_JAWD1EN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Discontinuous Mode for Regular Conversions In this mode the ADC converts, on each trigger, a subgroup of up to 8 of the defined regular channel group. The subgroup is defined by the number of -consecutive channels to be converted. After a subgroup has been converted -the next trigger will start conversion of the immediately following subgroup -of the same length or until the whole group has all been converted. When the -the whole group has been converted, the next trigger will restart conversion -of the subgroup at the beginning of the whole group. +consecutive channels to be converted. After a subgroup has been converted the +next trigger will start conversion of the immediately following subgroup of the +same length or until the whole group has all been converted. When the the whole +group has been converted, the next trigger will restart conversion of the +subgroup at the beginning of the whole group. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@param[in] length Unsigned int8. Number of channels in the group @ref adc_cr1_discnum +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base @param[in] length Unsigned int8. Number of channels in the group +@ref adc_cr1_discnum */ void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length) { - if ( (length-1) > 7 ) return; - ADC_CFGR(adc) |= ADC_CFGR_DISCEN; - ADC_CFGR(adc) |= ((length-1) << ADC_CFGR_DISCNUM_SHIFT); + if ((length-1) > 7) { + return; + } + ADC_CFGR(adc) |= ADC_CFGR_DISCEN; + ADC_CFGR(adc) |= ((length-1) << ADC_CFGR_DISCNUM_SHIFT); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable Discontinuous Mode for Regular Conversions -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base */ void adc_disable_discontinuous_mode_regular(uint32_t adc) @@ -185,14 +196,15 @@ void adc_disable_discontinuous_mode_regular(uint32_t adc) ADC_CFGR(adc) &= ~ADC_CFGR_DISCEN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Discontinuous Mode for Injected Conversions In this mode the ADC converts sequentially one channel of the defined group of injected channels, cycling back to the first channel in the group once the entire group has been converted. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base */ void adc_enable_discontinuous_mode_injected(uint32_t adc) @@ -200,10 +212,11 @@ void adc_enable_discontinuous_mode_injected(uint32_t adc) ADC_CFGR(adc) |= ADC_CFGR_JDISCEN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable Discontinuous Mode for Injected Conversions -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base */ void adc_disable_discontinuous_mode_injected(uint32_t adc) @@ -211,45 +224,49 @@ void adc_disable_discontinuous_mode_injected(uint32_t adc) ADC_CFGR(adc) &= ~ADC_CFGR_JDISCEN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Automatic Injected Conversions The ADC converts a defined injected group of channels immediately after the regular channels have been converted. The external trigger on the injected channels is disabled as required. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base */ void adc_enable_automatic_injected_group_conversion(uint32_t adc) { - adc_disable_external_trigger_injected(adc); + adc_disable_external_trigger_injected(adc); ADC_CFGR(adc) |= ADC_CFGR_JAUTO; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable Automatic Injected Conversions -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base */ void adc_disable_automatic_injected_group_conversion(uint32_t adc) { ADC_CFGR(adc) &= ~ADC_CFGR_JAUTO; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog for All Regular and/or Injected Channels -The analog watchdog allows the monitoring of an analog signal between two threshold -levels. The thresholds must be preset. Comparison is done before data alignment -takes place, so the thresholds are left-aligned. +The analog watchdog allows the monitoring of an analog signal between two +threshold levels. The thresholds must be preset. Comparison is done before data +alignment takes place, so the thresholds are left-aligned. @note The analog watchdog must be enabled for either or both of the regular or injected channels. If neither are enabled, the analog watchdog feature will be disabled. -@ref adc_enable_analog_watchdog_injected, @ref adc_enable_analog_watchdog_regular. +@ref adc_enable_analog_watchdog_injected, @ref +adc_enable_analog_watchdog_regular. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base */ void adc_enable_analog_watchdog_on_all_channels(uint32_t adc) @@ -257,63 +274,73 @@ void adc_enable_analog_watchdog_on_all_channels(uint32_t adc) ADC_CFGR(adc) &= ~ADC_CFGR_AWD1SGL; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog for a Selected Channel -The analog watchdog allows the monitoring of an analog signal between two threshold -levels. The thresholds must be preset. Comparison is done before data alignment -takes place, so the thresholds are left-aligned. +The analog watchdog allows the monitoring of an analog signal between two +threshold levels. The thresholds must be preset. Comparison is done before data +alignment takes place, so the thresholds are left-aligned. @note The analog watchdog must be enabled for either or both of the regular or injected channels. If neither are enabled, the analog watchdog feature will be disabled. If both are enabled, the same channel number is monitored. -@ref adc_enable_analog_watchdog_injected, @ref adc_enable_analog_watchdog_regular. +@ref adc_enable_analog_watchdog_injected, @ref +adc_enable_analog_watchdog_regular. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base @param[in] channel Unsigned int8. ADC channel number @ref adc_watchdog_channel */ -void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t channel) +void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, + uint8_t channel) { uint32_t reg32; - reg32 = (ADC_CFGR(adc) & ~ADC_CFGR_AWD1CH_MASK); /* Clear bits [4:0]. */ + reg32 = (ADC_CFGR(adc) & ~ADC_CFGR_AWD1CH_MASK); /* Clear bit [4:0]. */ if (channel < 18) reg32 |= channel; ADC_CFGR(adc) = reg32; ADC_CFGR(adc) |= ADC_CFGR_AWD1SGL; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set Scan Mode In this mode a conversion consists of a scan of the predefined set of channels, regular and injected, each channel conversion immediately following the previous one. It can use single, continuous or discontinuous mode. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base */ -//void adc_enable_scan_mode(uint32_t adc) -//{ -// ADC_CR1(adc) |= ADC_CR1_SCAN; -//} +/* +void adc_enable_scan_mode(uint32_t adc) +{ + ADC_CR1(adc) |= ADC_CR1_SCAN; +} +*/ -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable Scan Mode -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base */ -//void adc_disable_scan_mode(uint32_t adc) -//{ -// ADC_CR1(adc) &= ~ADC_CR1_SCAN; -//} +/* +void adc_disable_scan_mode(uint32_t adc) +{ + ADC_CR1(adc) &= ~ADC_CR1_SCAN; +} +*/ -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Injected End-Of-Conversion Interrupt -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base */ void adc_enable_eoc_interrupt_injected(uint32_t adc) @@ -321,10 +348,11 @@ void adc_enable_eoc_interrupt_injected(uint32_t adc) ADC_IER(adc) |= ADC_IER_JEOCIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable Injected End-Of-Conversion Interrupt -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base */ void adc_disable_eoc_interrupt_injected(uint32_t adc) @@ -332,10 +360,11 @@ void adc_disable_eoc_interrupt_injected(uint32_t adc) ADC_IER(adc) &= ~ADC_IER_JEOCIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog Interrupt -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base */ void adc_enable_all_awd_interrupt(uint32_t adc) @@ -345,10 +374,11 @@ void adc_enable_all_awd_interrupt(uint32_t adc) ADC_IER(adc) |= ADC_IER_AWD3IE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable Analog Watchdog Interrupt -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base */ void adc_disable_all_awd_interrupt(uint32_t adc) @@ -358,10 +388,11 @@ void adc_disable_all_awd_interrupt(uint32_t adc) ADC_IER(adc) &= ~ADC_IER_AWD3IE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Regular End-Of-Conversion Interrupt -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base */ void adc_enable_eoc_interrupt(uint32_t adc) @@ -369,10 +400,11 @@ void adc_enable_eoc_interrupt(uint32_t adc) ADC_IER(adc) |= ADC_IER_EOCIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable Regular End-Of-Conversion Interrupt -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base */ void adc_disable_eoc_interrupt(uint32_t adc) @@ -380,13 +412,14 @@ void adc_disable_eoc_interrupt(uint32_t adc) ADC_IER(adc) &= ~ADC_IER_EOCIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Software Triggered Conversion on Regular Channels This starts conversion on a set of defined regular channels. It is cleared by hardware once conversion starts. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base */ void adc_start_conversion_regular(uint32_t adc) @@ -398,13 +431,14 @@ void adc_start_conversion_regular(uint32_t adc) while (ADC_CR(adc) & ADC_CR_ADSTART); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Software Triggered Conversion on Injected Channels This starts conversion on a set of defined injected channels. It is cleared by hardware once conversion starts. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base */ void adc_start_conversion_injected(uint32_t adc) @@ -416,10 +450,11 @@ void adc_start_conversion_injected(uint32_t adc) while (ADC_CR(adc) & ADC_CR_JADSTART); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set the Data as Left Aligned -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base */ void adc_set_left_aligned(uint32_t adc) @@ -427,10 +462,11 @@ void adc_set_left_aligned(uint32_t adc) ADC_CFGR(adc) |= ADC_CFGR_ALIGN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set the Data as Right Aligned -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base */ void adc_set_right_aligned(uint32_t adc) @@ -438,7 +474,7 @@ void adc_set_right_aligned(uint32_t adc) ADC_CFGR(adc) &= ~ADC_CFGR_ALIGN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable DMA Transfers @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @@ -446,10 +482,10 @@ void adc_set_right_aligned(uint32_t adc) void adc_enable_dma(uint32_t adc) { - ADC_CFGR(adc) |= ADC_CFGR_DMAEN; + ADC_CFGR(adc) |= ADC_CFGR_DMAEN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable DMA Transfers @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @@ -457,10 +493,10 @@ void adc_enable_dma(uint32_t adc) void adc_disable_dma(uint32_t adc) { - ADC_CFGR(adc) &= ~ADC_CFGR_DMAEN; + ADC_CFGR(adc) &= ~ADC_CFGR_DMAEN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Continuous Conversion Mode In this mode the ADC starts a new conversion of a single channel or a channel @@ -474,7 +510,7 @@ void adc_set_continuous_conversion_mode(uint32_t adc) ADC_CFGR(adc) |= ADC_CFGR_CONT; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Single Conversion Mode In this mode the ADC performs a conversion of one channel or a channel group @@ -488,13 +524,14 @@ void adc_set_single_conversion_mode(uint32_t adc) ADC_CFGR(adc) &= ~ADC_CFGR_CONT; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set the Sample Time for a Single Channel The sampling time can be selected in ADC clock cycles from 1.5 to 239.5. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@param[in] channel Unsigned int8. ADC Channel integer 0..18 or from @ref adc_channel +@param[in] channel Unsigned int8. ADC Channel integer 0..18 or from @ref +adc_channel @param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg */ @@ -515,13 +552,14 @@ void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time) } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set the Sample Time for All Channels -The sampling time can be selected in ADC clock cycles from 1.5 to 239.5, same for -all channels. +The sampling time can be selected in ADC clock cycles from 1.5 to 239.5, same +for all channels. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base @param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg */ @@ -539,10 +577,11 @@ void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time) ADC_SMPR1(adc) = reg32; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set Analog Watchdog Upper Threshold -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base @param[in] threshold Unsigned int8. Upper threshold value */ @@ -550,14 +589,14 @@ void adc_set_watchdog_high_threshold(uint32_t adc, uint8_t threshold) { uint32_t reg32 = 0; - reg32 |= (threshold << 16) ; + reg32 |= (threshold << 16); reg32 &= ~0xff00ffff; /* Clear all bits above 8. */ ADC_TR1(adc) = reg32; ADC_TR2(adc) = reg32; ADC_TR3(adc) = reg32; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set Analog Watchdog Lower Threshold @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @@ -575,12 +614,12 @@ void adc_set_watchdog_low_threshold(uint32_t adc, uint8_t threshold) ADC_TR3(adc) = reg32; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set a Regular Channel Conversion Sequence Define a sequence of channels to be converted as a regular group with a length -from 1 to 16 channels. If this is called during conversion, the current conversion -is reset and conversion begins again with the newly defined group. +from 1 to 16 channels. If this is called during conversion, the current +conversion is reset and conversion begins again with the newly defined group. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @param[in] length Unsigned int8. Number of channels in the group. @@ -593,33 +632,38 @@ void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[]) uint8_t i = 0; /* Maximum sequence length is 16 channels. */ - if (length > 16) + if (length > 16) { return; + } for (i = 1; i <= length; i++) { - if (i <= 4) + if (i <= 4) { reg32_1 |= (channel[i - 1] << (i * 6)); - if ((i > 4) & (i <= 9)) + } + if ((i > 4) & (i <= 9)) { reg32_2 |= (channel[i - 1] << ((i - 4 - 1) * 6)); - if ((i > 9) & (i <= 14)) + } + if ((i > 9) & (i <= 14)) { reg32_3 |= (channel[i - 1] << ((i - 9 - 1) * 6)); - if ((i > 14) & (i <= 16)) + } + if ((i > 14) & (i <= 16)) { reg32_4 |= (channel[i - 1] << ((i - 14 - 1) * 6)); + } } - reg32_1 |= ((length -1) << ADC_SQR1_L_LSB); + reg32_1 |= ((length - 1) << ADC_SQR1_L_LSB); ADC_SQR1(adc) = reg32_1; ADC_SQR2(adc) = reg32_2; ADC_SQR3(adc) = reg32_3; - ADC_SQR4(adc) = reg32_4; + ADC_SQR4(adc) = reg32_4; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set an Injected Channel Conversion Sequence -Defines a sequence of channels to be converted as an injected group with a length -from 1 to 4 channels. If this is called during conversion, the current conversion -is reset and conversion begins again with the newly defined group. +Defines a sequence of channels to be converted as an injected group with a +length from 1 to 4 channels. If this is called during conversion, the current +conversion is reset and conversion begins again with the newly defined group. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @param[in] length Unsigned int8. Number of channels in the group. @@ -632,18 +676,20 @@ void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[]) uint8_t i = 0; /* Maximum sequence length is 4 channels. */ - if ((length-1) > 3) + if ((length-1) > 3) { return; + } - for (i = 1; i <= length; i++) + for (i = 1; i <= length; i++) { reg32 |= (channel[4 - i] << ((4 - i) * 5)); + } reg32 |= ((length - 1) << ADC_JSQR_JL_LSB); ADC_JSQR(adc) = reg32; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Read the End-of-Conversion Flag This flag is set after all channels of a regular or injected group have been @@ -655,10 +701,10 @@ converted. bool adc_eoc(uint32_t adc) { - return ((ADC_ISR(adc) & ADC_ISR_EOC) != 0); + return ((ADC_ISR(adc) & ADC_ISR_EOC) != 0); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Read the End-of-Conversion Flag for Injected Conversion This flag is set after all channels of an injected group have been converted. @@ -669,10 +715,10 @@ This flag is set after all channels of an injected group have been converted. bool adc_eoc_injected(uint32_t adc) { - return ((ADC_ISR(adc) & ADC_ISR_JEOC) != 0); + return ((ADC_ISR(adc) & ADC_ISR_JEOC) != 0); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Read from the Regular Conversion Result Register The result read back is 12 bits, right or left aligned within the first 16 bits. @@ -685,41 +731,43 @@ an appropriate dual mode has been set @see adc_set_dual_mode. uint32_t adc_read_regular(uint32_t adc) { - return ADC_DR(adc); + return ADC_DR(adc); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Read from an Injected Conversion Result Register -The result read back from the selected injected result register (one of four) is -12 bits, right or left aligned within the first 16 bits. The result can have a -negative value if the injected channel offset has been set @see adc_set_injected_offset. +The result read back from the selected injected result register (one of four) +is 12 bits, right or left aligned within the first 16 bits. The result can have +a negative value if the injected channel offset has been set @see +adc_set_injected_offset. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base @param[in] reg Unsigned int8. Register number (1 ... 4). @returns Unsigned int32 conversion result. */ uint32_t adc_read_injected(uint32_t adc, uint8_t reg) { - switch (reg) { - case 1: - return ADC_JDR1(adc); - case 2: - return ADC_JDR2(adc); - case 3: - return ADC_JDR3(adc); - case 4: - return ADC_JDR4(adc); - } + switch (reg) { + case 1: + return ADC_JDR1(adc); + case 2: + return ADC_JDR2(adc); + case 3: + return ADC_JDR3(adc); + case 4: + return ADC_JDR4(adc); + } return 0; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set the Injected Channel Data Offset -This value is subtracted from the injected channel results after conversion -is complete, and can result in negative results. A separate value can be specified +This value is subtracted from the injected channel results after conversion is +complete, and can result in negative results. A separate value can be specified for each injected data register. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @@ -729,34 +777,35 @@ for each injected data register. void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset) { - switch (reg) { - case 1: - ADC_OFR1(adc) |= ADC_OFR1_OFFSET1_EN; - ADC_OFR1(adc) |= offset; - break; - case 2: - ADC_OFR2(adc) |= ADC_OFR2_OFFSET2_EN; - ADC_OFR2(adc) |= offset; - break; - case 3: - ADC_OFR3(adc) |= ADC_OFR3_OFFSET3_EN; - ADC_OFR3(adc) |= offset; - break; - case 4: - ADC_OFR4(adc) |= ADC_OFR4_OFFSET4_EN; - ADC_OFR4(adc) |= offset; - break; - } + switch (reg) { + case 1: + ADC_OFR1(adc) |= ADC_OFR1_OFFSET1_EN; + ADC_OFR1(adc) |= offset; + break; + case 2: + ADC_OFR2(adc) |= ADC_OFR2_OFFSET2_EN; + ADC_OFR2(adc) |= offset; + break; + case 3: + ADC_OFR3(adc) |= ADC_OFR3_OFFSET3_EN; + ADC_OFR3(adc) |= offset; + break; + case 4: + ADC_OFR4(adc) |= ADC_OFR4_OFFSET4_EN; + ADC_OFR4(adc) |= offset; + break; + } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Power On If the ADC is in power-down mode then it is powered up. The application needs to wait a time of about 3 microseconds for stabilization before using the ADC. If the ADC is already on this function call will have no effect. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base */ void adc_power_on(uint32_t adc) @@ -765,12 +814,13 @@ void adc_power_on(uint32_t adc) } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set Clock Prescale The ADC clock taken from the APB2 clock can be scaled down by 2, 4, 6 or 8. -@param[in] prescale Unsigned int32. Prescale value for ADC Clock @ref adc_ccr_adcpre +@param[in] prescale Unsigned int32. Prescale value for ADC Clock @ref +adc_ccr_adcpre */ void adc_set_clk_prescale(uint32_t prescale) @@ -779,7 +829,7 @@ void adc_set_clk_prescale(uint32_t prescale) ADC_CCR = reg32; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set Dual/Triple Mode The multiple mode uses ADC1 as master, ADC2 and optionally ADC3 in a slave @@ -787,7 +837,8 @@ arrangement. This setting is applied to ADC1 only. The various modes possible are described in the reference manual. -@param[in] mode Unsigned int32. Multiple mode selection from @ref adc_multi_mode +@param[in] mode Unsigned int32. Multiple mode selection from @ref +adc_multi_mode */ void adc_set_multi_mode(uint32_t mode) @@ -795,19 +846,22 @@ void adc_set_multi_mode(uint32_t mode) ADC_CCR |= mode; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable an External Trigger for Regular Channels -This enables an external trigger for set of defined regular channels, and sets the -polarity of the trigger event: rising or falling edge or both. Note that if the -trigger polarity is zero, triggering is disabled. +This enables an external trigger for set of defined regular channels, and sets +the polarity of the trigger event: rising or falling edge or both. Note that if +the trigger polarity is zero, triggering is disabled. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base @param[in] trigger Unsigned int32. Trigger identifier @ref adc_trigger_regular -@param[in] polarity Unsigned int32. Trigger polarity @ref adc_trigger_polarity_regular +@param[in] polarity Unsigned int32. Trigger polarity @ref +adc_trigger_polarity_regular */ -void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, uint32_t polarity) +void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, + uint32_t polarity) { uint32_t reg32 = ADC_CFGR(adc); @@ -816,7 +870,7 @@ void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, uint32_ ADC_CFGR(adc) = reg32; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable an External Trigger for Regular Channels @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @@ -827,18 +881,20 @@ void adc_disable_external_trigger_regular(uint32_t adc) ADC_CFGR(adc) &= ~ADC_CFGR_EXTEN_MASK; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable an External Trigger for Injected Channels -This enables an external trigger for set of defined injected channels, and sets the -polarity of the trigger event: rising or falling edge or both. +This enables an external trigger for set of defined injected channels, and sets +the polarity of the trigger event: rising or falling edge or both. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @param[in] trigger Unsigned int8. Trigger identifier @ref adc_trigger_injected -@param[in] polarity Unsigned int32. Trigger polarity @ref adc_trigger_polarity_injected +@param[in] polarity Unsigned int32. Trigger polarity @ref +adc_trigger_polarity_injected */ -void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, uint32_t polarity) +void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, + uint32_t polarity) { uint32_t reg32 = ADC_JSQR(adc); @@ -847,10 +903,11 @@ void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, uint32 ADC_JSQR(adc) = reg32; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable an External Trigger for Injected Channels -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base */ void adc_disable_external_trigger_injected(uint32_t adc) @@ -858,13 +915,14 @@ void adc_disable_external_trigger_injected(uint32_t adc) ADC_JSQR(adc) &= ~ADC_JSQR_JEXTEN_MASK; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set Resolution -ADC Resolution can be reduced from 12 bits to 10, 8 or 6 bits for a corresponding -reduction in conversion time (resolution + 3 ADC clock cycles). +ADC Resolution can be reduced from 12 bits to 10, 8 or 6 bits for a +corresponding reduction in conversion time (resolution + 3 ADC clock cycles). -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base @param[in] resolution Unsigned int8. Resolution value @ref adc_cr1_res */ @@ -877,14 +935,15 @@ void adc_set_resolution(uint32_t adc, uint16_t resolution) ADC_CFGR(adc) = reg32; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable the Overrun Interrupt The overrun interrupt is generated when data is not read from a result register before the next conversion is written. If DMA is enabled, all transfers are terminated and any conversion sequence is aborted. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base */ void adc_enable_overrun_interrupt(uint32_t adc) @@ -892,10 +951,11 @@ void adc_enable_overrun_interrupt(uint32_t adc) ADC_IER(adc) |= ADC_IER_OVRIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable the Overrun Interrupt -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base */ void adc_disable_overrun_interrupt(uint32_t adc) @@ -903,23 +963,24 @@ void adc_disable_overrun_interrupt(uint32_t adc) ADC_IER(adc) &= ~ADC_IER_OVRIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Read the Overrun Flag -The overrun flag is set when data is not read from a result register before the next -conversion is written. If DMA is enabled, all transfers are terminated and any -conversion sequence is aborted. +The overrun flag is set when data is not read from a result register before the +next conversion is written. If DMA is enabled, all transfers are terminated and +any conversion sequence is aborted. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base @returns Unsigned int32 conversion result. */ bool adc_get_overrun_flag(uint32_t adc) { - return (ADC_ISR(adc) & ADC_ISR_OVR); + return ADC_ISR(adc) & ADC_ISR_OVR; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Clear Overrun Flags The overrun flag is cleared. Note that if an overrun occurs, DMA is terminated. @@ -936,7 +997,7 @@ void adc_clear_overrun_flag(uint32_t adc) ADC_ISR(adc) &= ~ADC_ISR_OVR; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable an EOC for Each Conversion The EOC is set after each conversion in a sequence rather than at the end of the @@ -950,13 +1011,14 @@ void adc_eoc_after_each(uint32_t adc) ADC_ISR(adc) |= ADC_ISR_EOS; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable the EOC for Each Conversion -The EOC is set at the end of each sequence rather than after each conversion in the -sequence. Overrun detection is enabled always. +The EOC is set at the end of each sequence rather than after each conversion in +the sequence. Overrun detection is enabled always. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base */ void adc_eoc_after_group(uint32_t adc) @@ -964,21 +1026,24 @@ void adc_eoc_after_group(uint32_t adc) ADC_ISR(adc) &= ~ADC_ISR_EOS; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set DMA to Continue -This must be set to allow DMA to continue to operate after the last conversion in -the DMA sequence. This allows DMA to be used in continuous circular mode. +This must be set to allow DMA to continue to operate after the last conversion +in the DMA sequence. This allows DMA to be used in continuous circular mode. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base */ -/*void adc_set_dma_continue(uint32_t adc) +/* +void adc_set_dma_continue(uint32_t adc) { ADC_CR2(adc) |= ADC_CR2_DDS; -}*/ +} +*/ -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set DMA to Terminate This must be set to allow DMA to terminate after the last conversion in the DMA @@ -987,11 +1052,14 @@ sequence. This can avoid overrun errors. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ -/*void adc_set_dma_terminate(uint32_t adc) +/* +void adc_set_dma_terminate(uint32_t adc) { ADC_CR2(adc) &= ~ADC_CR2_DDS; -}*/ -/*-----------------------------------------------------------------------------*/ +} +*/ + +/*---------------------------------------------------------------------------*/ /** @brief ADC Read the Analog Watchdog Flag This flag is set when the converted voltage crosses the high or low thresholds. @@ -1002,16 +1070,19 @@ This flag is set when the converted voltage crosses the high or low thresholds. bool adc_awd(uint32_t adc) { - return ((ADC_ISR(adc) & ADC_ISR_AWD1) && (ADC_ISR(adc) & ADC_ISR_AWD2) && (ADC_ISR(adc) & ADC_ISR_AWD3)); + return (ADC_ISR(adc) & ADC_ISR_AWD1) && + (ADC_ISR(adc) & ADC_ISR_AWD2) && + (ADC_ISR(adc) & ADC_ISR_AWD3); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable The Temperature Sensor This enables both the sensor and the reference voltage measurements on channels 16 and 17. These are only available on ADC1 channel 16 and 17 respectively. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base */ void adc_enable_temperature_sensor() @@ -1019,7 +1090,7 @@ void adc_enable_temperature_sensor() ADC_CCR |= ADC_CCR_TSEN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable The Temperature Sensor Disabling this will reduce power consumption from the sensor and the reference @@ -1033,7 +1104,7 @@ void adc_disable_temperature_sensor() ADC_CCR &= ~ADC_CCR_TSEN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /**@}*/ diff --git a/lib/stm32/f3/gpio.c b/lib/stm32/f3/gpio.c index bd8f76cf..88be2496 100644 --- a/lib/stm32/f3/gpio.c +++ b/lib/stm32/f3/gpio.c @@ -21,7 +21,8 @@ #include -void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down, uint16_t gpios) +void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down, + uint16_t gpios) { uint16_t i; uint32_t moder, pupd; @@ -34,8 +35,9 @@ void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down, uint pupd = GPIO_PUPDR(gpioport); for (i = 0; i < 16; i++) { - if (!((1 << i) & gpios)) + if (!((1 << i) & gpios)) { continue; + } moder &= ~GPIO_MODE_MASK(i); moder |= GPIO_MODE(i, mode); @@ -48,21 +50,24 @@ void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down, uint GPIO_PUPDR(gpioport) = pupd; } -void gpio_set_output_options(uint32_t gpioport, uint8_t otype, uint8_t speed, uint16_t gpios) +void gpio_set_output_options(uint32_t gpioport, uint8_t otype, uint8_t speed, + uint16_t gpios) { uint16_t i; uint32_t ospeedr; - if (otype == 0x1) + if (otype == 0x1) { GPIO_OTYPER(gpioport) |= gpios; - else + } else { GPIO_OTYPER(gpioport) &= ~gpios; + } ospeedr = GPIO_OSPEEDR(gpioport); for (i = 0; i < 16; i++) { - if (!((1 << i) & gpios)) + if (!((1 << i) & gpios)) { continue; + } ospeedr &= ~GPIO_OSPEED_MASK(i); ospeedr |= GPIO_OSPEED(i, speed); } @@ -79,15 +84,17 @@ void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint16_t gpios) afrh = GPIO_AFRH(gpioport); for (i = 0; i < 8; i++) { - if (!((1 << i) & gpios)) + if (!((1 << i) & gpios)) { continue; + } afrl &= ~GPIO_AFR_MASK(i); afrl |= GPIO_AFR(i, alt_func_num); } for (i = 8; i < 16; i++) { - if (!((1 << i) & gpios)) + if (!((1 << i) & gpios)) { continue; + } afrl &= ~GPIO_AFR_MASK(i - 8); afrh |= GPIO_AFR(i - 8, alt_func_num); } @@ -137,8 +144,11 @@ void gpio_port_config_lock(uint32_t gpioport, uint16_t gpios) reg32 = GPIO_LCKR(gpioport); /* Read LCKK. */ reg32 = GPIO_LCKR(gpioport); /* Read LCKK again. */ - /* Tell the compiler the variable is actually used. It will get optimized out anyways. */ - reg32 = reg32; + /* + * Tell the compiler the variable is actually used. + * It will get optimized out anyways. + */ + reg32 = reg32; /* If (reg32 & GPIO_LCKK) is true, the lock is now active. */ } diff --git a/lib/stm32/f3/i2c.c b/lib/stm32/f3/i2c.c index c202f8fa..e0fc54ad 100644 --- a/lib/stm32/f3/i2c.c +++ b/lib/stm32/f3/i2c.c @@ -107,7 +107,7 @@ mode, or simply release the bus if in Slave mode. void i2c_send_stop(uint32_t i2c) { - I2C_CR2(i2c) |= I2C_CR2_STOP; + I2C_CR2(i2c) |= I2C_CR2_STOP; } /*---------------------------------------------------------------------------*/ @@ -173,166 +173,174 @@ void i2c_send_data(uint32_t i2c, uint8_t data) */ uint8_t i2c_get_data(uint32_t i2c) { - return(I2C_RXDR(i2c) & 0xff); + return I2C_RXDR(i2c) & 0xff; } void i2c_enable_analog_filter(uint32_t i2c) { - I2C_CR1(i2c) &= ~I2C_CR1_ANFOFF; + I2C_CR1(i2c) &= ~I2C_CR1_ANFOFF; } void i2c_disable_analog_filter(uint32_t i2c) { - I2C_CR1(i2c) |= I2C_CR1_ANFOFF; + I2C_CR1(i2c) |= I2C_CR1_ANFOFF; } void i2c_set_digital_filter(uint32_t i2c, uint8_t dnf_setting) { - I2C_CR1(i2c) = (I2C_CR1(i2c) & ~I2C_CR1_DNF_MASK) | dnf_setting; + I2C_CR1(i2c) = (I2C_CR1(i2c) & ~I2C_CR1_DNF_MASK) | dnf_setting; } /* t_presc= (presc+1)*t_i2cclk */ void i2c_set_prescaler(uint32_t i2c, uint8_t presc) { - I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_PRESC_MASK) | (presc << I2C_TIMINGR_PRESC_SHIFT); + I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_PRESC_MASK) | + (presc << I2C_TIMINGR_PRESC_SHIFT); } void i2c_set_data_setup_time(uint32_t i2c, uint8_t s_time) { - I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SCLDEL_MASK) | (s_time << I2C_TIMINGR_SCLDEL_SHIFT); + I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SCLDEL_MASK) | + (s_time << I2C_TIMINGR_SCLDEL_SHIFT); } void i2c_set_data_hold_time(uint32_t i2c, uint8_t h_time) { - I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SDADEL_MASK) | (h_time << I2C_TIMINGR_SDADEL_SHIFT); + I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SDADEL_MASK) | + (h_time << I2C_TIMINGR_SDADEL_SHIFT); } void i2c_set_scl_high_period(uint32_t i2c, uint8_t period) { - I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SCLH_MASK) | (period << I2C_TIMINGR_SCLH_SHIFT); + I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SCLH_MASK) | + (period << I2C_TIMINGR_SCLH_SHIFT); } void i2c_set_scl_low_period(uint32_t i2c, uint8_t period) { - I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SCLL_MASK) | (period << I2C_TIMINGR_SCLL_SHIFT); + I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SCLL_MASK) | + (period << I2C_TIMINGR_SCLL_SHIFT); } void i2c_enable_stretching(uint32_t i2c) { - I2C_CR1(i2c) &= ~I2C_CR1_NOSTRETCH; + I2C_CR1(i2c) &= ~I2C_CR1_NOSTRETCH; } void i2c_disable_stretching(uint32_t i2c) { - I2C_CR1(i2c) |= I2C_CR1_NOSTRETCH; + I2C_CR1(i2c) |= I2C_CR1_NOSTRETCH; } void i2c_100khz_i2cclk8mhz(uint32_t i2c) { - i2c_set_prescaler(i2c, 1); - i2c_set_scl_low_period(i2c, 0x13); - i2c_set_scl_high_period(i2c, 0xF); - i2c_set_data_hold_time(i2c, 0x2); - i2c_set_data_setup_time(i2c, 0x4); + i2c_set_prescaler(i2c, 1); + i2c_set_scl_low_period(i2c, 0x13); + i2c_set_scl_high_period(i2c, 0xF); + i2c_set_data_hold_time(i2c, 0x2); + i2c_set_data_setup_time(i2c, 0x4); } void i2c_set_7bit_addr_mode(uint32_t i2c) { - I2C_CR2(i2c) &= ~I2C_CR2_ADD10; + I2C_CR2(i2c) &= ~I2C_CR2_ADD10; } void i2c_set_10bit_addr_mode(uint32_t i2c) { - I2C_CR2(i2c) |= I2C_CR2_ADD10; + I2C_CR2(i2c) |= I2C_CR2_ADD10; } void i2c_set_7bit_address(uint32_t i2c, uint8_t addr) { - I2C_CR2(i2c) = (I2C_CR2(i2c) & ~I2C_CR2_SADD_7BIT_MASK) | ((addr & 0x7F) << I2C_CR2_SADD_7BIT_SHIFT); + I2C_CR2(i2c) = (I2C_CR2(i2c) & ~I2C_CR2_SADD_7BIT_MASK) | + ((addr & 0x7F) << I2C_CR2_SADD_7BIT_SHIFT); } void i2c_set_10bit_address(uint32_t i2c, uint16_t addr) { - I2C_CR2(i2c) = (I2C_CR2(i2c) & ~I2C_CR2_SADD_10BIT_MASK) | ((addr & 0x3FF) << I2C_CR2_SADD_10BIT_SHIFT); + I2C_CR2(i2c) = (I2C_CR2(i2c) & ~I2C_CR2_SADD_10BIT_MASK) | + ((addr & 0x3FF) << I2C_CR2_SADD_10BIT_SHIFT); } void i2c_set_write_transfer_dir(uint32_t i2c) { - I2C_CR2(i2c) &= ~I2C_CR2_RD_WRN; + I2C_CR2(i2c) &= ~I2C_CR2_RD_WRN; } void i2c_set_read_transfer_dir(uint32_t i2c) { - I2C_CR2(i2c) |= I2C_CR2_RD_WRN; + I2C_CR2(i2c) |= I2C_CR2_RD_WRN; } void i2c_set_bytes_to_transfer(uint32_t i2c, uint32_t n_bytes) { - I2C_CR2(i2c) = (I2C_CR2(i2c) & ~I2C_CR2_NBYTES_MASK) | (n_bytes << I2C_CR2_NBYTES_SHIFT); + I2C_CR2(i2c) = (I2C_CR2(i2c) & ~I2C_CR2_NBYTES_MASK) | + (n_bytes << I2C_CR2_NBYTES_SHIFT); } uint8_t i2c_is_start(uint32_t i2c) { - if ((I2C_CR2(i2c) & I2C_CR2_START) != 0) { - return(1); - } else { - return(0); - } + if ((I2C_CR2(i2c) & I2C_CR2_START) != 0) { + return 1; + } + + return 0; } void i2c_enable_autoend(uint32_t i2c) { - I2C_CR2(i2c) |= I2C_CR2_AUTOEND; + I2C_CR2(i2c) |= I2C_CR2_AUTOEND; } void i2c_disable_autoend(uint32_t i2c) { - I2C_CR2(i2c) &= ~I2C_CR2_AUTOEND; + I2C_CR2(i2c) &= ~I2C_CR2_AUTOEND; } uint8_t i2c_nack(uint32_t i2c) { - if ((I2C_ISR(i2c) & I2C_ISR_NACKF) != 0) { - return(1); - } else { - return(0); - } + if ((I2C_ISR(i2c) & I2C_ISR_NACKF) != 0) { + return 1; + } + + return 0; } uint8_t i2c_busy(uint32_t i2c) { - if ((I2C_ISR(i2c) & I2C_ISR_BUSY) != 0) { - return(1); - } else { - return(0); - } + if ((I2C_ISR(i2c) & I2C_ISR_BUSY) != 0) { + return 1; + } + + return 0; } uint8_t i2c_transmit_int_status(uint32_t i2c) { - if ((I2C_ISR(i2c) & I2C_ISR_TXIS) != 0) { - return(1); - } else { - return(0); - } + if ((I2C_ISR(i2c) & I2C_ISR_TXIS) != 0) { + return 1; + } + + return 0; } uint8_t i2c_transfer_complete(uint32_t i2c) { - if ((I2C_ISR(i2c) & I2C_ISR_TC) != 0) { - return(1); - } else { - return(0); - } + if ((I2C_ISR(i2c) & I2C_ISR_TC) != 0) { + return 1; + } + + return 0; } uint8_t i2c_received_data(uint32_t i2c) { - if ((I2C_ISR(i2c) & I2C_ISR_RXNE) != 0) { - return(1); - } else { - return(0); - } + if ((I2C_ISR(i2c) & I2C_ISR_RXNE) != 0) { + return 1; + } + + return 0; } @@ -398,78 +406,79 @@ void i2c_disable_txdma(uint32_t i2c) I2C_CR1(i2c) &= ~I2C_CR1_TXDMAEN; } -void write_i2c(uint32_t i2c, uint8_t i2c_addr, uint8_t reg, uint8_t size, uint8_t *data) { - int wait; - int i; - while (i2c_busy(i2c) == 1) {} - while (i2c_is_start(i2c) == 1) {} - /*Setting transfer properties*/ - i2c_set_bytes_to_transfer(i2c, size+1); - i2c_set_7bit_address(i2c, (i2c_addr & 0x7F)); - i2c_set_write_transfer_dir(i2c); - i2c_enable_autoend(i2c); - /*start transfer*/ - i2c_send_start(i2c); - - wait=true; - while (wait) { - if (i2c_transmit_int_status(i2c)) { - wait=false; - } - while (i2c_nack(i2c)){} - } - i2c_send_data(i2c, reg); - for (i=0; i> 2); + return (RCC_CFGR & 0x000c) >> 2; } void rcc_clock_setup_hsi(const clock_scale_t *clock) { - /* Enable internal high-speed oscillator. */ - rcc_osc_on(HSI); - rcc_wait_for_osc_ready(HSI); - /* Select HSI as SYSCLK source. */ - rcc_set_sysclk_source(RCC_CFGR_SW_HSI); //se cayo - rcc_wait_for_sysclk_status(HSI); + /* Enable internal high-speed oscillator. */ + rcc_osc_on(HSI); + rcc_wait_for_osc_ready(HSI); + /* Select HSI as SYSCLK source. */ + rcc_set_sysclk_source(RCC_CFGR_SW_HSI); /* XXX: se cayo */ + rcc_wait_for_sysclk_status(HSI); - rcc_osc_off(PLL); - rcc_wait_for_osc_not_ready(PLL); - rcc_set_pll_source(clock->pllsrc); - rcc_set_main_pll_hsi(clock->pll); - /* Enable PLL oscillator and wait for it to stabilize. */ - rcc_osc_on(PLL); - rcc_wait_for_osc_ready(PLL); - /* - * Set prescalers for AHB, ADC, ABP1, ABP2. - * Do this before touching the PLL (TODO: why?). - */ - rcc_set_hpre(clock->hpre); - rcc_set_ppre2(clock->ppre2); - rcc_set_ppre1(clock->ppre1); - /* Configure flash settings. */ - flash_set_ws(clock->flash_config); - /* Select PLL as SYSCLK source. */ - rcc_set_sysclk_source(RCC_CFGR_SW_PLL); //se cayo - /* Wait for PLL clock to be selected. */ - rcc_wait_for_sysclk_status(PLL); + rcc_osc_off(PLL); + rcc_wait_for_osc_not_ready(PLL); + rcc_set_pll_source(clock->pllsrc); + rcc_set_main_pll_hsi(clock->pll); + /* Enable PLL oscillator and wait for it to stabilize. */ + rcc_osc_on(PLL); + rcc_wait_for_osc_ready(PLL); + /* + * Set prescalers for AHB, ADC, ABP1, ABP2. + * Do this before touching the PLL (TODO: why?). + */ + rcc_set_hpre(clock->hpre); + rcc_set_ppre2(clock->ppre2); + rcc_set_ppre1(clock->ppre1); + /* Configure flash settings. */ + flash_set_ws(clock->flash_config); + /* Select PLL as SYSCLK source. */ + rcc_set_sysclk_source(RCC_CFGR_SW_PLL); /* XXX: se cayo */ + /* Wait for PLL clock to be selected. */ + rcc_wait_for_sysclk_status(PLL); - /* Set the peripheral clock frequencies used. */ - rcc_ppre1_frequency = clock->apb1_frequency; - rcc_ppre2_frequency = clock->apb2_frequency; + /* Set the peripheral clock frequencies used. */ + rcc_ppre1_frequency = clock->apb1_frequency; + rcc_ppre2_frequency = clock->apb2_frequency; } @@ -434,35 +434,37 @@ void rcc_backupdomain_reset(void) RCC_BDCR &= ~RCC_BDCR_BDRST; } -void rcc_set_i2c_clock_hsi(uint32_t i2c) { - if (i2c==I2C1) { - RCC_CFGR3 &= ~RCC_CFGR3_I2C1SW; - } - if (i2c==I2C2) { - RCC_CFGR3 &= ~RCC_CFGR3_I2C2SW; - } +void rcc_set_i2c_clock_hsi(uint32_t i2c) +{ + if (i2c == I2C1) { + RCC_CFGR3 &= ~RCC_CFGR3_I2C1SW; + } + if (i2c == I2C2) { + RCC_CFGR3 &= ~RCC_CFGR3_I2C2SW; + } } -void rcc_set_i2c_clock_sysclk(uint32_t i2c) { - if (i2c==I2C1) { - RCC_CFGR3 |= RCC_CFGR3_I2C1SW; - } - if (i2c==I2C2) { - RCC_CFGR3 |= RCC_CFGR3_I2C2SW; - } +void rcc_set_i2c_clock_sysclk(uint32_t i2c) +{ + if (i2c == I2C1) { + RCC_CFGR3 |= RCC_CFGR3_I2C1SW; + } + if (i2c == I2C2) { + RCC_CFGR3 |= RCC_CFGR3_I2C2SW; + } } uint32_t rcc_get_i2c_clocks(void) { - return(RCC_CFGR3 & (RCC_CFGR3_I2C1SW | RCC_CFGR3_I2C2SW)); + return RCC_CFGR3 & (RCC_CFGR3_I2C1SW | RCC_CFGR3_I2C2SW); } void rcc_usb_prescale_1_5(void) { - RCC_CFGR &= ~RCC_CFGR_USBPRES; + RCC_CFGR &= ~RCC_CFGR_USBPRES; } void rcc_usb_prescale_1(void) { - RCC_CFGR |= RCC_CFGR_USBPRES; + RCC_CFGR |= RCC_CFGR_USBPRES; } diff --git a/lib/stm32/f3/spi.c b/lib/stm32/f3/spi.c index 8207592b..67b041f5 100644 --- a/lib/stm32/f3/spi.c +++ b/lib/stm32/f3/spi.c @@ -57,4 +57,4 @@ void spi_fifo_reception_threshold_16bit(uint32_t spi) void spi_i2s_mode_spi_mode(uint32_t spi) { SPI_I2SCFGR(spi) &= ~SPI_I2SCFGR_I2SMOD; -} \ No newline at end of file +} diff --git a/lib/stm32/f3/usart.c b/lib/stm32/f3/usart.c index 5145cc4c..be474542 100644 --- a/lib/stm32/f3/usart.c +++ b/lib/stm32/f3/usart.c @@ -126,7 +126,7 @@ usart_reg_base bool usart_get_interrupt_source(uint32_t usart, uint32_t flag) { - uint32_t flag_set = (USART_ISR(usart) & flag); + uint32_t flag_set = (USART_ISR(usart) & flag); /* IDLE, RXNE, TC, TXE interrupts */ if ((flag >= USART_ISR_IDLE) && (flag <= USART_ISR_TXE)) { return ((flag_set & USART_CR1(usart)) != 0); @@ -138,4 +138,4 @@ bool usart_get_interrupt_source(uint32_t usart, uint32_t flag) return false; } -/**@}*/ \ No newline at end of file +/**@}*/