stm32f3: f1 usb header files moved to stm32 root directory.
- Now the f1 usb header files serve both the f1 and f3. - usb_f103 modified to find the new headers file location.
This commit is contained in:
Federico Ruiz Ugalde
committed by
Piotr Esden-Tempski
Piotr Esden-Tempski
parent
934c8dbf4c
commit
60bdf4eebd
@@ -1,279 +0,0 @@
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/** @defgroup adc_defines USB Defines
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@brief <b>Defined Constants and Types for the STM32F1xx USB Module</b>
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@ingroup STM32F1xx_defines
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2009
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Piotr Esden-Tempski <piotr@esden.net>
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@date 11 March 2013
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2009 Piotr Esden-Tempski <piotr@esden.net>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#ifndef LIBOPENCM3_USB_H
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#define LIBOPENCM3_USB_H
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/stm32/tools.h>
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/* --- USB base addresses -------------------------------------------------- */
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/* USB packet buffer memory base address. */
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#define USB_PMA_BASE 0x40006000L
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/* --- USB general registers ----------------------------------------------- */
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/* USB Control register */
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#define USB_CNTR_REG (&MMIO32(USB_DEV_FS_BASE + 0x40))
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/* USB Interrupt status register */
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#define USB_ISTR_REG (&MMIO32(USB_DEV_FS_BASE + 0x44))
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/* USB Frame number register */
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#define USB_FNR_REG (&MMIO32(USB_DEV_FS_BASE + 0x48))
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/* USB Device address register */
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#define USB_DADDR_REG (&MMIO32(USB_DEV_FS_BASE + 0x4C))
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/* USB Buffer table address register */
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#define USB_BTABLE_REG (&MMIO32(USB_DEV_FS_BASE + 0x50))
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/* USB EP register */
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#define USB_EP_REG(EP) (&MMIO32(USB_DEV_FS_BASE) + (EP))
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/* --- USB control register masks / bits ----------------------------------- */
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/* Interrupt mask bits, set to 1 to enable interrupt generation */
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#define USB_CNTR_CTRM 0x8000
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#define USB_CNTR_PMAOVRM 0x4000
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#define USB_CNTR_ERRM 0x2000
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#define USB_CNTR_WKUPM 0x1000
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#define USB_CNTR_SUSPM 0x0800
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#define USB_CNTR_RESETM 0x0400
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#define USB_CNTR_SOFM 0x0200
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#define USB_CNTR_ESOFM 0x0100
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/* Request/Force bits */
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#define USB_CNTR_RESUME 0x0010 /* Resume request */
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#define USB_CNTR_FSUSP 0x0008 /* Force suspend */
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#define USB_CNTR_LP_MODE 0x0004 /* Low-power mode */
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#define USB_CNTR_PWDN 0x0002 /* Power down */
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#define USB_CNTR_FRES 0x0001 /* Force reset */
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/* --- USB interrupt status register masks / bits -------------------------- */
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#define USB_ISTR_CTR 0x8000 /* Correct Transfer */
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#define USB_ISTR_PMAOVR 0x4000 /* Packet Memory Area Over / Underrun */
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#define USB_ISTR_ERR 0x2000 /* Error */
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#define USB_ISTR_WKUP 0x1000 /* Wake up */
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#define USB_ISTR_SUSP 0x0800 /* Suspend mode request */
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#define USB_ISTR_RESET 0x0400 /* USB RESET request */
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#define USB_ISTR_SOF 0x0200 /* Start Of Frame */
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#define USB_ISTR_ESOF 0x0100 /* Expected Start Of Frame */
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#define USB_ISTR_DIR 0x0010 /* Direction of transaction */
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#define USB_ISTR_EP_ID 0x000F /* Endpoint Identifier */
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/* --- USB interrupt status register manipulators -------------------------- */
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/* Note: CTR is read only! */
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#define USB_CLR_ISTR_PMAOVR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_PMAOVR)
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#define USB_CLR_ISTR_ERR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ERR)
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#define USB_CLR_ISTR_WKUP() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_WKUP)
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#define USB_CLR_ISTR_SUSP() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SUSP)
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#define USB_CLR_ISTR_RESET() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_RESET)
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#define USB_CLR_ISTR_SOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SOF)
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#define USB_CLR_ISTR_ESOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ESOF)
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/* --- USB device address register masks / bits ---------------------------- */
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#define USB_DADDR_ENABLE 0x0080
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#define USB_DADDR_ADDR 0x007F
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/* --- USB device address register manipulators ---------------------------- */
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/* --- USB endpoint register offsets --------------------------------------- */
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#define USB_EP0 0
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#define USB_EP1 1
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#define USB_EP2 2
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#define USB_EP3 3
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#define USB_EP4 4
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#define USB_EP5 5
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#define USB_EP6 6
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#define USB_EP7 7
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/* --- USB endpoint register masks / bits ---------------------------------- */
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/* Masks and toggle bits */
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#define USB_EP_RX_CTR 0x8000 /* Correct transfer RX */
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#define USB_EP_RX_DTOG 0x4000 /* Data toggle RX */
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#define USB_EP_RX_STAT 0x3000 /* Endpoint status for RX */
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#define USB_EP_SETUP 0x0800 /* Setup transaction completed */
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#define USB_EP_TYPE 0x0600 /* Endpoint type */
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#define USB_EP_KIND 0x0100 /* Endpoint kind.
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* When set and type=bulk -> double buffer
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* When set and type=control -> status out
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*/
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#define USB_EP_TX_CTR 0x0080 /* Correct transfer TX */
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#define USB_EP_TX_DTOG 0x0040 /* Data toggle TX */
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#define USB_EP_TX_STAT 0x0030 /* Endpoint status for TX */
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#define USB_EP_ADDR 0x000F /* Endpoint Address */
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/* Masking all toggle bits */
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#define USB_EP_NTOGGLE_MSK (USB_EP_RX_CTR | \
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USB_EP_SETUP | \
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USB_EP_TYPE | \
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USB_EP_KIND | \
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USB_EP_TX_CTR | \
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USB_EP_ADDR)
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/* All non toggle bits plus EP_RX toggle bits */
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#define USB_EP_RX_STAT_TOG_MSK (USB_EP_RX_STAT | USB_EP_NTOGGLE_MSK)
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/* All non toggle bits plus EP_TX toggle bits */
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#define USB_EP_TX_STAT_TOG_MSK (USB_EP_TX_STAT | USB_EP_NTOGGLE_MSK)
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/* Endpoint status bits for USB_EP_RX_STAT bit field */
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#define USB_EP_RX_STAT_DISABLED 0x0000
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#define USB_EP_RX_STAT_STALL 0x1000
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#define USB_EP_RX_STAT_NAK 0x2000
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#define USB_EP_RX_STAT_VALID 0x3000
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/* Endpoint status bits for USB_EP_TX_STAT bit field */
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#define USB_EP_TX_STAT_DISABLED 0x0000
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#define USB_EP_TX_STAT_STALL 0x0010
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#define USB_EP_TX_STAT_NAK 0x0020
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#define USB_EP_TX_STAT_VALID 0x0030
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/* Endpoint type bits for USB_EP_TYPE bit field */
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#define USB_EP_TYPE_BULK 0x0000
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#define USB_EP_TYPE_CONTROL 0x0200
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#define USB_EP_TYPE_ISO 0x0400
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#define USB_EP_TYPE_INTERRUPT 0x0600
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/* --- USB endpoint register manipulators ---------------------------------- */
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/*
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* Set USB endpoint tx/rx status.
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*
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* USB status field is changed using an awkward toggle mechanism, that
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* is why we use some helper macros for that.
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*/
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#define USB_SET_EP_RX_STAT(EP, STAT) \
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TOG_SET_REG_BIT_MSK(USB_EP_REG(EP), USB_EP_RX_STAT_TOG_MSK, STAT)
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#define USB_SET_EP_TX_STAT(EP, STAT) \
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TOG_SET_REG_BIT_MSK(USB_EP_REG(EP), USB_EP_TX_STAT_TOG_MSK, STAT)
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/*
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* Macros for clearing and setting USB endpoint register bits that do
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* not use the toggle mechanism.
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*
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* Because the register contains some bits that use the toggle
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* mechanism we need a helper macro here. Otherwise the code gets really messy.
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*/
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#define USB_CLR_EP_NTOGGLE_BIT(EP, BIT) \
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CLR_REG_BIT_MSK(USB_EP_REG(EP), USB_EP_NTOGGLE_MSK, BIT)
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#define USB_CLR_EP_RX_CTR(EP) \
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USB_CLR_EP_NTOGGLE_BIT(EP, USB_EP_RX_CTR)
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#define USB_CLR_EP_TX_CTR(EP) \
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USB_CLR_EP_NTOGGLE_BIT(EP, USB_EP_TX_CTR)
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#define USB_SET_EP_TYPE(EP, TYPE) \
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SET_REG(USB_EP_REG(EP), \
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(GET_REG(USB_EP_REG(EP)) & \
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(USB_EP_NTOGGLE_MSK & \
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(~USB_EP_TYPE))) | TYPE)
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#define USB_SET_EP_KIND(EP) \
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SET_REG(USB_EP_REG(EP), \
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(GET_REG(USB_EP_REG(EP)) & \
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(USB_EP_NTOGGLE_MSK & \
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(~USB_EP_KIND))) | USB_EP_KIND)
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#define USB_CLR_EP_KIND(EP) \
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SET_REG(USB_EP_REG(EP), \
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(GET_REG(USB_EP_REG(EP)) & \
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(USB_EP_NTOGGLE_MSK & (~USB_EP_KIND))))
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#define USB_SET_EP_STAT_OUT(EP) USB_SET_EP_KIND(EP)
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#define USB_CLR_EP_STAT_OUT(EP) USB_CLR_EP_KIND(EP)
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#define USB_SET_EP_ADDR(EP, ADDR) \
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SET_REG(USB_EP_REG(EP), \
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((GET_REG(USB_EP_REG(EP)) & \
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(USB_EP_NTOGGLE_MSK & \
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(~USB_EP_ADDR))) | ADDR))
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/* Macros for clearing DTOG bits */
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#define USB_CLR_EP_TX_DTOG(EP) \
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SET_REG(USB_EP_REG(EP), \
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GET_REG(USB_EP_REG(EP)) & \
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(USB_EP_NTOGGLE_MSK | USB_EP_TX_DTOG))
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#define USB_CLR_EP_RX_DTOG(EP) \
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SET_REG(USB_EP_REG(EP), \
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GET_REG(USB_EP_REG(EP)) & \
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(USB_EP_NTOGGLE_MSK | USB_EP_RX_DTOG))
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/* --- USB BTABLE registers ------------------------------------------------ */
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#define USB_GET_BTABLE GET_REG(USB_BTABLE_REG)
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#define USB_EP_TX_ADDR(EP) \
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((uint32_t *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 0) * 2))
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#define USB_EP_TX_COUNT(EP) \
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((uint32_t *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 2) * 2))
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#define USB_EP_RX_ADDR(EP) \
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((uint32_t *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 4) * 2))
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#define USB_EP_RX_COUNT(EP) \
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((uint32_t *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 6) * 2))
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/* --- USB BTABLE manipulators --------------------------------------------- */
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#define USB_GET_EP_TX_ADDR(EP) GET_REG(USB_EP_TX_ADDR(EP))
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#define USB_GET_EP_TX_COUNT(EP) GET_REG(USB_EP_TX_COUNT(EP))
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#define USB_GET_EP_RX_ADDR(EP) GET_REG(USB_EP_RX_ADDR(EP))
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#define USB_GET_EP_RX_COUNT(EP) GET_REG(USB_EP_RX_COUNT(EP))
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#define USB_SET_EP_TX_ADDR(EP, ADDR) SET_REG(USB_EP_TX_ADDR(EP), ADDR)
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#define USB_SET_EP_TX_COUNT(EP, COUNT) SET_REG(USB_EP_TX_COUNT(EP), COUNT)
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#define USB_SET_EP_RX_ADDR(EP, ADDR) SET_REG(USB_EP_RX_ADDR(EP), ADDR)
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#define USB_SET_EP_RX_COUNT(EP, COUNT) SET_REG(USB_EP_RX_COUNT(EP), COUNT)
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#define USB_GET_EP_TX_BUFF(EP) \
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(USB_PMA_BASE + (uint8_t *)(USB_GET_EP_TX_ADDR(EP) * 2))
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#define USB_GET_EP_RX_BUFF(EP) \
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(USB_PMA_BASE + (uint8_t *)(USB_GET_EP_RX_ADDR(EP) * 2))
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#endif
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/**@}*/
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@@ -1,101 +0,0 @@
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2009 Piotr Esden-Tempski <piotr@esden.net>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_USB_DESC
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#define LIBOPENCM3_USB_DESC
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/* Descriptor types */
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#define USB_DT_DEVICE 0x01
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#define USB_DT_CONF 0x02
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#define USB_DT_STRING 0x03
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#define USB_DT_INTERFACE 0x04
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#define USB_DT_ENDPOINT 0x05
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struct usb_desc_head {
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uint8_t length; /* Descriptor size 0x012 */
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uint8_t type; /* Descriptor type ID */
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};
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struct usb_device_desc {
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struct usb_desc_head h; /* Size 0x12, ID 0x01 */
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uint16_t bcd_usb; /* USB Version */
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uint8_t class; /* Device class */
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uint8_t sub_class; /* Subclass code */
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uint8_t protocol; /* Protocol code */
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uint8_t max_psize; /* Maximum packet size -> 64bytes */
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uint16_t vendor; /* Vendor number */
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uint16_t product; /* Device number */
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uint16_t bcd_dev; /* Device version */
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uint8_t man_desc; /* Index of manufacturer string desc */
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uint8_t prod_desc; /* Index of product string desc */
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uint8_t sn_desc; /* Index of serial number string desc */
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uint8_t num_conf; /* Number of possible configurations */
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};
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struct usb_conf_desc_header {
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struct usb_desc_head h; /* Size 0x09, Id 0x02 */
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uint16_t tot_leng; /* Total length of data */
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uint8_t num_int; /* Number of interfaces */
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uint8_t conf_val; /* Configuration selector */
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uint8_t conf_desc; /* Index of conf string desc */
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uint8_t attr; /* Attribute bitmap:
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* 7 : Bus powered
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* 6 : Self powered
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* 5 : Remote wakeup
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* 4..0 : Reserved -> 0000
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*/
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uint8_t max_power; /* Maximum power consumption in 2mA steps */
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};
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struct usb_int_desc_header {
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struct usb_desc_head h; /* Size 0x09, Id 0x04 */
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uint8_t iface_num; /* Interface id number */
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uint8_t alt_setting; /* Alternative setting selector */
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uint8_t num_endp; /* Endpoints used */
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uint8_t class; /* Interface class */
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uint8_t sub_class; /* Subclass code */
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uint8_t protocol; /* Protocol code */
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uint8_t iface_desc; /* Index of interface string desc */
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};
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struct usb_ep_desc {
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struct usb_desc_head h; /* Size 0x07, Id 0x05 */
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uint8_t ep_addr; /* Endpoint address:
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0..3 : Endpoint Number
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4..6 : Reserved -> 0
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7 : Direction 0=out 1=in */
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uint8_t ep_attr; /* Endpoint attributes */
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uint16_t max_psize; /* Maximum packet size -> 64bytes */
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uint8_t interval; /* Interval for polling endpoint
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data. Ignored for bulk & control
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endpoints. */
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};
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struct usb_conf_desc {
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struct usb_conf_desc_header cdh;
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struct usb_int_desc_header idh;
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struct usb_ep_desc ep[];
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};
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struct usb_string_desc {
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struct usb_desc_head h; /* Size > 0x02, Id 0x03 */
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uint16_t string[]; /* String UTF16 encoded */
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};
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#endif
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