STM32H7: Add support for RAM4 & RAM5, cleanup

* added: Linker script adds support for RAM4 and RAM5 memory regions, so
  that those are usable by code. This also fixes the fact that RAM4 was
  declared, but inaccessible previously
* changed: RAM1 is renamed to RAM2, shifting numbering of all regions.
  This is done in order to be in line with other STM32 definitions,
  similarly ROM1 became ROM2.

ld/linker.ld.S

@@ -50,6 +50,12 @@ MEMORY
 #if defined(_RAM3)
 	ram3 (rwx) : ORIGIN = _RAM3_OFF, LENGTH = _RAM3
 #endif
+#if defined(_RAM4)
+	ram4 (rwx) : ORIGIN = _RAM4_OFF, LENGTH = _RAM4
+#endif
+#if defined(_RAM5)
+	ram5 (rwx) : ORIGIN = _RAM5_OFF, LENGTH = _RAM5
+#endif
 #if defined(_CCM)
 	ccm (rwx) : ORIGIN = _CCM_OFF, LENGTH = _CCM
 #endif
@@ -168,6 +174,20 @@ SECTIONS
 	} >ram3
 #endif
 
+#if defined(_RAM4)
+	.ram4 : {
+		*(.ram4*)
+		. = ALIGN(4);
+	} >ram4
+#endif
+
+#if defined(_RAM5)
+	.ram5 : {
+		*(.ram5*)
+		. = ALIGN(4);
+	} >ram4
+#endif
+
 #if defined(_XSRAM)
 	.xsram : {
 		*(.xsram*)