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stm32l4: fix various problems with rcc_get* functions

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- rcc_get_i2c_clk_freq: Add support by taking RCC_CCIPR2 into account for I2C4.
 - rcc_get_timer_clk_freq: Add support for LP timers
 - rcc_get_usart_clk_freq: Fix APB freq used for LPUART1 and UART1, respectively.
This commit is contained in:
Stefan Tauner
2022-03-02 09:05:28 +01:00
committed by Karl Palsson
parent a6927e410c
commit 5bcf2a0c35
2 changed files with 35 additions and 21 deletions
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9
include/libopencm3/stm32/l4/rcc.h
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@@ -90,6 +90,7 @@
#define RCC_BDCR MMIO32(RCC_BASE + 0x90)
#define RCC_CSR MMIO32(RCC_BASE + 0x94)
#define RCC_CRRCR MMIO32(RCC_BASE + 0x98)
#define RCC_CCIPR2 MMIO32(RCC_BASE + 0x9C)
/* --- RCC_CR values ------------------------------------------------------- */
@@ -636,6 +637,7 @@ Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz,
#define RCC_CCIPR_I2CxSEL_SYS 1
#define RCC_CCIPR_I2CxSEL_HSI16 2
#define RCC_CCIPR_I2CxSEL_MASK 0x3
#define RCC_CCIPR_I2C4SEL_SHIFT 0
#define RCC_CCIPR_I2C3SEL_SHIFT 16
#define RCC_CCIPR_I2C2SEL_SHIFT 14
#define RCC_CCIPR_I2C1SEL_SHIFT 12
@@ -663,13 +665,6 @@ Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz,
#define RCC_CCIPR_USART2SEL_SHIFT 2
#define RCC_CCIPR_USART1SEL_SHIFT 0
#define RCC_CCIPR_USART1SEL_APB 0
#define RCC_CCIPR_USART1SEL_SYS 1
#define RCC_CCIPR_USART1SEL_HSI16 2
#define RCC_CCIPR_USART1SEL_LSE 3
#define RCC_CCIPR_USART1SEL_SHIFT 0
#define RCC_CCIPR_USART1SEL_MASK 0x3
/* --- RCC_BDCR - Backup domain control register --------------------------- */
#define RCC_BDCR_LSCOSEL (1 << 25)