This mainly moves the STM32 timers' code to the common area.
F2 and F4 have a common section to deal with the options register (TIM2 and TIM5 only) L1 has been made common with timer_common_all as its options register has very different settings to F2/F4. Code is in the L1/timer.c L1/timer.h files Note that F3 and F05 timers should fit into this scheme, with F3 having additional features. Bundled with this is L1/pwr.h to change a documentation setting Also all the Doxyfiles have added "ENABLE_PREPROCESSING = NO" to fix a problem introduced by commit 118.
This commit is contained in:
Ken Sarkies
1113
include/libopencm3/stm32/common/timer_common_all.h
Normal file
1113
include/libopencm3/stm32/common/timer_common_all.h
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File diff suppressed because it is too large
Load Diff
99
include/libopencm3/stm32/common/timer_common_f24.h
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99
include/libopencm3/stm32/common/timer_common_f24.h
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@@ -0,0 +1,99 @@
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/** @addtogroup timer_defines
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@author @htmlonly © @endhtmlonly 2011 Fergus Noble <fergusnoble@gmail.com>
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA TIMER.H
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The order of header inclusion is important. timer.h includes the device
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specific memorymap.h header before including this header file.*/
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#ifdef LIBOPENCM3_TIMER_H
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#ifndef LIBOPENCM3_TIMER_COMMON_F24_H
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#define LIBOPENCM3_TIMER_COMMON_F24_H
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#include <libopencm3/stm32/common/timer_common_all.h>
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/*
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* TIM2 and TIM5 are now 32bit and the following registers are now 32-bit wide:
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* CNT, ARR, CCR1, CCR2, CCR3, CCR4
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*/
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/* Timer 2/5 option register (TIMx_OR) */
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#define TIM_OR(tim_base) MMIO32(tim_base + 0x50)
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#define TIM2_OR TIM_OR(TIM2)
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#define TIM5_OR TIM_OR(TIM5)
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/* --- TIM2_OR values ---------------------------------------------------- */
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/* ITR1_RMP */
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/****************************************************************************/
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/** @defgroup tim2_opt_trigger_remap TIM2_OR Timer 2 Option Register Internal Trigger 1 Remap
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Only available in F2 and F4 series.
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@ingroup timer_defines
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@{*/
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/** Internal Trigger 1 remapped to timer 8 trigger out */
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#define TIM2_OR_ITR1_RMP_TIM8_TRGOU (0x0 << 10)
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/** Internal Trigger 1 remapped to PTP trigger out */
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#define TIM2_OR_ITR1_RMP_PTP (0x1 << 10)
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/** Internal Trigger 1 remapped to USB OTG FS SOF */
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#define TIM2_OR_ITR1_RMP_OTG_FS_SOF (0x2 << 10)
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/** Internal Trigger 1 remapped to USB OTG HS SOF */
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#define TIM2_OR_ITR1_RMP_OTG_HS_SOF (0x3 << 10)
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/**@}*/
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#define TIM2_OR_ITR1_RMP_MASK (0x3 << 10)
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/* --- TIM5_OR values ---------------------------------------------------- */
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/* ITR4_RMP */
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/****************************************************************************/
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/** @defgroup tim5_opt_trigger_remap TIM5_OR Timer 5 Option Register Internal Trigger 4 Remap
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Only available in F2 and F4 series.
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@ingroup timer_defines
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@{*/
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/** Internal Trigger 4 remapped to GPIO (see reference manual) */
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#define TIM5_OR_TI4_RMP_GPIO (0x0 << 6)
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/** Internal Trigger 4 remapped to LSI internal clock */
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#define TIM5_OR_TI4_RMP_LSI (0x1 << 6)
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/** Internal Trigger 4 remapped to LSE internal clock */
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#define TIM5_OR_TI4_RMP_LSE (0x2 << 6)
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/** Internal Trigger 4 remapped to RTC output event */
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#define TIM5_OR_TI4_RMP_RTC (0x3 << 6)
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/**@}*/
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#define TIM5_OR_TI4_RMP_MASK (0x3 << 6)
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/* --- Function prototypes ------------------------------------------------- */
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BEGIN_DECLS
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void timer_set_option(u32 timer_peripheral, u32 option);
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END_DECLS
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#endif
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#else
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#warning "timer_common_f24.h should not be included explicitly, only via timer.h"
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#endif
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40
include/libopencm3/stm32/f1/timer.h
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40
include/libopencm3/stm32/f1/timer.h
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@@ -0,0 +1,40 @@
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/** @defgroup timer_defines Timer Defines
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@brief <b>libopencm3 Defined Constants and Types for the STM32F1xx Timers</b>
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@ingroup STM32F1xx_defines
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@version 1.0.0
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@date 8 March 2013
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@author @htmlonly © @endhtmlonly 2011 Fergus Noble <fergusnoble@gmail.com>
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_TIMER_H
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#define LIBOPENCM3_TIMER_H
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#include <libopencm3/stm32/common/timer_common_all.h>
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#endif
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@@ -1,3 +1,17 @@
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/** @defgroup timer_defines Timer Defines
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@brief <b>libopencm3 Defined Constants and Types for the STM32F2xx Timers</b>
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@ingroup STM32F2xx_defines
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@version 1.0.0
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@date 8 March 2013
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@author @htmlonly © @endhtmlonly 2011 Fergus Noble <fergusnoble@gmail.com>
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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@@ -17,45 +31,9 @@
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_TIMER_F2_H
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#define LIBOPENCM3_TIMER_F2_H
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#ifndef LIBOPENCM3_TIMER_H
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#define LIBOPENCM3_TIMER_H
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#include <libopencm3/stm32/timer.h>
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/*
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* TIM2 and TIM5 are now 32bit and the following registers are now 32-bit wide:
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* CNT, ARR, CCR1, CCR2, CCR3, CCR4
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*/
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/* Timer 2/5 option register (TIMx_OR) */
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#define TIM_OR(tim_base) MMIO32(tim_base + 0x50)
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#define TIM2_OR TIM_OR(TIM2)
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#define TIM5_OR TIM_OR(TIM5)
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/* --- TIM2_OR values ---------------------------------------------------- */
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/* MOE: Main output enable */
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#define TIM2_OR_ITR1_RMP_TIM8_TRGOU (0x0 << 10)
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#define TIM2_OR_ITR1_RMP_PTP (0x1 << 10)
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#define TIM2_OR_ITR1_RMP_OTG_FS_SOF (0x2 << 10)
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#define TIM2_OR_ITR1_RMP_OTG_HS_SOF (0x3 << 10)
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#define TIM2_OR_ITR1_RMP_MASK (0x3 << 10)
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/* --- TIM5_OR values ---------------------------------------------------- */
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/* MOE: Main output enable */
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#define TIM5_OR_TI4_RMP_GPIO (0x0 << 6)
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#define TIM5_OR_TI4_RMP_LSI (0x1 << 6)
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#define TIM5_OR_TI4_RMP_LSE (0x2 << 6)
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#define TIM5_OR_TI4_RMP_RTC (0x3 << 6)
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#define TIM5_OR_TI4_RMP_MASK (0x3 << 6)
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/* --- Function prototypes ------------------------------------------------- */
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BEGIN_DECLS
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void timer_set_option(u32 timer_peripheral, u32 option);
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END_DECLS
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#include <libopencm3/stm32/common/timer_common_f24.h>
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#endif
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@@ -1,3 +1,17 @@
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/** @defgroup timer_defines Timer Defines
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@brief <b>libopencm3 Defined Constants and Types for the STM32F4xx Timers</b>
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@ingroup STM32F4xx_defines
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@version 1.0.0
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@date 8 March 2013
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@author @htmlonly © @endhtmlonly 2011 Fergus Noble <fergusnoble@gmail.com>
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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@@ -17,45 +31,9 @@
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_TIMER_F4_H
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#define LIBOPENCM3_TIMER_F4_H
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#ifndef LIBOPENCM3_TIMER_H
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#define LIBOPENCM3_TIMER_H
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#include <libopencm3/stm32/timer.h>
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/*
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* TIM2 and TIM5 are now 32bit and the following registers are now 32-bit wide:
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* CNT, ARR, CCR1, CCR2, CCR3, CCR4
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*/
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/* Timer 2/5 option register (TIMx_OR) */
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#define TIM_OR(tim_base) MMIO32(tim_base + 0x50)
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#define TIM2_OR TIM_OR(TIM2)
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#define TIM5_OR TIM_OR(TIM5)
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/* --- TIM2_OR values ---------------------------------------------------- */
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/* MOE: Main output enable */
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#define TIM2_OR_ITR1_RMP_TIM8_TRGOU (0x0 << 10)
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#define TIM2_OR_ITR1_RMP_PTP (0x1 << 10)
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#define TIM2_OR_ITR1_RMP_OTG_FS_SOF (0x2 << 10)
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#define TIM2_OR_ITR1_RMP_OTG_HS_SOF (0x3 << 10)
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#define TIM2_OR_ITR1_RMP_MASK (0x3 << 10)
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/* --- TIM5_OR values ---------------------------------------------------- */
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/* MOE: Main output enable */
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#define TIM5_OR_TI4_RMP_GPIO (0x0 << 6)
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#define TIM5_OR_TI4_RMP_LSI (0x1 << 6)
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#define TIM5_OR_TI4_RMP_LSE (0x2 << 6)
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#define TIM5_OR_TI4_RMP_RTC (0x3 << 6)
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#define TIM5_OR_TI4_RMP_MASK (0x3 << 6)
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/* --- Function prototypes ------------------------------------------------- */
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BEGIN_DECLS
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void timer_set_option(u32 timer_peripheral, u32 option);
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END_DECLS
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#include <libopencm3/stm32/common/timer_common_f24.h>
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#endif
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@@ -54,7 +54,7 @@ LGPL License Terms @ref lgpl_license
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/* VOS[12:11]: Regulator voltage scaling output selection */
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#define PWR_CR_VOS_LSB 11
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/** @defgroup pwr_vos Voltage Scaling Output level selection
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@ingroup STM32F_pwr_defines
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@ingroup pwr_defines
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@{*/
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#define PWR_CR_VOS_RANGE1 (0x1 << PWR_CR_VOS_LSB)
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88
include/libopencm3/stm32/l1/timer.h
Normal file
88
include/libopencm3/stm32/l1/timer.h
Normal file
@@ -0,0 +1,88 @@
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/** @defgroup timer_defines Timer Defines
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@brief <b>libopencm3 Defined Constants and Types for the STM32L1xx Timers</b>
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@ingroup STM32L1xx_defines
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@version 1.0.0
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@date 8 March 2013
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@author @htmlonly © @endhtmlonly 2011 Fergus Noble <fergusnoble@gmail.com>
|
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LGPL License Terms @ref lgpl_license
|
||||
*/
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||||
|
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/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LIBOPENCM3_TIMER_H
|
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#define LIBOPENCM3_TIMER_H
|
||||
|
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#include <libopencm3/stm32/common/timer_common_all.h>
|
||||
|
||||
/*
|
||||
* TIM2 and TIM5 are now 32bit and the following registers are now 32-bit wide:
|
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* CNT, ARR, CCR1, CCR2, CCR3, CCR4
|
||||
*/
|
||||
|
||||
/* Timer 2/3 option register (TIMx_OR) */
|
||||
#define TIM_OR(tim_base) MMIO32(tim_base + 0x50)
|
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#define TIM2_OR TIM_OR(TIM2)
|
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#define TIM3_OR TIM_OR(TIM3)
|
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|
||||
/* --- TIMx_OR values ---------------------------------------------------- */
|
||||
|
||||
/* ITR1_RMP */
|
||||
/****************************************************************************/
|
||||
/** @defgroup tim2_opt_trigger_remap TIM2_OR Timer 2 Option Register Internal Trigger 1 Remap
|
||||
@ingroup timer_defines
|
||||
|
||||
@{*/
|
||||
/** Internal Trigger 1 remapped to timer 10 output compare */
|
||||
#define TIM2_OR_ITR1_RMP_TIM10_OC (0x0 << 0)
|
||||
/** Internal Trigger 1 remapped to timer 5 TGO */
|
||||
#define TIM2_OR_ITR1_RMP_TIM5_TGO (0x1 << 0)
|
||||
/**@}*/
|
||||
#define TIM3_OR_ITR1_RMP_MASK (0x1 << 0)
|
||||
|
||||
/* --- TIMx_OR values ---------------------------------------------------- */
|
||||
|
||||
/* ITR2_RMP */
|
||||
/****************************************************************************/
|
||||
/** @defgroup tim3_opt_trigger_remap TIM3_OR Timer 3 Option Register Internal Trigger 2 Remap
|
||||
@ingroup timer_defines
|
||||
|
||||
@{*/
|
||||
/** Internal Trigger 1 remapped to timer 11 output compare */
|
||||
#define TIM3_OR_ITR2_RMP_TIM8_TRGOU (0x0 << 0)
|
||||
/** Internal Trigger 1 remapped to timer 5 TGO */
|
||||
#define TIM3_OR_ITR2_RMP_PTP (0x1 << 0)
|
||||
/**@}*/
|
||||
#define TIM3_OR_ITR2_RMP_MASK (0x1 << 0)
|
||||
|
||||
/* --- Function prototypes ------------------------------------------------- */
|
||||
|
||||
BEGIN_DECLS
|
||||
|
||||
void timer_set_option(u32 timer_peripheral, u32 option);
|
||||
|
||||
END_DECLS
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user