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stm32f3: Some additions to rcc.

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- Additional frequency configuration (48Mhz, for usb use!)
- FLASH latency decreased (too unnecessarily low before)
- Rcc functions to change usb freq prescaler.
This commit is contained in:
Federico Ruiz Ugalde
2013-06-30 21:57:27 -06:00
committed by Piotr Esden-Tempski
parent 011124c33f
commit 59b2b5da87
2 changed files with 26 additions and 2 deletions
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3
include/libopencm3/stm32/f3/rcc.h
View File

@@ -381,6 +381,7 @@ extern uint32_t rcc_ppre2_frequency;
typedef enum { typedef enum {
CLOCK_44MHZ, CLOCK_44MHZ,
CLOCK_48MHZ,
CLOCK_64MHZ, CLOCK_64MHZ,
CLOCK_END CLOCK_END
} clock_t; } clock_t;
@@ -436,6 +437,8 @@ void rcc_clock_setup_hsi(const clock_scale_t *clock);
void rcc_set_i2c_clock_hsi(uint32_t i2c); void rcc_set_i2c_clock_hsi(uint32_t i2c);
void rcc_set_i2c_clock_sysclk(uint32_t i2c); void rcc_set_i2c_clock_sysclk(uint32_t i2c);
uint32_t rcc_get_i2c_clocks(void); uint32_t rcc_get_i2c_clocks(void);
void rcc_usb_prescale_1_5(void);
void rcc_usb_prescale_1(void);
END_DECLS END_DECLS

25
lib/stm32/f3/rcc.c
View File

@@ -39,10 +39,21 @@ const clock_scale_t hsi_8mhz[CLOCK_END] =
.ppre1 = RCC_CFGR_PPRE1_DIV_2, .ppre1 = RCC_CFGR_PPRE1_DIV_2,
.ppre2 = RCC_CFGR_PPRE2_DIV_NONE, .ppre2 = RCC_CFGR_PPRE2_DIV_NONE,
.power_save = 1, .power_save = 1,
.flash_config = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY_2WS, .flash_config = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY_1WS,
.apb1_frequency = 22000000, .apb1_frequency = 22000000,
.apb2_frequency = 44000000, .apb2_frequency = 44000000,
}, },
{ /* 48MHz */
.pll= RCC_CFGR_PLLMUL_PLL_IN_CLK_X12,
.pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE1_DIV_2,
.ppre2 = RCC_CFGR_PPRE2_DIV_NONE,
.power_save = 1,
.flash_config = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY_1WS,
.apb1_frequency = 24000000,
.apb2_frequency = 48000000,
},
{ /* 64MHz */ { /* 64MHz */
.pll= RCC_CFGR_PLLMUL_PLL_IN_CLK_X16, .pll= RCC_CFGR_PLLMUL_PLL_IN_CLK_X16,
.pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2, .pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2,
@@ -50,7 +61,7 @@ const clock_scale_t hsi_8mhz[CLOCK_END] =
.ppre1 = RCC_CFGR_PPRE1_DIV_2, .ppre1 = RCC_CFGR_PPRE1_DIV_2,
.ppre2 = RCC_CFGR_PPRE2_DIV_NONE, .ppre2 = RCC_CFGR_PPRE2_DIV_NONE,
.power_save = 1, .power_save = 1,
.flash_config = FLASH_ACR_PRFTBE| FLASH_ACR_LATENCY_3WS, .flash_config = FLASH_ACR_PRFTBE| FLASH_ACR_LATENCY_2WS,
.apb1_frequency = 32000000, .apb1_frequency = 32000000,
.apb2_frequency = 64000000, .apb2_frequency = 64000000,
} }
@@ -445,3 +456,13 @@ uint32_t rcc_get_i2c_clocks(void)
{ {
return(RCC_CFGR3 & (RCC_CFGR3_I2C1SW | RCC_CFGR3_I2C2SW)); return(RCC_CFGR3 & (RCC_CFGR3_I2C1SW | RCC_CFGR3_I2C2SW));
} }
void rcc_usb_prescale_1_5(void)
{
RCC_CFGR &= ~RCC_CFGR_USBPRES;
}
void rcc_usb_prescale_1(void)
{
RCC_CFGR |= RCC_CFGR_USBPRES;
}