Added output compare channel convenience functions and adapted the pwm_6step example accordingly.
This commit is contained in:
Piotr Esden-Tempski
@@ -87,222 +87,103 @@ void tim_setup(void)
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/* Enable preload. */
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timer_enable_preload(TIM1);
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//timer_disable_preload(TIM1);
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/* Continous mode. */
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timer_continuous_mode(TIM1);
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/* Period (32kHz) */
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TIM1_ARR = 72000000 / 32000;
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timer_set_period(TIM1, 72000000 / 32000);
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/* -- OC1 and OC1N configuration -- */
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{
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u16 tmp_ccmr1 = 0, tmp_ccer = 0, tmp_cr2 = 0;
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/** Disable OC1. **/
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TIM1_CCER &= ~TIM_CCER_CC1E;
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/* Disable outputs. */
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timer_disable_oc_output(TIM1, TIM_OC1);
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timer_disable_oc_output(TIM1, TIM_OC1N);
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/** Disable OC1N. **/
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TIM1_CCER &= ~TIM_CCER_CC1NE;
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/* Configure global mode of line 1. */
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timer_disable_oc_clear(TIM1, TIM_OC1);
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timer_enable_oc_preload(TIM1, TIM_OC1);
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timer_set_oc_slow_mode(TIM1, TIM_OC1);
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timer_set_oc_mode(TIM1, TIM_OC1, TIM_CCMR1_OC1M_PWM1);
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/** Get registers. **/
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tmp_ccmr1 = TIM1_CCMR1;
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tmp_ccer = TIM1_CCER;
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tmp_cr2 = TIM1_CR2;
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/* Configure OC1. */
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timer_set_oc_polarity_high(TIM1, TIM_OC1);
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timer_set_oc_idle_state_set(TIM1, TIM_OC1);
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/** Configure global mode of line 1 **/
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/* Configure OC1N. */
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timer_set_oc_polarity_high(TIM1, TIM_OC1N);
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timer_set_oc_idle_state_set(TIM1, TIM_OC1N);
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/* Disable OC1 clear. (esden: What is that?) */
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tmp_ccmr1 &= ~TIM_CCMR1_OC1CE;
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/* Set the capture compare value for OC1. */
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timer_set_oc_value(TIM1, TIM_OC1, 100);
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/* Set CC1 to output mode. */
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tmp_ccmr1 &= ~TIM_CCMR1_CC1S_MASK;
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tmp_ccmr1 |= TIM_CCMR1_CC1S_OUT;
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/* Enable OC1 preload enable. */
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//tmp_ccmr1 |= TIM_CCMR1_OC1PE;
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tmp_ccmr1 &= ~TIM_CCMR1_OC1PE;
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/* Disable OC1 fast mode. */
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tmp_ccmr1 &= ~TIM_CCMR1_OC1FE;
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/* Set OC1 mode to PWM1. */
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tmp_ccmr1 &= ~TIM_CCMR1_OC1M_MASK;
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tmp_ccmr1 |= TIM_CCMR1_OC1M_PWM1;
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/** Configure OC1. **/
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/* Set output polarity level, high. */
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tmp_ccer &= ~TIM_CCER_CC1P;
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/* Enable OC1 output */
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tmp_ccer |= TIM_CCER_CC1E;
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/* Set OC1 idle state to "set". (TIM1 and TIM8 only) */
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tmp_cr2 |= TIM_CR2_OIS1;
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/** Configure OC1N. **/
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/* Set output polarity level, high. (TIM1 and TIM8 only) */
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tmp_ccer &= ~TIM_CCER_CC1NP;
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/* Enable OC1N output. (TIM1 and TIM8 only) */
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tmp_ccer |= TIM_CCER_CC1NE;
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/* Set OC1N idle state to "set". (TIM1 and TIM8 only) */
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tmp_cr2 |= TIM_CR2_OIS1N;
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/** Set the capture compare value for OC1 **/
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TIM1_CCR1 = 100;
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/** Write register values **/
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TIM1_CR2 = tmp_cr2;
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TIM1_CCMR1 = tmp_ccmr1;
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TIM1_CCER = tmp_ccer;
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}
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/* Reenable outputs. */
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timer_enable_oc_output(TIM1, TIM_OC1);
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timer_enable_oc_output(TIM1, TIM_OC1N);
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/* -- OC2 and OC2N configuration -- */
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{
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u16 tmp_ccmr1 = 0, tmp_ccer = 0, tmp_cr2 = 0;
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/** Disable OC2. **/
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TIM1_CCER &= ~TIM_CCER_CC2E;
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/* Disable outputs. */
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timer_disable_oc_output(TIM1, TIM_OC2);
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timer_disable_oc_output(TIM1, TIM_OC2N);
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/** Disable OC2N. **/
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TIM1_CCER &= ~TIM_CCER_CC2NE;
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/* Configure global mode of line 2. */
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timer_disable_oc_clear(TIM1, TIM_OC2);
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timer_enable_oc_preload(TIM1, TIM_OC2);
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timer_set_oc_slow_mode(TIM1, TIM_OC2);
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timer_set_oc_mode(TIM1, TIM_OC2, TIM_CCMR1_OC2M_PWM1);
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/** Get registers. **/
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tmp_ccmr1 = TIM1_CCMR1;
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tmp_ccer = TIM1_CCER;
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tmp_cr2 = TIM1_CR2;
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/* Configure OC2. */
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timer_set_oc_polarity_high(TIM1, TIM_OC2);
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timer_set_oc_idle_state_set(TIM1, TIM_OC2);
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/** Configure global mode of line 1 **/
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/* Configure OC2N. */
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timer_set_oc_polarity_high(TIM1, TIM_OC2N);
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timer_set_oc_idle_state_set(TIM1, TIM_OC2N);
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/* Disable OC2 clear. (esden: What is that?) */
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tmp_ccmr1 &= ~TIM_CCMR1_OC2CE;
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/* Set the capture compare value for OC1. */
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timer_set_oc_value(TIM1, TIM_OC2, 200);
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/* Set CC2 to output mode. */
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tmp_ccmr1 &= ~TIM_CCMR1_CC2S_MASK;
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tmp_ccmr1 |= TIM_CCMR1_CC2S_OUT;
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/* Enable OC2 preload enable. */
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tmp_ccmr1 |= TIM_CCMR1_OC2PE;
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/* Disable OC2 fast mode. */
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tmp_ccmr1 &= ~TIM_CCMR1_OC2FE;
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/* Set OC2 mode to PWM1. */
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tmp_ccmr1 &= ~TIM_CCMR1_OC2M_MASK;
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tmp_ccmr1 |= TIM_CCMR1_OC2M_PWM1;
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/** Configure OC2. **/
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/* Set output polarity level, high. */
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tmp_ccer &= ~TIM_CCER_CC2P;
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/* Enable OC2 output */
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tmp_ccer |= TIM_CCER_CC2E;
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/* Set OC2 idle state to "set". (TIM1 and TIM8 only) */
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tmp_cr2 |= TIM_CR2_OIS2;
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/** Configure OC2N. **/
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/* Set output polarity level, high. (TIM1 and TIM8 only) */
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tmp_ccer &= ~TIM_CCER_CC2NP;
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/* Enable OC2N output. (TIM1 and TIM8 only) */
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tmp_ccer |= TIM_CCER_CC2NE;
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/* Set OC2N idle state to "set". (TIM1 and TIM8 only) */
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tmp_cr2 |= TIM_CR2_OIS2N;
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/** Set the capture compare value for OC2 **/
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TIM1_CCR2 = 200;
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/** Write register values **/
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TIM1_CR2 = tmp_cr2;
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TIM1_CCMR1 = tmp_ccmr1;
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TIM1_CCER = tmp_ccer;
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}
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/* Reenable outputs. */
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timer_enable_oc_output(TIM1, TIM_OC2);
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timer_enable_oc_output(TIM1, TIM_OC2N);
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/* -- OC3 and OC3N configuration -- */
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{
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u16 tmp_ccmr2 = 0, tmp_ccer = 0, tmp_cr2 = 0;
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/** Disable OC3. **/
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TIM1_CCER &= ~TIM_CCER_CC3E;
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/* Disable outputs. */
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timer_disable_oc_output(TIM1, TIM_OC3);
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timer_disable_oc_output(TIM1, TIM_OC3N);
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/** Disable OC3N. **/
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TIM1_CCER &= ~TIM_CCER_CC3NE;
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/* Configure global mode of line 3. */
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timer_disable_oc_clear(TIM1, TIM_OC3);
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timer_enable_oc_preload(TIM1, TIM_OC3);
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timer_set_oc_slow_mode(TIM1, TIM_OC3);
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timer_set_oc_mode(TIM1, TIM_OC3, TIM_CCMR2_OC3M_PWM1);
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/** Get registers. **/
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tmp_ccmr2 = TIM1_CCMR2;
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tmp_ccer = TIM1_CCER;
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tmp_cr2 = TIM1_CR2;
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/* Configure OC3. */
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timer_set_oc_polarity_high(TIM1, TIM_OC3);
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timer_set_oc_idle_state_set(TIM1, TIM_OC3);
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/** Configure global mode of line 1 **/
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/* Configure OC3N. */
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timer_set_oc_polarity_high(TIM1, TIM_OC3N);
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timer_set_oc_idle_state_set(TIM1, TIM_OC3N);
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/* Disable OC3 clear. (esden: What is that?) */
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tmp_ccmr2 &= ~TIM_CCMR2_OC3CE;
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/* Set the capture compare value for OC3. */
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timer_set_oc_value(TIM1, TIM_OC3, 300);
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/* Set CC3 to output mode. */
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tmp_ccmr2 &= ~TIM_CCMR2_CC3S_MASK;
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tmp_ccmr2 |= TIM_CCMR2_CC3S_OUT;
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/* Enable OC3 preload enable. */
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tmp_ccmr2 |= TIM_CCMR2_OC3PE;
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/* Disable OC3 fast mode. */
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tmp_ccmr2 &= ~TIM_CCMR2_OC3FE;
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/* Set OC3 mode to PWM1. */
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tmp_ccmr2 &= ~TIM_CCMR2_OC3M_MASK;
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tmp_ccmr2 |= TIM_CCMR2_OC3M_PWM1;
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/** Configure OC3. **/
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/* Set output polarity level, high. */
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tmp_ccer &= ~TIM_CCER_CC3P;
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/* Enable OC3 output */
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tmp_ccer |= TIM_CCER_CC3E;
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/* Set OC3 idle state to "set". (TIM1 and TIM8 only) */
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tmp_cr2 |= TIM_CR2_OIS3;
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/** Configure OC3N. **/
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/* Set output polarity level, high. (TIM1 and TIM8 only) */
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tmp_ccer &= ~TIM_CCER_CC3NP;
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/* Enable OC3N output. (TIM1 and TIM8 only) */
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tmp_ccer |= TIM_CCER_CC3NE;
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/* Set OC3N idle state to "set". (TIM1 and TIM8 only) */
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tmp_cr2 |= TIM_CR2_OIS3N;
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/** Set the capture compare value for OC3 **/
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TIM1_CCR3 = 300;
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/** Write register values **/
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TIM1_CR2 = tmp_cr2;
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TIM1_CCMR2 = tmp_ccmr2;
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TIM1_CCER = tmp_ccer;
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}
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/* Reenable outputs. */
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timer_enable_oc_output(TIM1, TIM_OC3);
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timer_enable_oc_output(TIM1, TIM_OC3N);
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/* ---- */
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/* ARR reload enable */
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TIM1_CR1 |= TIM_CR1_ARPE;
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timer_enable_preload(TIM1);
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/* Enable outputs in the break subsystem */
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TIM1_BDTR |= TIM_BDTR_MOE;
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/* Counter enable */
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TIM1_CR1 |= TIM_CR1_CEN;
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timer_enable_counter(TIM1);
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}
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int main(void)
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