lpc43xx: Convert register definitions to YAML
This commit is contained in:
Ben Gamari
committed by
Piotr Esden-Tempski
Piotr Esden-Tempski
parent
4fd218ad4c
commit
580be39e47
619
scripts/data/lpc43xx/i2s.yaml
Normal file
619
scripts/data/lpc43xx/i2s.yaml
Normal file
@@ -0,0 +1,619 @@
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!!omap
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- I2S0_DAO:
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fields: !!omap
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- WORDWIDTH:
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access: rw
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description: Selects the number of bytes in data
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lsb: 0
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reset_value: '1'
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width: 2
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- MONO:
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access: rw
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description: When 1, data is of monaural format. When 0, the data is in stereo
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format
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lsb: 2
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reset_value: '0'
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width: 1
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- STOP:
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access: rw
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description: When 1, disables accesses on FIFOs, places the transmit channel
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in mute mode
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lsb: 3
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reset_value: '0'
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width: 1
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- RESET:
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access: rw
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description: When 1, asynchronously resets the transmit channel and FIFO
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lsb: 4
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reset_value: '0'
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width: 1
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- WS_SEL:
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access: rw
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description: When 0, the interface is in master mode. When 1, the interface
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is in slave mode
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lsb: 5
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reset_value: '1'
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width: 1
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- WS_HALFPERIOD:
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access: rw
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description: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod
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= 31.
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lsb: 6
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reset_value: '0x1f'
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width: 9
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- MUTE:
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access: rw
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description: When 1, the transmit channel sends only zeroes
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lsb: 15
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reset_value: '1'
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width: 1
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- I2S1_DAO:
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fields: !!omap
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- WORDWIDTH:
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access: rw
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description: Selects the number of bytes in data
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lsb: 0
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reset_value: '1'
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width: 2
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- MONO:
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access: rw
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description: When 1, data is of monaural format. When 0, the data is in stereo
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format
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lsb: 2
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reset_value: '0'
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width: 1
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- STOP:
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access: rw
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description: When 1, disables accesses on FIFOs, places the transmit channel
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in mute mode
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lsb: 3
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reset_value: '0'
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width: 1
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- RESET:
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access: rw
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description: When 1, asynchronously resets the transmit channel and FIFO
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lsb: 4
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reset_value: '0'
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width: 1
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- WS_SEL:
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access: rw
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description: When 0, the interface is in master mode. When 1, the interface
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is in slave mode
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lsb: 5
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reset_value: '1'
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width: 1
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- WS_HALFPERIOD:
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access: rw
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description: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod
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= 31.
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lsb: 6
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reset_value: '0x1f'
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width: 9
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- MUTE:
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access: rw
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description: When 1, the transmit channel sends only zeroes
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lsb: 15
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reset_value: '1'
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width: 1
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- I2S0_DAI:
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fields: !!omap
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- WORDWIDTH:
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access: rw
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description: Selects the number of bytes in data
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lsb: 0
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reset_value: '1'
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width: 2
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- MONO:
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access: rw
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description: When 1, data is of monaural format. When 0, the data is in stereo
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format
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lsb: 2
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reset_value: '0'
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width: 1
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- STOP:
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access: rw
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description: When 1, disables accesses on FIFOs, places the transmit channel
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in mute mode
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lsb: 3
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reset_value: '0'
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width: 1
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- RESET:
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access: rw
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description: When 1, asynchronously resets the transmit channel and FIFO
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lsb: 4
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reset_value: '0'
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width: 1
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- WS_SEL:
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access: rw
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description: When 0, the interface is in master mode. When 1, the interface
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is in slave mode
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lsb: 5
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reset_value: '1'
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width: 1
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- WS_HALFPERIOD:
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access: rw
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description: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod
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= 31.
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lsb: 6
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reset_value: '0x1f'
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width: 9
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- MUTE:
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access: rw
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description: When 1, the transmit channel sends only zeroes
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lsb: 15
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reset_value: '1'
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width: 1
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- I2S1_DAI:
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fields: !!omap
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- WORDWIDTH:
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access: rw
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description: Selects the number of bytes in data
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lsb: 0
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reset_value: '1'
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width: 2
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- MONO:
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access: rw
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description: When 1, data is of monaural format. When 0, the data is in stereo
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format
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lsb: 2
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reset_value: '0'
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width: 1
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- STOP:
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access: rw
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description: When 1, disables accesses on FIFOs, places the transmit channel
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in mute mode
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lsb: 3
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reset_value: '0'
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width: 1
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- RESET:
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access: rw
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description: When 1, asynchronously resets the transmit channel and FIFO
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lsb: 4
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reset_value: '0'
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width: 1
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- WS_SEL:
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access: rw
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description: When 0, the interface is in master mode. When 1, the interface
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is in slave mode
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lsb: 5
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reset_value: '1'
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width: 1
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- WS_HALFPERIOD:
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access: rw
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description: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod
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= 31.
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lsb: 6
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reset_value: '0x1f'
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width: 9
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- MUTE:
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access: rw
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description: When 1, the transmit channel sends only zeroes
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lsb: 15
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reset_value: '1'
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width: 1
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- I2S0_TXFIFO:
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fields: !!omap
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- I2STXFIFO:
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access: w
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description: 8 x 32-bit transmit FIFO
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lsb: 0
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reset_value: '0'
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width: 32
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- I2S1_TXFIFO:
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fields: !!omap
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- I2STXFIFO:
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access: w
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description: 8 x 32-bit transmit FIFO
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lsb: 0
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reset_value: '0'
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width: 32
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- I2S0_RXFIFO:
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fields: !!omap
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- I2SRXFIFO:
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access: r
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description: 8 x 32-bit receive FIFO
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lsb: 0
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reset_value: '0'
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width: 32
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- I2S1_RXFIFO:
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fields: !!omap
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- I2SRXFIFO:
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access: r
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description: 8 x 32-bit receive FIFO
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lsb: 0
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reset_value: '0'
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width: 32
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- I2S0_STATE:
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fields: !!omap
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- IRQ:
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access: r
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description: This bit reflects the presence of Receive Interrupt or Transmit
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Interrupt
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lsb: 0
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reset_value: '1'
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width: 1
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- DMAREQ1:
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access: r
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description: This bit reflects the presence of Receive or Transmit DMA Request
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1
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lsb: 1
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reset_value: '1'
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width: 1
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- DMAREQ2:
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access: r
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description: This bit reflects the presence of Receive or Transmit DMA Request
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2
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lsb: 2
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reset_value: '1'
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width: 1
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- RX_LEVEL:
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access: r
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description: Reflects the current level of the Receive FIFO
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lsb: 8
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reset_value: '0'
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width: 4
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- TX_LEVEL:
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access: r
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description: Reflects the current level of the Transmit FIFO
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lsb: 16
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reset_value: '0'
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width: 4
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- I2S1_STATE:
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fields: !!omap
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- IRQ:
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access: r
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description: This bit reflects the presence of Receive Interrupt or Transmit
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Interrupt
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lsb: 0
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reset_value: '1'
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width: 1
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- DMAREQ1:
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access: r
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description: This bit reflects the presence of Receive or Transmit DMA Request
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1
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lsb: 1
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reset_value: '1'
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width: 1
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- DMAREQ2:
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access: r
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description: This bit reflects the presence of Receive or Transmit DMA Request
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2
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lsb: 2
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reset_value: '1'
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width: 1
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- RX_LEVEL:
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access: r
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description: Reflects the current level of the Receive FIFO
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lsb: 8
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reset_value: '0'
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width: 4
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- TX_LEVEL:
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access: r
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description: Reflects the current level of the Transmit FIFO
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lsb: 16
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reset_value: '0'
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width: 4
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- I2S0_DMA1:
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fields: !!omap
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- RX_DMA1_ENABLE:
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access: rw
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description: When 1, enables DMA1 for I2S receive
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lsb: 0
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reset_value: '0'
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width: 1
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- TX_DMA1_ENABLE:
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access: rw
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description: When 1, enables DMA1 for I2S transmit
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lsb: 1
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reset_value: '0'
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width: 1
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- RX_DEPTH_DMA1:
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access: rw
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description: Set the FIFO level that triggers a receive DMA request on DMA1
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lsb: 8
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reset_value: '0'
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width: 4
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- TX_DEPTH_DMA1:
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access: rw
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description: Set the FIFO level that triggers a transmit DMA request on DMA1
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lsb: 16
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reset_value: '0'
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width: 4
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- I2S1_DMA1:
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fields: !!omap
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- RX_DMA1_ENABLE:
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access: rw
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description: When 1, enables DMA1 for I2S receive
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lsb: 0
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reset_value: '0'
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width: 1
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- TX_DMA1_ENABLE:
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access: rw
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description: When 1, enables DMA1 for I2S transmit
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lsb: 1
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reset_value: '0'
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width: 1
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- RX_DEPTH_DMA1:
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access: rw
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description: Set the FIFO level that triggers a receive DMA request on DMA1
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lsb: 8
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reset_value: '0'
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width: 4
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- TX_DEPTH_DMA1:
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access: rw
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description: Set the FIFO level that triggers a transmit DMA request on DMA1
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lsb: 16
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reset_value: '0'
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width: 4
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- I2S0_DMA2:
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fields: !!omap
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- RX_DMA2_ENABLE:
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access: rw
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description: When 1, enables DMA2 for I2S receive
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lsb: 0
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reset_value: '0'
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width: 1
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- TX_DMA2_ENABLE:
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access: rw
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description: When 1, enables DMA2 for I2S transmit
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lsb: 1
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reset_value: '0'
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width: 1
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- RX_DEPTH_DMA2:
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access: rw
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description: Set the FIFO level that triggers a receive DMA request on DMA2
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lsb: 8
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reset_value: '0'
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width: 4
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- TX_DEPTH_DMA2:
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access: rw
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description: Set the FIFO level that triggers a transmit DMA request on DMA2
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lsb: 16
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reset_value: '0'
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width: 4
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- I2S1_DMA2:
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fields: !!omap
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- RX_DMA2_ENABLE:
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access: rw
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description: When 1, enables DMA2 for I2S receive
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lsb: 0
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reset_value: '0'
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width: 1
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- TX_DMA2_ENABLE:
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access: rw
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description: When 1, enables DMA2 for I2S transmit
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lsb: 1
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reset_value: '0'
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width: 1
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- RX_DEPTH_DMA2:
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access: rw
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description: Set the FIFO level that triggers a receive DMA request on DMA2
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lsb: 8
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reset_value: '0'
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width: 4
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- TX_DEPTH_DMA2:
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access: rw
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description: Set the FIFO level that triggers a transmit DMA request on DMA2
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lsb: 16
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reset_value: '0'
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width: 4
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- I2S0_IRQ:
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fields: !!omap
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- RX_IRQ_ENABLE:
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access: rw
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description: When 1, enables I2S receive interrupt
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lsb: 0
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reset_value: '0'
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width: 1
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- TX_IRQ_ENABLE:
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access: rw
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description: When 1, enables I2S transmit interrupt
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lsb: 1
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reset_value: '0'
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width: 1
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- RX_DEPTH_IRQ:
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access: rw
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description: Set the FIFO level on which to create an irq request.
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lsb: 8
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reset_value: '0'
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width: 4
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- TX_DEPTH_IRQ:
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access: rw
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description: Set the FIFO level on which to create an irq request.
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lsb: 16
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reset_value: '0'
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width: 4
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- I2S1_IRQ:
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fields: !!omap
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- RX_IRQ_ENABLE:
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access: rw
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description: When 1, enables I2S receive interrupt
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lsb: 0
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reset_value: '0'
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width: 1
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- TX_IRQ_ENABLE:
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access: rw
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description: When 1, enables I2S transmit interrupt
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lsb: 1
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reset_value: '0'
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width: 1
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- RX_DEPTH_IRQ:
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access: rw
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description: Set the FIFO level on which to create an irq request.
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lsb: 8
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reset_value: '0'
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width: 4
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- TX_DEPTH_IRQ:
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access: rw
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description: Set the FIFO level on which to create an irq request.
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lsb: 16
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reset_value: '0'
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width: 4
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- I2S0_TXRATE:
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fields: !!omap
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- Y_DIVIDER:
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access: rw
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description: I2S transmit MCLK rate denominator
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lsb: 0
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reset_value: '0'
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width: 8
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- X_DIVIDER:
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access: rw
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description: I2S transmit MCLK rate numerator
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lsb: 8
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reset_value: '0'
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width: 8
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- I2S1_TXRATE:
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fields: !!omap
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- Y_DIVIDER:
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access: rw
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description: I2S transmit MCLK rate denominator
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lsb: 0
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reset_value: '0'
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width: 8
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- X_DIVIDER:
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access: rw
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description: I2S transmit MCLK rate numerator
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lsb: 8
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reset_value: '0'
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width: 8
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- I2S0_RXRATE:
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fields: !!omap
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- Y_DIVIDER:
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access: rw
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description: I2S receive MCLK rate denominator
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lsb: 0
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reset_value: '0'
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width: 8
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- X_DIVIDER:
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access: rw
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description: I2S receive MCLK rate numerator
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lsb: 8
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reset_value: '0'
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width: 8
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- I2S1_RXRATE:
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fields: !!omap
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- Y_DIVIDER:
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access: rw
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description: I2S receive MCLK rate denominator
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lsb: 0
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reset_value: '0'
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width: 8
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- X_DIVIDER:
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access: rw
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description: I2S receive MCLK rate numerator
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lsb: 8
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reset_value: '0'
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width: 8
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- I2S0_TXBITRATE:
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fields: !!omap
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- TX_BITRATE:
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access: rw
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description: I2S transmit bit rate
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lsb: 0
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reset_value: '0'
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width: 6
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- I2S1_TXBITRATE:
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fields: !!omap
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- TX_BITRATE:
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access: rw
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description: I2S transmit bit rate
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lsb: 0
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reset_value: '0'
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width: 6
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- I2S0_RXBITRATE:
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fields: !!omap
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||||
- RX_BITRATE:
|
||||
access: rw
|
||||
description: I2S receive bit rate
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 6
|
||||
- I2S1_RXBITRATE:
|
||||
fields: !!omap
|
||||
- RX_BITRATE:
|
||||
access: rw
|
||||
description: I2S receive bit rate
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 6
|
||||
- I2S0_TXMODE:
|
||||
fields: !!omap
|
||||
- TXCLKSEL:
|
||||
access: rw
|
||||
description: Clock source selection for the transmit bit clock divider
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 2
|
||||
- TX4PIN:
|
||||
access: rw
|
||||
description: Transmit 4-pin mode selection
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TXMCENA:
|
||||
access: rw
|
||||
description: Enable for the TX_MCLK output
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- I2S1_TXMODE:
|
||||
fields: !!omap
|
||||
- TXCLKSEL:
|
||||
access: rw
|
||||
description: Clock source selection for the transmit bit clock divider
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 2
|
||||
- TX4PIN:
|
||||
access: rw
|
||||
description: Transmit 4-pin mode selection
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- TXMCENA:
|
||||
access: rw
|
||||
description: Enable for the TX_MCLK output
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- I2S0_RXMODE:
|
||||
fields: !!omap
|
||||
- RXCLKSEL:
|
||||
access: rw
|
||||
description: Clock source selection for the receive bit clock divider
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 2
|
||||
- RX4PIN:
|
||||
access: rw
|
||||
description: Receive 4-pin mode selection
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RXMCENA:
|
||||
access: rw
|
||||
description: Enable for the RX_MCLK output
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- I2S1_RXMODE:
|
||||
fields: !!omap
|
||||
- RXCLKSEL:
|
||||
access: rw
|
||||
description: Clock source selection for the receive bit clock divider
|
||||
lsb: 0
|
||||
reset_value: '0'
|
||||
width: 2
|
||||
- RX4PIN:
|
||||
access: rw
|
||||
description: Receive 4-pin mode selection
|
||||
lsb: 2
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
- RXMCENA:
|
||||
access: rw
|
||||
description: Enable for the RX_MCLK output
|
||||
lsb: 3
|
||||
reset_value: '0'
|
||||
width: 1
|
||||
Reference in New Issue
Block a user