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stm32f4: rcc: support new plls for new f4 parts

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Revise the PLL inits to support new and old PLL configurations,
particularly to support F4x9 devices.

Signed-off-by: Karl Palsson <karlp@tweak.net.au>
This commit is contained in:
Chuck McManis
2016-07-28 20:37:58 -07:00
committed by Karl Palsson
parent 095ed8511a
commit 57c2b00a69
2 changed files with 105 additions and 30 deletions
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29
include/libopencm3/stm32/f4/rcc.h
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@@ -563,6 +563,14 @@
/* RCC_PLLSAICFGR[18:16]: PLLSAIP */
#define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16
#define RCC_PLLSAICFGR_PLLSAIP_MASK 0x3
/** @defgroup rcc_pllsaicfgr_pllsaip PLLSAICFGR PLLSAIP values
@ingroup rcc_defines
@{*/
#define RCC_PLLSAICFGR_PLLSAIP_DIV2 0x0
#define RCC_PLLSAICFGR_PLLSAIP_DIV4 0x1
#define RCC_PLLSAICFGR_PLLSAIP_DIV6 0x2
#define RCC_PLLSAICFGR_PLLSAIP_DIV8 0x3
/**@}*/
/* RCC_PLLSAICFGR[14:6]: PLLSAIN */
#define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6
@@ -611,22 +619,6 @@ static inline bool rcc_pllsai_ready(void)
return (RCC_CR & RCC_CR_PLLSAIRDY) != 0;
}
/* pllsain=49..432, pllsaiq=2..15, pllsair=2..7 */
static inline void rcc_pllsai_config(uint16_t pllsain,
uint16_t pllsaiq,
uint16_t pllsair)
{
RCC_PLLSAICFGR = (((pllsain & 0x1ff) << 6) |
((pllsaiq & 0xF) << 24) |
((pllsair & 0x7) << 28));
}
static inline void rcc_ltdc_set_clock_divr(uint8_t pllsaidivr)
{
RCC_DCKCFGR = (((RCC_DCKCFGR &
~RCC_DCKCFGR_PLLSAIDIVR_MASK) |
((pllsaidivr & 0x3) << 16)));
}
/* --- Variable definitions ------------------------------------------------ */
extern uint32_t rcc_ahb_frequency;
@@ -648,6 +640,7 @@ struct rcc_clock_scale {
uint16_t plln;
uint8_t pllp;
uint8_t pllq;
uint8_t pllr;
uint32_t flash_config;
uint8_t hpre;
uint8_t ppre1;
@@ -959,9 +952,9 @@ void rcc_set_ppre1(uint32_t ppre1);
void rcc_set_hpre(uint32_t hpre);
void rcc_set_rtcpre(uint32_t rtcpre);
void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp,
uint32_t pllq);
uint32_t pllq, uint32_t pllr);
void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp,
uint32_t pllq);
uint32_t pllq, uint32_t pllr);
uint32_t rcc_system_clock_source(void);
void rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock);