diff --git a/include/libopencm3/stm32/g0/irq.json b/include/libopencm3/stm32/g0/irq.json
index aa43cbc1..7a7fc52b 100644
--- a/include/libopencm3/stm32/g0/irq.json
+++ b/include/libopencm3/stm32/g0/irq.json
@@ -16,20 +16,20 @@
         "tim1_brk_up_trg_com", 
         "tim1_cc",
         "tim2", 
-        "tim3", 
+        "tim34",
         "tim6_dac_lptim1", 
         "tim7_lptim2",
         "tim14", 
         "tim15", 
-        "tim16",
-        "tim17", 
+        "tim16_fdcan_it0",
+        "tim17_fdcan_it1",
         "i2c1", 
-        "i2c2", 
+        "i2c23",
         "spi1", 
-        "spi2", 
+        "spi23",
         "usart1", 
-        "usart2", 
-        "usart3_usart4_lpuart1",
+        "usart2_lpuart2",
+        "usart3456_lpuart1",
         "cec", 
         "aes_rng"
     ], 
diff --git a/include/libopencm3/stm32/g0/memorymap.h b/include/libopencm3/stm32/g0/memorymap.h
index 1bf07989..40845624 100644
--- a/include/libopencm3/stm32/g0/memorymap.h
+++ b/include/libopencm3/stm32/g0/memorymap.h
@@ -30,6 +30,7 @@
 /* APB */
 #define TIM2_BASE			(PERIPH_BASE_APB + 0x0000)
 #define TIM3_BASE			(PERIPH_BASE_APB + 0x0400)
+#define TIM4_BASE			(PERIPH_BASE_APB + 0x0800)
 #define TIM6_BASE			(PERIPH_BASE_APB + 0x1000)
 #define TIM7_BASE			(PERIPH_BASE_APB + 0x1400)
 #define TIM14_BASE			(PERIPH_BASE_APB + 0x2000)
@@ -37,28 +38,40 @@
 #define WWDG_BASE			(PERIPH_BASE_APB + 0x2c00)
 #define IWDG_BASE			(PERIPH_BASE_APB + 0x3000)
 #define SPI2_BASE			(PERIPH_BASE_APB + 0x3800)
+#define SPI3_BASE			(PERIPH_BASE_APB + 0x3c00)
 #define USART2_BASE			(PERIPH_BASE_APB + 0x4400)
 #define USART3_BASE			(PERIPH_BASE_APB + 0x4800)
 #define USART4_BASE			(PERIPH_BASE_APB + 0x4C00)
+#define USART5_BASE			(PERIPH_BASE_APB + 0x5000)
 #define I2C1_BASE			(PERIPH_BASE_APB + 0x5400)
 #define I2C2_BASE			(PERIPH_BASE_APB + 0x5800)
+#define USB_BASE			(PERIPH_BASE_APB + 0x5c00)
+#define FDCAN1_BASE			(PERIPH_BASE_APB + 0x6400)
+#define FDCAN2_BASE			(PERIPH_BASE_APB + 0x6800)
+#define CRS_BASE			(PERIPH_BASE_APB + 0x6c00)
 #define POWER_CONTROL_BASE		(PERIPH_BASE_APB + 0x7000)
 #define DAC_BASE			(PERIPH_BASE_APB + 0x7400)
 #define CEC_BASE			(PERIPH_BASE_APB + 0x7800)
 #define LPTIM1_BASE			(PERIPH_BASE_APB + 0x7c00)
 #define LPUART1_BASE			(PERIPH_BASE_APB + 0x8000)
+#define LPUART2_BASE			(PERIPH_BASE_APB + 0x8400)
+#define I2C3_BASE			(PERIPH_BASE_APB + 0x8800)
 #define LPTIM2_BASE			(PERIPH_BASE_APB + 0x9400)
+#define USB_RAM1_BASE			(PERIPH_BASE_APB + 0x9800)
+#define USB_RAM2_BASE			(PERIPH_BASE_APB + 0x9c00)
 #define UCPD1_BASE			(PERIPH_BASE_APB + 0xA000)
 #define UCPD2_BASE			(PERIPH_BASE_APB + 0xA400)
 #define TAMP_BASE			(PERIPH_BASE_APB + 0xB000)
+#define FDCANMSG_BASE			(PERIPH_BASE_APB + 0xB400)
 #define SYSCFG_BASE			(PERIPH_BASE_APB + 0x10000)
-#define VREFBUF_BASE		(PERIPH_BASE_APB + 0x10030)
-#define SYSCFG_ITLINE_BASE	(PERIPH_BASE_APB + 0x10080)
+#define VREFBUF_BASE			(PERIPH_BASE_APB + 0x10030)
+#define SYSCFG_ITLINE_BASE		(PERIPH_BASE_APB + 0x10080)
 #define COMP_BASE			(PERIPH_BASE_APB + 0x10200)
 #define ADC1_BASE			(PERIPH_BASE_APB + 0x12400)
 #define TIM1_BASE			(PERIPH_BASE_APB + 0x12C00)
 #define SPI1_BASE			(PERIPH_BASE_APB + 0x13000)
 #define USART1_BASE			(PERIPH_BASE_APB + 0x13800)
+#define USART6_BASE			(PERIPH_BASE_APB + 0x13c00)
 #define TIM15_BASE			(PERIPH_BASE_APB + 0x14000)
 #define TIM16_BASE			(PERIPH_BASE_APB + 0x14400)
 #define TIM17_BASE			(PERIPH_BASE_APB + 0x14800)
@@ -66,6 +79,7 @@
 
 /* AHB */
 #define DMA1_BASE			(PERIPH_BASE_AHB + 0x00000)
+#define DMA2_BASE			(PERIPH_BASE_AHB + 0x00400)
 #define DMAMUX_BASE			(PERIPH_BASE_AHB + 0x00800)
 #define RCC_BASE			(PERIPH_BASE_AHB + 0x01000)
 #define EXTI_BASE			(PERIPH_BASE_AHB + 0x01800)