EMTime/libopencm3
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

swm050: new MCU family

Browse Source 
SWM050 is a series of MCU made by Foshan Synwit Tech. It contains a
Cortex-M0 CPU core, 8KiB of Flash and 1KiB of SRAM. The only peripherals
are GPIO, Timer and WDT. There's only two parts in this series, with
either TSSOP-8 or SSOP-16 packages.

This commit introduces the interrupt vector and GPIO support for them.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
This commit is contained in:
Icenowy Zheng
2019-02-19 01:25:12 +08:00
committed by Karl Palsson
parent a652856533
commit 54eff24e7c
10 changed files with 405 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
include/libopencmsis/dispatch/irqhandlers.h
View File

@@ -59,6 +59,8 @@
/* Yes, we use the same interrupt table for both LM3S and LM4F */
# include <libopencmsis/lm3s/irqhandlers.h>
#elif defined(SWM050)
# include <libopencmsis/swm050/irqhandlers.h>
#else
# warning"no chipset defined; user interrupts are not redirected"

22
include/libopencmsis/swm050/irqhandlers.h Normal file
View File

@@ -0,0 +1,22 @@
/* This file is part of the libopencm3 project.
*
* It was generated by the irq2nvic_h script.
*
* These definitions bend every interrupt handler that is defined CMSIS style
* to the weak symbol exported by libopencm3.
*/
#define TIMER_SE0_IRQHandler timer_se0_isr
#define TIMER_SE1_IRQHandler timer_se1_isr
#define WDT_IRQHandler wdt_isr
#define CP_IRQHandler cp_isr
#define GPIOA0_IRQHandler gpioa0_isr
#define GPIOA1_IRQHandler gpioa1_isr
#define GPIOA2_IRQHandler gpioa2_isr
#define GPIOA3_IRQHandler gpioa3_isr
#define GPIOA4_IRQHandler gpioa4_isr
#define GPIOA5_IRQHandler gpioa5_isr
#define GPIOA6_IRQHandler gpioa6_isr
#define GPIOA7_IRQHandler gpioa7_isr
#define GPIOA8_IRQHandler gpioa8_isr
#define GPIOA9_IRQHandler gpioa9_isr