stm32f09: add register definitions for USART5..8
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@@ -205,6 +205,9 @@ Control</b>
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#define RCC_APB2RSTR_SPI1RST (1 << 12)
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#define RCC_APB2RSTR_TIM1RST (1 << 11)
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#define RCC_APB2RSTR_ADCRST (1 << 9)
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#define RCC_APB2RSTR_USART8RST (1 << 7)
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#define RCC_APB2RSTR_USART7RST (1 << 6)
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#define RCC_APB2RSTR_USART6RST (1 << 5)
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#define RCC_APB2RSTR_SYSCFGRST (1 << 0)
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/* --- RCC_APB1RSTR values ------------------------------------------------- */
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@@ -217,6 +220,7 @@ Control</b>
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#define RCC_APB1RSTR_USBRST (1 << 23)
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#define RCC_APB1RSTR_I2C2RST (1 << 22)
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#define RCC_APB1RSTR_I2C1RST (1 << 21)
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#define RCC_APB1RSTR_USART5RST (1 << 20)
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#define RCC_APB1RSTR_USART4RST (1 << 19)
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#define RCC_APB1RSTR_USART3RST (1 << 18)
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#define RCC_APB1RSTR_USART2RST (1 << 17)
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@@ -252,6 +256,9 @@ Control</b>
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#define RCC_APB2ENR_SPI1EN (1 << 12)
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#define RCC_APB2ENR_TIM1EN (1 << 11)
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#define RCC_APB2ENR_ADCEN (1 << 9)
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#define RCC_APB2ENR_USART8EN (1 << 7)
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#define RCC_APB2ENR_USART7EN (1 << 6)
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#define RCC_APB2ENR_USART6EN (1 << 5)
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#define RCC_APB2ENR_SYSCFGCOMPEN (1 << 0)
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/* --- RCC_APB1ENR values -------------------------------------------------- */
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@@ -264,6 +271,7 @@ Control</b>
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#define RCC_APB1ENR_USBEN (1 << 23)
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#define RCC_APB1ENR_I2C2EN (1 << 22)
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#define RCC_APB1ENR_I2C1EN (1 << 21)
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#define RCC_APB1ENR_USART5EN (1 << 20)
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#define RCC_APB1ENR_USART4EN (1 << 19)
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#define RCC_APB1ENR_USART3EN (1 << 18)
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#define RCC_APB1ENR_USART2EN (1 << 17)
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@@ -418,6 +426,9 @@ enum rcc_periph_clken {
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/* APB2 peripherals */
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RCC_SYSCFG_COMP = _REG_BIT(0x18, 0),
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RCC_USART6 = _REG_BIT(0x18, 5),
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RCC_USART7 = _REG_BIT(0x18, 6),
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RCC_USART8 = _REG_BIT(0x18, 7),
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RCC_ADC = _REG_BIT(0x18, 9),
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RCC_ADC1 = _REG_BIT(0x18, 9), /* Compatibility alias */
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RCC_TIM1 = _REG_BIT(0x18, 11),
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@@ -439,6 +450,7 @@ enum rcc_periph_clken {
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RCC_USART2 = _REG_BIT(0x1C, 17),
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RCC_USART3 = _REG_BIT(0x1C, 18),
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RCC_USART4 = _REG_BIT(0x1C, 19),
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RCC_USART5 = _REG_BIT(0x1C, 20),
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RCC_I2C1 = _REG_BIT(0x1C, 21),
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RCC_I2C2 = _REG_BIT(0x1C, 22),
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RCC_USB = _REG_BIT(0x1C, 23),
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