STM32F1xx: Changed markup to get more control over documentation, each
file having its own group module rather than using @file. No code changes except for the following: gpio: Added function to map the eventout signal plus two Remap functions dma: Prevent changing base addresses while channel enabled (see datasheet) pwr: Added pwr.c (new file) timer: Removed the last function that I introduced recently; there is already an equivalent function present. Changed some parameter names for consistency.
This commit is contained in:
Ken Sarkies
@@ -1,4 +1,4 @@
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/** @file
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/** @defgroup STM32F1xx-rcc-file RCC
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@ingroup STM32F1xx
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@@ -10,25 +10,26 @@
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@author @htmlonly © @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
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@author @htmlonly © @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
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@date 18 May 2012
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@date 18 August 2012
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This library supports the Reset and Clock
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Control System in the STM32F1xx series of ARM Cortex Microcontrollers
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by ST Microelectronics.
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This library supports the Reset and Clock Control System in the STM32F1xx
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series of ARM Cortex Microcontrollers by ST Microelectronics.
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@note Full support for connection line devices is not yet provided.
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Clock settings and resets for many peripherals are given here rather than in the
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peripheral library.
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corresponding peripheral library.
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The library also provides a number of common configurations for the processor
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system clock. Not all possible configurations are given here.
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@bugs None known
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system clock. Not all possible configurations are included.
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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*
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* This library is free software: you can redistribute it and/or modify
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@@ -45,6 +46,7 @@ LGPL License Terms @ref lgpl_license
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#include <libopencm3/stm32/f1/rcc.h>
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#include <libopencm3/stm32/f1/flash.h>
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@@ -54,12 +56,12 @@ u32 rcc_ppre1_frequency = 8000000;
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/** Default ppre2 peripheral clock frequency after reset. */
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u32 rcc_ppre2_frequency = 8000000;
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//-----------------------------------------------------------------------------
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/** @brief RCC Clear the Oscillator Ready Interrupt
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/*-----------------------------------------------------------------------------*/
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/** @brief RCC Clear the Oscillator Ready Interrupt Flag
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Clear the interrupt flag that was set when a clock oscillator became ready to use.
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@param[in] enum ::osc_t. Oscillator ID
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@param[in] osc enum ::osc_t. Oscillator ID
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*/
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void rcc_osc_ready_int_clear(osc_t osc)
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@@ -83,6 +85,12 @@ void rcc_osc_ready_int_clear(osc_t osc)
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}
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief RCC Enable the Oscillator Ready Interrupt
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@param[in] osc enum ::osc_t. Oscillator ID
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*/
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void rcc_osc_ready_int_enable(osc_t osc)
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{
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switch (osc) {
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@@ -104,6 +112,12 @@ void rcc_osc_ready_int_enable(osc_t osc)
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}
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief RCC Disable the Oscillator Ready Interrupt
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@param[in] osc enum ::osc_t. Oscillator ID
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*/
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void rcc_osc_ready_int_disable(osc_t osc)
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{
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switch (osc) {
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@@ -125,6 +139,13 @@ void rcc_osc_ready_int_disable(osc_t osc)
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}
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief RCC Read the Oscillator Ready Interrupt Flag
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@param[in] osc enum ::osc_t. Oscillator ID
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@returns int. Boolean value for flag set.
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*/
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int rcc_osc_ready_int_flag(osc_t osc)
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{
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switch (osc) {
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@@ -149,16 +170,33 @@ int rcc_osc_ready_int_flag(osc_t osc)
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return -1;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief RCC Clear the Clock Security System Interrupt Flag
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*/
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void rcc_css_int_clear(void)
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{
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RCC_CIR |= RCC_CIR_CSSC;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief RCC Read the Clock Security System Interrupt Flag
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@returns int. Boolean value for flag set.
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*/
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int rcc_css_int_flag(void)
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{
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return ((RCC_CIR & RCC_CIR_CSSF) != 0);
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief RCC Wait for Oscillator Ready.
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@param[in] osc enum ::osc_t. Oscillator ID
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*/
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void rcc_wait_for_osc_ready(osc_t osc)
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{
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switch (osc) {
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@@ -180,6 +218,20 @@ void rcc_wait_for_osc_ready(osc_t osc)
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}
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief RCC Turn on an Oscillator.
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Enable an oscillator and power on. Each oscillator requires an amount of time to
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settle to a usable state. Refer to datasheets for time delay information. A status
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flag is available to indicate when the oscillator becomes ready (see
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@ref rcc_osc_ready_int_flag and @ref rcc_wait_for_osc_ready).
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@note The LSE clock is in the backup domain and cannot be enabled until the
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backup domain write protection has been removed (see @ref pwr_disable_backup_domain_write_protect).
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@param[in] osc enum ::osc_t. Oscillator ID
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*/
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void rcc_osc_on(osc_t osc)
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{
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switch (osc) {
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@@ -201,6 +253,20 @@ void rcc_osc_on(osc_t osc)
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}
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief RCC Turn off an Oscillator.
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Disable an oscillator and power off.
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@note An oscillator cannot be turned off if it is selected as the system clock.
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@note The LSE clock is in the backup domain and cannot be disabled until the
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backup domain write protection has been removed (see
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@ref pwr_disable_backup_domain_write_protect) or the backup domain has been
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(see reset @ref rcc_backupdomain_reset).
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@param[in] osc enum ::osc_t. Oscillator ID
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*/
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void rcc_osc_off(osc_t osc)
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{
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switch (osc) {
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@@ -222,16 +288,39 @@ void rcc_osc_off(osc_t osc)
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}
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief RCC Enable the Clock Security System.
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*/
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void rcc_css_enable(void)
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{
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RCC_CR |= RCC_CR_CSSON;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief RCC Disable the Clock Security System.
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*/
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void rcc_css_disable(void)
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{
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RCC_CR &= ~RCC_CR_CSSON;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief RCC Enable Bypass.
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Enable an external clock to bypass the internal clock (high speed and low speed
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clocks only). The external clock must be enabled (see @ref rcc_osc_on)
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and the internal clock must be disabled (see @ref rcc_osc_off) for this to have effect.
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@note The LSE clock is in the backup domain and cannot be bypassed until the
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backup domain write protection has been removed (see @ref pwr_disable_backup_domain_write_protect).
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@param[in] osc enum ::osc_t. Oscillator ID. Only HSE and LSE have effect.
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*/
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void rcc_osc_bypass_enable(osc_t osc)
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{
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switch (osc) {
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@@ -249,6 +338,19 @@ void rcc_osc_bypass_enable(osc_t osc)
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}
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief RCC Disable Bypass.
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Re-enable the internal clock (high speed and low speed clocks only). The internal
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clock must be disabled (see @ref rcc_osc_off) for this to have effect.
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@note The LSE clock is in the backup domain and cannot have bypass removed until the
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backup domain write protection has been removed (see @ref pwr_disable_backup_domain_write_protect)
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or the backup domain has been reset (see @ref rcc_backupdomain_reset).
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@param[in] osc enum ::osc_t. Oscillator ID. Only HSE and LSE have effect.
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*/
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void rcc_osc_bypass_disable(osc_t osc)
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{
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switch (osc) {
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@@ -266,18 +368,20 @@ void rcc_osc_bypass_disable(osc_t osc)
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}
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}
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//-----------------------------------------------------------------------------
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/** @brief RCC Enable a peripheral clock.
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/*-----------------------------------------------------------------------------*/
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/** @brief RCC Enable Peripheral Clocks.
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Enable the clock on a particular peripheral. Several peripherals could be
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enabled simultaneously if they are controlled by the same register.
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Enable the clock on particular peripherals. There are three registers
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involved, each one controlling the enabling of clocks associated with the AHB,
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APB1 and APB2 respectively. Several peripherals could be
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enabled simultaneously <em>only if they are controlled by the same register</em>.
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@param[in] Unsigned int32 *reg. Pointer to a Clock Enable Register
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(either RCC_AHBENR, RCC_APB1RENR or RCC_APB2RENR)
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@param[in] Unsigned int32 en. OR of all enables to be set
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@param[in] *reg Unsigned int32. Pointer to a Clock Enable Register
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(either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
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@param[in] en Unsigned int32. Logical OR of all enables to be set
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@li If register is RCC_AHBER, from @ref rcc_ahbenr_en
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@li If register is RCC_APB1RENR, from @ref rcc_apb1enr_en
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@li If register is RCC_APB2RENR, from @ref rcc_apb2enr_en
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@li If register is RCC_APB1ENR, from @ref rcc_apb1enr_en
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@li If register is RCC_APB2ENR, from @ref rcc_apb2enr_en
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*/
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void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en)
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@@ -285,21 +389,75 @@ void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en)
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*reg |= en;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief RCC Disable Peripheral Clocks.
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Enable the clock on particular peripherals. There are three registers
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involved, each one controlling the enabling of clocks associated with the AHB,
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APB1 and APB2 respectively. Several peripherals could be
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disabled simultaneously <em>only if they are controlled by the same register</em>.
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@param[in] *reg Unsigned int32. Pointer to a Clock Enable Register
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(either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
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@param[in] en Unsigned int32. Logical OR of all enables to be used for disabling.
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@li If register is RCC_AHBER, from @ref rcc_ahbenr_en
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@li If register is RCC_APB1ENR, from @ref rcc_apb1enr_en
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@li If register is RCC_APB2ENR, from @ref rcc_apb2enr_en
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*/
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void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en)
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{
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*reg &= ~en;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief RCC Reset Peripherals.
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Reset particular peripherals. There are three registers
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involved, each one controlling reset of peripherals associated with the AHB,
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APB1 and APB2 respectively. Several peripherals could be reset simultaneously
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<em>only if they are controlled by the same register</em>.
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@param[in] *reg Unsigned int32. Pointer to a Reset Register
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(either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
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@param[in] reset Unsigned int32. Logical OR of all resets.
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@li If register is RCC_AHBRSTR, from @ref rcc_ahbrstr_rst
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@li If register is RCC_APB1RSTR, from @ref rcc_apb1rstr_rst
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@li If register is RCC_APB2RSTR, from @ref rcc_apb2rstr_rst
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*/
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void rcc_peripheral_reset(volatile u32 *reg, u32 reset)
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{
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*reg |= reset;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief RCC Remove Reset on Peripherals.
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Remove the reset on particular peripherals. There are three registers
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involved, each one controlling reset of peripherals associated with the AHB,
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APB1 and APB2 respectively. Several peripherals could have the reset removed
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simultaneously <em>only if they are controlled by the same register</em>.
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@param[in] *reg Unsigned int32. Pointer to a Reset Register
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(either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
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@param[in] clear_reset Unsigned int32. Logical OR of all resets to be removed:
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@li If register is RCC_AHBRSTR, from @ref rcc_ahbrstr_rst
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@li If register is RCC_APB1RSTR, from @ref rcc_apb1rstr_rst
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@li If register is RCC_APB2RSTR, from @ref rcc_apb2rstr_rst
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*/
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void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset)
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{
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*reg &= ~clear_reset;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief RCC Set the Source for the System Clock.
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@param[in] clk Unsigned int32. System Clock Selection @ref rcc_cfgr_scs
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*/
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void rcc_set_sysclk_source(u32 clk)
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{
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u32 reg32;
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@@ -309,6 +467,14 @@ void rcc_set_sysclk_source(u32 clk)
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RCC_CFGR = (reg32 | clk);
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}
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|
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/*-----------------------------------------------------------------------------*/
|
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/** @brief RCC Set the PLL Multiplication Factor.
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@note This only has effect when the PLL is disabled.
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@param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pmf
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*/
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void rcc_set_pll_multiplication_factor(u32 mul)
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{
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u32 reg32;
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@@ -318,6 +484,14 @@ void rcc_set_pll_multiplication_factor(u32 mul)
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RCC_CFGR = (reg32 | (mul << 18));
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}
|
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|
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/*-----------------------------------------------------------------------------*/
|
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/** @brief RCC Set the PLL Clock Source.
|
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|
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@note This only has effect when the PLL is disabled.
|
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|
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@param[in] pllsrc Unsigned int32. PLL clock source @ref rcc_cfgr_pcs
|
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*/
|
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void rcc_set_pll_source(u32 pllsrc)
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{
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u32 reg32;
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@@ -327,6 +501,14 @@ void rcc_set_pll_source(u32 pllsrc)
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RCC_CFGR = (reg32 | (pllsrc << 16));
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}
|
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|
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/*-----------------------------------------------------------------------------*/
|
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/** @brief RCC Set the HSE Frequency Divider used as PLL Clock Source.
|
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|
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@note This only has effect when the PLL is disabled.
|
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|
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@param[in] pllxtpre Unsigned int32. HSE division factor @ref rcc_cfgr_hsepre
|
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*/
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void rcc_set_pllxtpre(u32 pllxtpre)
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{
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u32 reg32;
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@@ -336,6 +518,14 @@ void rcc_set_pllxtpre(u32 pllxtpre)
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RCC_CFGR = (reg32 | (pllxtpre << 17));
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}
|
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|
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/*-----------------------------------------------------------------------------*/
|
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/** @brief ADC Setup the A/D Clock
|
||||
|
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The ADC's have a common clock prescale setting.
|
||||
|
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@param[in] adcpre u32. Prescale divider taken from @ref rcc_cfgr_adcpre
|
||||
*/
|
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void rcc_set_adcpre(u32 adcpre)
|
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{
|
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u32 reg32;
|
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@@ -345,6 +535,12 @@ void rcc_set_adcpre(u32 adcpre)
|
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RCC_CFGR = (reg32 | (adcpre << 14));
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}
|
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|
||||
/*-----------------------------------------------------------------------------*/
|
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/** @brief RCC Set the APB2 Prescale Factor.
|
||||
|
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@param[in] ppre2 Unsigned int32. APB2 prescale factor @ref rcc_cfgr_apb2pre
|
||||
*/
|
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void rcc_set_ppre2(u32 ppre2)
|
||||
{
|
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u32 reg32;
|
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@@ -354,6 +550,14 @@ void rcc_set_ppre2(u32 ppre2)
|
||||
RCC_CFGR = (reg32 | (ppre2 << 11));
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief RCC Set the APB1 Prescale Factor.
|
||||
|
||||
@note The APB1 clock frequency must not exceed 36MHz.
|
||||
|
||||
@param[in] ppre1 Unsigned int32. APB1 prescale factor @ref rcc_cfgr_apb1pre
|
||||
*/
|
||||
|
||||
void rcc_set_ppre1(u32 ppre1)
|
||||
{
|
||||
u32 reg32;
|
||||
@@ -363,6 +567,12 @@ void rcc_set_ppre1(u32 ppre1)
|
||||
RCC_CFGR = (reg32 | (ppre1 << 8));
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief RCC Set the AHB Prescale Factor.
|
||||
|
||||
@param[in] hpre Unsigned int32. AHB prescale factor @ref rcc_cfgr_ahbpre
|
||||
*/
|
||||
|
||||
void rcc_set_hpre(u32 hpre)
|
||||
{
|
||||
u32 reg32;
|
||||
@@ -372,6 +582,17 @@ void rcc_set_hpre(u32 hpre)
|
||||
RCC_CFGR = (reg32 | (hpre << 4));
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief RCC Set the USB Prescale Factor.
|
||||
|
||||
The prescale factor can be set to 1 (no prescale) for use when the PLL clock is
|
||||
48MHz, or 1.5 to generate the 48MHz USB clock from a 64MHz PLL clock.
|
||||
|
||||
@note This bit cannot be reset while the USB clock is enabled.
|
||||
|
||||
@param[in] usbpre Unsigned int32. USB prescale factor @ref rcc_cfgr_usbpre
|
||||
*/
|
||||
|
||||
void rcc_set_usbpre(u32 usbpre)
|
||||
{
|
||||
u32 reg32;
|
||||
@@ -381,16 +602,31 @@ void rcc_set_usbpre(u32 usbpre)
|
||||
RCC_CFGR = (reg32 | (usbpre << 22));
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief RCC Get the System Clock Source.
|
||||
|
||||
@returns Unsigned int32. System clock source:
|
||||
@li 00 indicates HSE
|
||||
@li 01 indicates LSE
|
||||
@li 02 indicates PLL
|
||||
*/
|
||||
|
||||
u32 rcc_system_clock_source(void)
|
||||
{
|
||||
/* Return the clock source which is used as system clock. */
|
||||
return ((RCC_CFGR & 0x000c) >> 2);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/*
|
||||
* These functions are setting up the whole clock system for the most common
|
||||
* input clock and output clock configurations.
|
||||
*/
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief RCC Set System Clock PLL at 64MHz from HSI
|
||||
|
||||
*/
|
||||
|
||||
void rcc_clock_setup_in_hsi_out_64mhz(void)
|
||||
{
|
||||
/* Enable internal high-speed oscillator. */
|
||||
@@ -438,6 +674,11 @@ void rcc_clock_setup_in_hsi_out_64mhz(void)
|
||||
rcc_ppre2_frequency = 64000000;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief RCC Set System Clock PLL at 48MHz from HSI
|
||||
|
||||
*/
|
||||
|
||||
void rcc_clock_setup_in_hsi_out_48mhz(void)
|
||||
{
|
||||
/* Enable internal high-speed oscillator. */
|
||||
@@ -486,6 +727,11 @@ void rcc_clock_setup_in_hsi_out_48mhz(void)
|
||||
rcc_ppre2_frequency = 48000000;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief RCC Set System Clock PLL at 24MHz from HSI
|
||||
|
||||
*/
|
||||
|
||||
void rcc_clock_setup_in_hsi_out_24mhz(void) {
|
||||
/* Enable internal high-speed oscillator. */
|
||||
rcc_osc_on(HSI);
|
||||
@@ -532,6 +778,10 @@ void rcc_clock_setup_in_hsi_out_24mhz(void) {
|
||||
rcc_ppre2_frequency = 24000000;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief RCC Set System Clock PLL at 24MHz from HSE at 8MHz
|
||||
|
||||
*/
|
||||
|
||||
void rcc_clock_setup_in_hse_8mhz_out_24mhz(void)
|
||||
{
|
||||
@@ -591,6 +841,11 @@ void rcc_clock_setup_in_hse_8mhz_out_24mhz(void)
|
||||
rcc_ppre2_frequency = 24000000;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief RCC Set System Clock PLL at 72MHz from HSE at 8MHz
|
||||
|
||||
*/
|
||||
|
||||
void rcc_clock_setup_in_hse_8mhz_out_72mhz(void)
|
||||
{
|
||||
/* Enable internal high-speed oscillator. */
|
||||
@@ -649,6 +904,11 @@ void rcc_clock_setup_in_hse_8mhz_out_72mhz(void)
|
||||
rcc_ppre2_frequency = 72000000;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief RCC Set System Clock PLL at 24MHz from HSE at 12MHz
|
||||
|
||||
*/
|
||||
|
||||
void rcc_clock_setup_in_hse_12mhz_out_72mhz(void)
|
||||
{
|
||||
/* Enable internal high-speed oscillator. */
|
||||
@@ -707,6 +967,11 @@ void rcc_clock_setup_in_hse_12mhz_out_72mhz(void)
|
||||
rcc_ppre2_frequency = 72000000;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief RCC Set System Clock PLL at 24MHz from HSE at 16MHz
|
||||
|
||||
*/
|
||||
|
||||
void rcc_clock_setup_in_hse_16mhz_out_72mhz(void)
|
||||
{
|
||||
/* Enable internal high-speed oscillator. */
|
||||
@@ -765,6 +1030,12 @@ void rcc_clock_setup_in_hse_16mhz_out_72mhz(void)
|
||||
rcc_ppre2_frequency = 72000000;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief RCC Reset the backup domain
|
||||
|
||||
The backup domain register is reset to disable all controls.
|
||||
*/
|
||||
|
||||
void rcc_backupdomain_reset(void)
|
||||
{
|
||||
/* Set the backup domain software reset. */
|
||||
@@ -773,3 +1044,5 @@ void rcc_backupdomain_reset(void)
|
||||
/* Clear the backup domain software reset. */
|
||||
RCC_BDCR &= ~RCC_BDCR_BDRST;
|
||||
}
|
||||
/**@}*/
|
||||
|
||||
|
||||
Reference in New Issue
Block a user