STM32F1xx: Changed markup to get more control over documentation, each
file having its own group module rather than using @file. No code changes except for the following: gpio: Added function to map the eventout signal plus two Remap functions dma: Prevent changing base addresses while channel enabled (see datasheet) pwr: Added pwr.c (new file) timer: Removed the last function that I introduced recently; there is already an equivalent function present. Changed some parameter names for consistency.
This commit is contained in:
Ken Sarkies
@@ -1,3 +1,24 @@
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/** @defgroup STM32F1xx-dma-file DMA
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@ingroup STM32F1xx
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@brief <b>libopencm3 STM32F1xx DMA Controller</b>
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
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@date 18 August 2012
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This library supports the DMA
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Control System in the STM32F1xx series of ARM Cortex Microcontrollers
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by ST Microelectronics. It can provide for two DMA controllers,
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one with 7 channels and one with 5. Channels are hardware dedicated
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and each is shared with a number of different sources (only one can be
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used at a time, under the responsibility of the programmer).
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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@@ -17,8 +38,19 @@
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#include <libopencm3/stm32/f1/dma.h>
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/*-----------------------------------------------------------------------------*/
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/** @brief DMA Channel Reset
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The channel is disabled and configuration registers are cleared.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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*/
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void dma_channel_reset(u32 dma, u8 channel)
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{
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/* Disable channel. */
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@@ -35,18 +67,51 @@ void dma_channel_reset(u32 dma, u8 channel)
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DMA_IFCR(dma) |= DMA_IFCR_CIF(channel);
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief DMA Channel Enable Memory to Memory Transfers
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Memory to memory transfers do not require a trigger to activate each transfer.
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Transfers begin immediately the channel has been enabled, and proceed without
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intervention.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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*/
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void dma_enable_mem2mem_mode(u32 dma, u8 channel)
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{
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DMA_CCR(dma, channel) |= DMA_CCR_MEM2MEM;
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DMA_CCR(dma, channel) &= ~DMA_CCR_CIRC;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief DMA Channel Set Priority
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Channel Priority has four levels: low to very high. This has precedence over the
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hardware priority.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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@param[in] prio unsigned int32. Priority level @ref dma_ch_pri.
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*/
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void dma_set_priority(u32 dma, u8 channel, u32 prio)
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{
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DMA_CCR(dma, channel) &= ~(DMA_CCR_PL_MASK);
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DMA_CCR(dma, channel) |= prio;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief DMA Channel Set Memory Word Width
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Set the memory word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for
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alignment information if the source and destination widths do not match.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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@param[in] mem_size unsigned int32. Memory word width @ref dma_ch_memwidth.
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*/
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void dma_set_memory_size(u32 dma, u8 channel, u32 mem_size)
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{
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@@ -54,89 +119,249 @@ void dma_set_memory_size(u32 dma, u8 channel, u32 mem_size)
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DMA_CCR(dma, channel) |= mem_size;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief DMA Channel Set Peripheral Word Width
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Set the peripheral word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for
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alignment information if the source and destination widths do not match, or
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if the peripheral does not support byte or half-word writes.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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@param[in] peripheral_size unsigned int32. Peripheral word width @ref dma_ch_perwidth.
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*/
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void dma_set_peripheral_size(u32 dma, u8 channel, u32 peripheral_size)
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{
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DMA_CCR(dma, channel) &= ~(DMA_CCR_PSIZE_MASK);
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DMA_CCR(dma, channel) |= peripheral_size;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief DMA Channel Enable Memory Increment after Transfer
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Following each transfer the current memory address is incremented by
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1, 2 or 4 depending on the data size set in @ref dma_set_memory_size. The
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value held by the base memory address register is unchanged.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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*/
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void dma_enable_memory_increment_mode(u32 dma, u8 channel)
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{
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DMA_CCR(dma, channel) |= DMA_CCR_MINC;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief DMA Channel Disable Memory Increment after Transfer
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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*/
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void dma_enable_peripheral_increment_mode(u32 dma, u8 channel)
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{
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DMA_CCR(dma, channel) |= DMA_CCR_PINC;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief DMA Channel Enable Memory Circular Mode
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After the number of bytes/words to be transferred has been completed, the
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original transfer block size, memory and peripheral base addresses are
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reloaded and the process repeats.
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@note This cannot be used with memory to memory mode, which is explictly
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disabled here.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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*/
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void dma_enable_circular_mode(u32 dma, u8 channel)
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{
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DMA_CCR(dma, channel) |= DMA_CCR_CIRC;
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DMA_CCR(dma, channel) &= ~DMA_CCR_MEM2MEM;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief DMA Channel Enable Transfers from a Peripheral
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The data direction is set to read from a peripheral.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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*/
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void dma_set_read_from_peripheral(u32 dma, u8 channel)
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{
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DMA_CCR(dma, channel) &= ~DMA_CCR_DIR;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief DMA Channel Enable Transfers from Memory
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The data direction is set to read from memory.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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*/
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void dma_set_read_from_memory(u32 dma, u8 channel)
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{
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DMA_CCR(dma, channel) |= DMA_CCR_DIR;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief DMA Channel Enable Interrupt on Transfer Error
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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*/
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void dma_enable_transfer_error_interrupt(u32 dma, u8 channel)
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{
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DMA_CCR(dma, channel) |= DMA_CCR_TEIE;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief DMA Channel Disable Interrupt on Transfer Error
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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*/
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void dma_disable_transfer_error_interrupt(u32 dma, u8 channel)
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{
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DMA_CCR(dma, channel) &= ~DMA_CCR_TEIE;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief DMA Channel Enable Interrupt on Transfer Half Complete
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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*/
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void dma_enable_half_transfer_interrupt(u32 dma, u8 channel)
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{
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DMA_CCR(dma, channel) |= DMA_CCR_HTIE;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief DMA Channel Disable Interrupt on Transfer Half Complete
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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*/
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void dma_disable_half_transfer_interrupt(u32 dma, u8 channel)
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{
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DMA_CCR(dma, channel) &= ~DMA_CCR_HTIE;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief DMA Channel Enable Interrupt on Transfer Complete
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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*/
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void dma_enable_transfer_complete_interrupt(u32 dma, u8 channel)
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{
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DMA_CCR(dma, channel) |= DMA_CCR_TCIE;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief DMA Channel Disable Interrupt on Transfer Complete
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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*/
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void dma_disable_transfer_complete_interrupt(u32 dma, u8 channel)
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{
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DMA_CCR(dma, channel) &= ~DMA_CCR_TCIE;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief DMA Channel Enable
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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*/
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void dma_enable_channel(u32 dma, u8 channel)
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{
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DMA_CCR(dma, channel) |= DMA_CCR_EN;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief DMA Channel Disable
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@note The DMA channel registers retain their values when the channel is disabled.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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*/
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void dma_disable_channel(u32 dma, u8 channel)
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{
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DMA_CCR(dma, channel) &= ~DMA_CCR_EN;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief DMA Channel Set the Peripheral Address
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Set the address of the peripheral register to or from which data is to be transferred.
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Refer to the documentation for the specific peripheral.
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@note The DMA channel must be disabled before setting this address. This function
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has no effect if the channel is enabled.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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@param[in] address unsigned int32. Peripheral Address.
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*/
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void dma_set_peripheral_address(u32 dma, u8 channel, u32 address)
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{
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DMA_CPAR(dma, channel) = (u32) address;
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if (!(DMA_CCR(dma, channel) & DMA_CCR_EN))
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DMA_CPAR(dma, channel) = (u32) address;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief DMA Channel Set the Base Memory Address
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@note The DMA channel must be disabled before setting this address. This function
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has no effect if the channel is enabled.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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@param[in] address unsigned int32. Memory Initial Address.
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*/
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void dma_set_memory_address(u32 dma, u8 channel, u32 address)
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{
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DMA_CMAR(dma, channel) = (u32) address;
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if (!(DMA_CCR(dma, channel) & DMA_CCR_EN))
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DMA_CMAR(dma, channel) = (u32) address;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief DMA Channel Set the Transfer Block Size
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@note The DMA channel must be disabled before setting this count value. The count
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is not changed if the channel is enabled.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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@param[in] number unsigned int16. Number of data words to transfer (65535 maximum).
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*/
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void dma_set_number_of_data(u32 dma, u8 channel, u16 number)
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{
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DMA_CNDTR(dma, channel) = number;
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}
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/**@}*/
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