diff --git a/include/libopencm3/stm32/u5/gpio.h b/include/libopencm3/stm32/u5/gpio.h new file mode 100644 index 00000000..05ba8529 --- /dev/null +++ b/include/libopencm3/stm32/u5/gpio.h @@ -0,0 +1,60 @@ +/** @defgroup gpio_defines GPIO Defines + * + * @brief Defined Constants and Types for the STM32F0xx General Purpose I/O + * + * @ingroup STM32F0xx_defines + * + * @version 1.0.0 + * + * @date 1 July 2012 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_GPIO_H +#define LIBOPENCM3_GPIO_H + +#include + +/*****************************************************************************/ +/* Module definitions */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Register definitions */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Register values */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* API definitions */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* API Functions */ +/*****************************************************************************/ + +BEGIN_DECLS + +END_DECLS + +#endif diff --git a/include/libopencm3/stm32/u5/irq.json b/include/libopencm3/stm32/u5/irq.json new file mode 100644 index 00000000..199026fe --- /dev/null +++ b/include/libopencm3/stm32/u5/irq.json @@ -0,0 +1,148 @@ +{ + "irqs": [ + "wwdg", + "pvd_pvm", + "rtc", + "rtc_s", + "tamp", + "ramcfg", + "flash", + "flash_s", + "gtzc", + "rcc", + "rcc_s", + "exti0", + "exti1", + "exti2", + "exti3", + "exti4", + "exti5", + "exti6", + "exti7", + "exti8", + "exti9", + "exti10", + "exti11", + "exti12", + "exti13", + "exti14", + "exti15", + "iwdg", + "saes", + "gpdma1_ch0", + "gpdma1_ch1", + "gpdma1_ch2", + "gpdma1_ch3", + "gpdma1_ch4", + "gpdma1_ch5", + "gpdma1_ch6", + "gpdma1_ch7", + "adc12", + "dac1", + "fdcan1_it0", + "fdcan1_it1", + "tim1_brk", + "tim1_up", + "tim1_trg_com", + "tim1_cc", + "tim2", + "tim3", + "tim4", + "tim5", + "tim6", + "tim7", + "tim8_brk", + "tim8_up", + "tim8_trg_coml", + "tim8_cc", + "i2c1_ev", + "i2c1_er", + "i2c2_ev", + "i2c2_er", + "spi1", + "spi2", + "usart1", + "usart2", + "usart3", + "uart4", + "uart5", + "lpuart1", + "lptim1", + "lptim2", + "tim15", + "tim16", + "tim17", + "comp", + "usb", + "crs", + "fmc", + "octospi1", + "pwr_s3wu", + "sdmmc1", + "sdmmc2", + "gpdma1_ch8", + "gpdma1_ch9", + "gpdma1_ch10", + "gpdma1_ch11", + "gpdma1_ch12", + "gpdma1_ch13", + "gpdma1_ch14", + "gpdma1_ch15", + "i2c3_ev", + "i2c3_er", + "sai1", + "sai2", + "tsc", + "aes", + "rng", + "fpu", + "hash", + "pka", + "lptim3", + "spi3", + "i2c4_er", + "i2c4_ev", + "mdf1_flt0", + "mdf1_flt1", + "mdf1_flt2", + "mdf1_flt3", + "ucpd1", + "icache", + "otfdec1", + "otfdec2", + "lptim4", + "dcache1", + "adf1_flt0", + "adc4", + "lpdma1_ch0", + "lpdma1_ch1", + "lpdma1_ch2", + "lpdma1_ch3", + "dma2d", + "dcmi_pssi", + "octospi2", + "mdf1_flt4", + "mdf1_flt5", + "cordic", + "fmac", + "lsecss", + "usart6", + "i2c5_er", + "i2c5_ev", + "i2c6_er", + "i2c6_ev", + "hspi1", + "gpu2d_irq", + "gpu2d_irqsys", + "gfxmmu", + "lcd_tft", + "lcd_tft_err", + "dsihost", + "dcache2", + "gfxtim", + "jpeg" + ], + "partname_humanreadable": "STM32 u5 series", + "partname_doxygen": "STM32U5", + "includeguard": "LIBOPENCM3_STM32_U5_NVIC_H" +} diff --git a/include/libopencm3/stm32/u5/memorymap.h b/include/libopencm3/stm32/u5/memorymap.h new file mode 100644 index 00000000..2c5523fe --- /dev/null +++ b/include/libopencm3/stm32/u5/memorymap.h @@ -0,0 +1,226 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Frantisek Burian + * + * .. based on file from F4. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_MEMORYMAP_H +#define LIBOPENCM3_MEMORYMAP_H + +#include + +/* --- STM32 specific peripheral definitions ------------------------------- */ + +/* Memory map for all buses */ +#define FLASH_BASE (0x08000000U) + +/* Non-secure */ +#define PERIPH_BASE_NS (0x40000000U) + +/* Secure, non-secure callable*/ +#define PERIPH_BASE_SC (0x50000000U) + +#define PERIPH_BASE PERIPH_BASE_NS + +#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000000U) +#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x00012C00U) +#define PERIPH_BASE_APB3 (PERIPH_BASE + 0x06000400U) + +#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x00020000U) +#define PERIPH_BASE_AHB2 (PERIPH_BASE + 0x02020000U) +#define PERIPH_BASE_AHB3 (PERIPH_BASE + 0x06020000U) + +/* Register boundary addresses */ + +/* APB1 */ +#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000U) +#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400U) +#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800U) +#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0C00U) +#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000U) +#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400U) +/* PERIPH_BASE_APB1 + 0x1800 (0x4000 1800 - 0x4000 2BFF): Reserved */ +#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2C00U) +#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000U) +/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */ +#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800U) +/* PERIPH_BASE_APB1 + 0x3C00 (0x4000 3C00 - 0x4000 43FF): Reserved */ +#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400U) +#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800U) +#define USART4_BASE (PERIPH_BASE_APB1 + 0x4C00U) +#define USART5_BASE (PERIPH_BASE_APB1 + 0x5000U) +#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400U) +#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800U) +/* PERIPH_BASE_APB1 + 0x5C00 (0x4000 5C00 - 0x4000 5FFF): Reserved */ +#define CRS_BASE (PERIPH_BASE_APB1 + 0x6000U) +#define USART6_BASE (PERIPH_BASE_APB1 + 0x6400U) +/* PERIPH_BASE_APB1 + 0x6800 (0x4000 6800 - 0x4000 83FF): Reserved */ +#define I2C4_BASE (PERIPH_BASE_AHB1 + 0x8500U) +/* PERIPH_BASE_APB1 + 0x8800 (0x4000 8800 - 0x4000 93FF): Reserved */ +#define LPTIM2_BASE (PERIPH_BASE_AHB1 + 0x9400U) +#define I2C5_BASE (PERIPH_BASE_AHB1 + 0x9800U) +#define I2C6_BASE (PERIPH_BASE_AHB1 + 0x9C00U) +/* PERIPH_BASE_APB1 + 0xA000 (0x4000 A000 - 0x4000 A3FF): Reserved */ +#define FDCAN1_BASE (PERIPH_BASE_AHB1 + 0xA400U) +/* PERIPH_BASE_APB1 + 0xA800 (0x4000 A800 - 0x4000 ABFF): Reserved */ +#define FDCAN1_RAM_BASE (PERIPH_BASE_AHB1 + 0xAC00U) +/* PERIPH_BASE_APB1 + 0xB000 (0x4000 B000 - 0x4000 DBFF): Reserved */ +#define UCPD1_BASE (PERIPH_BASE_AHB1 + 0xDC00U) +/* PERIPH_BASE_APB1 + 0xE000 (0x4000 E000 - 0x4000 2BFF): Reserved */ + +/* APB2 */ +#define TIM1_BASE (PERIPH_BASE_APB2 + 0x0000U) +#define SPI1_BASE (PERIPH_BASE_APB2 + 0x0400U) +#define TIM8_BASE (PERIPH_BASE_APB2 + 0x0800U) +#define USART1_BASE (PERIPH_BASE_APB2 + 0x0C00U) +/* PERIPH_BASE_APB2 + 0x1000 (0x4001 3C00 - 0x4001 3FFF): Reserved */ +#define TIM15_BASE (PERIPH_BASE_APB2 + 0x1400U) +#define TIM16_BASE (PERIPH_BASE_APB2 + 0x1800U) +#define TIM17_BASE (PERIPH_BASE_APB2 + 0x1C00U) +/* PERIPH_BASE_APB2 + 0x2000 (0x4001 4C00 - 0x4001 53FF): Reserved */ +#define SAI1_BASE (PERIPH_BASE_APB2 + 0x2800U) +#define SAI2_BASE (PERIPH_BASE_APB2 + 0x2C00U) +/* PERIPH_BASE_APB2 + 0x3000 (0x4001 5C00 - 0x4001 5FFF): Reserved */ +#define USB_BASE (PERIPH_BASE_APB2 + 0x3400U) +#define USB_RAM_BASE (PERIPH_BASE_APB2 + 0x3800U) +#define GFXTIM_BASE (PERIPH_BASE_APB2 + 0x3800U) +#define LTDC_BASE (PERIPH_BASE_APB2 + 0x3C00U) +#define DSI_BASE (PERIPH_BASE_APB2 + 0x4000U) +/* PERIPH_BASE_APB2 + 0x5000 (0x4001 7C00 - 0x4001 FFFF): Reserved */ + +/* AHB1 */ +#define GPDMA1_BASE (PERIPH_BASE_AHB1 + 0x0000U) +#define CORDIC_BASE (PERIPH_BASE_AHB1 + 0x1000U) +#define FMAC_BASE (PERIPH_BASE_AHB1 + 0x1400U) +/* PERIPH_BASE_AHB1 + 0x1800 (0x4002 1800 - 0x4002 1FFF): Reserved */ +#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000U) +/* PERIPH_BASE_AHB1 + 0x2400 (0x4002 2400 - 0x4002 2FFF): Reserved */ +#define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000U) +/* PERIPH_BASE_AHB1 + 0x3400 (0x4002 3400 - 0x4002 3FFF): Reserved */ +#define TSC_BASE (PERIPH_BASE_AHB1 + 0x4000U) +/* PERIPH_BASE_AHB1 + 0x4400 (0x4002 4400 - 0x4002 4FFF): Reserved */ +#define MDF1_BASE (PERIPH_BASE_AHB1 + 0x5000U) +#define RAMCFG_BASE (PERIPH_BASE_AHB1 + 0x6000U) +/* PERIPH_BASE_AHB1 + 0x7000 (0x4002 7000 - 0x4002 AFFF): Reserved */ +#define JPEG_BASE (PERIPH_BASE_AHB1 + 0xA000U) +#define DMA2D_BASE (PERIPH_BASE_AHB1 + 0xB000U) +/* PERIPH_BASE_AHB1 + 0xBC00 (0x4002 BC00 - 0x4002 BFFF): Reserved */ +#define GFXMMU_BASE (PERIPH_BASE_AHB1 + 0xC000U) +#define GPU2D_BASE (PERIPH_BASE_AHB1 + 0xF000U) +/* PERIPH_BASE_AHB1 + 0x10000 (0x4003 0000 - 0x4003 03FF): Reserved */ +#define ICACHE_BASE (PERIPH_BASE_AHB1 + 0x10400U) +/* PERIPH_BASE_AHB1 + 0x10800 (0x4003 0800 - 0x4003 13FF): Reserved */ +#define DCACHE1_BASE (PERIPH_BASE_AHB1 + 0x11400U) +#define DCACHE2_BASE (PERIPH_BASE_AHB1 + 0x11800U) +/* PERIPH_BASE_AHB1 + 0x11C00 (0x4003 1C00 - 0x4003 23FF): Reserved */ +#define GTZC1_TZSC_BASE (PERIPH_BASE_AHB1 + 0x12400U) +#define GTZC1_TZIC_BASE (PERIPH_BASE_AHB1 + 0x12800U) +#define GTZC1_MPCBB1_BASE (PERIPH_BASE_AHB1 + 0x12C00U) +#define GTZC1_MPCBB2_BASE (PERIPH_BASE_AHB1 + 0x13000U) +#define GTZC1_MPCBB3_BASE (PERIPH_BASE_AHB1 + 0x13400U) +#define GTZC1_MPCBB5_BASE (PERIPH_BASE_AHB1 + 0x13C00U) +#define GTZC1_MPCBB6_BASE (PERIPH_BASE_AHB1 + 0x13800U) +/* PERIPH_BASE_AHB1 + 0x14000 (0x4003 4000 - 0x4003 63FF): Reserved */ +#define BKPSRAM_BASE (PERIPH_BASE_AHB1 + 0x16400U) +/* PERIPH_BASE_AHB1 + 0x16C00 (0x4003 6C00 - 0x4201 FFFF): Reserved */ + +/* AHB2 */ +#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000U) +#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400U) +#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800U) +#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0C00U) +#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000U) +#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400U) +#define GPIO_PORT_G_BASE (PERIPH_BASE_AHB2 + 0x1800U) +#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB2 + 0x1C00U) +#define GPIO_PORT_I_BASE (PERIPH_BASE_AHB2 + 0x2000U) +#define GPIO_PORT_J_BASE (PERIPH_BASE_AHB2 + 0x2400U) +/* PERIPH_BASE_AHB2 + 0x2800 (0x4202 2800 - 0x4202 7FFF): Reserved */ +#define ADC1_BASE (PERIPH_BASE_AHB2 + 0x8000U) +/* PERIPH_BASE_AHB2 + 0x8400 (0x4202 8400 - 0x4202 BFFF): Reserved */ +#define DCMI_BASE (PERIPH_BASE_AHB2 + 0xC000U) +#define PSSI_BASE (PERIPH_BASE_AHB2 + 0xC400U) +/* PERIPH_BASE_AHB2 + 0xC800 (0x4202 C800 - 0x4203 FFFF): Reserved */ +#define OTG_FS_BASE (PERIPH_BASE_AHB2 + 0x20000U) +#define OTG_HS_BASE (PERIPH_BASE_AHB2 + 0x20000U) +#define AES AES_BASE (PERIPH_BASE_AHB2 + 0xA0000U) +#define HASH_BASE (PERIPH_BASE_AHB2 + 0xA0400U) +#define RNG_BASE (PERIPH_BASE_AHB2 + 0xA0800U) +#define SAES_BASE (PERIPH_BASE_AHB2 + 0xA0C00U) +/* PERIPH_BASE_AHB2 + 0xA1000 (0x420C 1000 - 0x420C 1FFF): Reserved */ +#define PKA_BASE (PERIPH_BASE_AHB2 + 0xA2000U) +#define OCTOSPIM_BASE (PERIPH_BASE_AHB2 + 0xA4000U) +/* PERIPH_BASE_AHB2 + 0xA4400 (0x420C 4400 - 0x420C 4FFF): Reserved */ +#define OTFDEC1_BASE (PERIPH_BASE_AHB2 + 0xA5000U) +#define OTFDEC2_BASE (PERIPH_BASE_AHB2 + 0xA5400U) +/* PERIPH_BASE_AHB2 + 0xA5800 (0x420C 5800 - 0x420C 7FFF): Reserved */ +#define SDMMC1_BASE (PERIPH_BASE_AHB2 + 0xA8000U) +#define DLYBSD1_BASE (PERIPH_BASE_AHB2 + 0xA8400U) +#define DLYBSD2_BASE (PERIPH_BASE_AHB2 + 0xA8800U) +#define SDMMC2_BASE (PERIPH_BASE_AHB2 + 0xA8C00U) +/* PERIPH_BASE_AHB2 + 0xA9000 (0x420C 9000 - 0x420C EFFF): Reserved */ +#define DLYBOS1_BASE (PERIPH_BASE_AHB2 + 0xAF000U) +#define DLYBOS2_BASE (PERIPH_BASE_AHB2 + 0xAF400U) +/* PERIPH_BASE_AHB2 + 0xAF800 (0x420C F800 - 0x420D 03FF): Reserved */ +#define FSMC_BASE (PERIPH_BASE_AHB2 + 0xB0400U) +/* PERIPH_BASE_AHB2 + 0xB0800 (0x420D 0800 - 0x420D 13FF): Reserved */ +#define OCTOSPI1_BASE (PERIPH_BASE_AHB2 + 0xB1400U) +/* PERIPH_BASE_AHB2 + 0xB1800 (0x420D 1800 - 0x420D 23FF): Reserved */ +#define OCTOSPI2_BASE (PERIPH_BASE_AHB2 + 0xB2400U) +/* PERIPH_BASE_AHB2 + 0xB2800 (0x420D 2800 - 0x420D 33FF): Reserved */ +#define HSPI1_BASE (PERIPH_BASE_AHB2 + 0xB3400U) +/* PERIPH_BASE_AHB2 + 0xB3800 (0x420D 3800 - 0x4600 03FF): Reserved */ + +/* APB3 */ +#define SYSCFG_BASE (PERIPH_BASE_APB3 + 0x0000U) +/* PERIPH_BASE_APB3 + 0x0400 (0x4600 0800 - 0x4600 1FFF): Reserved */ +#define SPI3_BASE (PERIPH_BASE_APB3 + 0x1C00U) +#define LPUART1_BASE PERIPH_BASE_APB3 + 0x2000U) +#define I2C3a_BASE (PERIPH_BASE_APB3 + 0x2400U) +/* PERIPH_BASE_APB3 + 0x2800 (0x4600 2C00 - 0x4600 43FF): Reserved */ +#define LPTIM1_BASE (PERIPH_BASE_APB3 + 0x4000U) +#define LPTIM3_BASE (PERIPH_BASE_APB3 + 0x4400U) +#define LPTIM_BASE (PERIPH_BASE_APB3 + 0x4800U) +#define OPAMP_BASE (PERIPH_BASE_APB3 + 0x4C00U) +#define COMP_BASE (PERIPH_BASE_APB3 + 0x5000U) +/* PERIPH_BASE_APB3 + 0x5400 (0x4600 5800 - 0x4600 73FF): Reserved */ +#define VREFBUF_BASE (PERIPH_BASE_APB3 + 0x7000U) +#define RTC_BASE (PERIPH_BASE_APB3 + 0x7400U) +#define TAMP_BASE (PERIPH_BASE_APB3 + 0x7800U) +/* PERIPH_BASE_APB3 + 0x7C00 (0x4600 8000 - 0x4601 FFFF): Reserved */ + +/* AHB3 */ +#define LPGPIO1_BASE (PERIPH_BASE_AHB3 + 0x0000U) +/* PERIPH_BASE_AHB3 + 0x0400 (0x4602 0400 - 0x4602 07FF): Reserved */ +#define PWR_BASE (PERIPH_BASE_AHB3 + 0x0800U) +#define RCC_BASE (PERIPH_BASE_AHB3 + 0x0C00U) +#define ADC4_BASE (PERIPH_BASE_AHB3 + 0x1000U) +/* PERIPH_BASE_AHB3 + 0x1400 (0x4602 1400 - 0x4602 17FF): Reserved */ +#define DAC1_BASE (PERIPH_BASE_AHB3 + 0x1800U) +/* PERIPH_BASE_AHB3 + 0x1C00 ( 0x4602 1C00 - 0x4602 1FFF): Reserved */ +#define EXTI_BASE (PERIPH_BASE_AHB3 + 0x2000U) +/* PERIPH_BASE_AHB3 + 0x2400 (0x4602 2400 - 0x4602 2FFF): Reserved */ +#define GTZC2_TZSC_BASE (PERIPH_BASE_AHB3 + 0x3000U) +#define GTZC2_TZIC_BASE (PERIPH_BASE_AHB3 + 0x3400U) +#define GTZC2_MPCBB4_BASE (PERIPH_BASE_AHB3 + 0x3800U) +/* PERIPH_BASE_AHB3 + 0x3C00 (0x4602 3C00 - 0x4602 3FFF): Reserved */ +#define ADF1_BASE (PERIPH_BASE_AHB3 + 0x4000U) +#define LPDMA1_BASE (PERIPH_BASE_AHB3 + 0x5000U) +/* PERIPH_BASE_AHB3 + 0x6000 (0x4602 6000 - 0x4FFF FFFF): Reserved */ + +#endif diff --git a/include/libopencm3/stm32/u5/rcc.h b/include/libopencm3/stm32/u5/rcc.h new file mode 100644 index 00000000..485f8511 --- /dev/null +++ b/include/libopencm3/stm32/u5/rcc.h @@ -0,0 +1,131 @@ +/** @defgroup rcc_defines RCC Defines + * + * @ingroup STM32U5xx_defines + * + * @brief Defined Constants and Types for the STM32U5xx Reset and Clock + * Control + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2015 Karl Palsson + * + * @date 05 October 2024 + * + * LGPL License Terms @ref lgpl_license + * */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2015 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + * + */ + +/**@{*/ + +#ifndef LIBOPENCM3_RCC_H +#define LIBOPENCM3_RCC_H + +/*****************************************************************************/ +/* Module definitions */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Register definitions */ +/*****************************************************************************/ + +#define RCC_CR MMIO32(RCC_BASE + 0x00) +#define RCC_CFGR MMIO32(RCC_BASE + 0x1c) +#define RCC_CFGR2 MMIO32(RCC_BASE + 0x20) +#define RCC_CFGR3 MMIO32(RCC_BASE + 0x24) + + +/*****************************************************************************/ +/* Register values */ +/*****************************************************************************/ + +/* --- RCC_CR values ------------------------------------------------------- */ + +#define RCC_CR_HSEBYP (1 << 18) + +/* --- RCC_CFGR values ----------------------------------------------------- */ + +#define RCC_CFGR_MCO_SHIFT 24 +#define RCC_CFGR_MCO_MASK 0xf + +/* --- RCC_BDCR values ----------------------------------------------------- */ + +#define RCC_BDCR MMIO32(RCC_BASE + 0xF0) +#define RCC_BDCR_LSEBYP (1 << 2) + +/*****************************************************************************/ +/* API definitions */ +/*****************************************************************************/ + +enum rcc_osc { + RCC_PLL, + RCC_HSE, + RCC_HSI, + RCC_HSI16, + RCC_MSIS, + RCC_MSIK, + RCC_LSI, + RCC_LSE, + RCC_HSI48, + RCC_SHSI, +}; + +#define _REG_BIT(base, bit) (((base) << 5) + (bit)) + +enum rcc_periph_rst { + /* AHB2 peripherals */ + RST_GPIOA = _REG_BIT(0x64, 0), + RST_GPIOB = _REG_BIT(0x64, 1), + RST_GPIOC = _REG_BIT(0x64, 2), + RST_GPIOD = _REG_BIT(0x64, 3), + RST_GPIOE = _REG_BIT(0x64, 4), + RST_GPIOF = _REG_BIT(0x64, 5), + RST_GPIOG = _REG_BIT(0x64, 6), + RST_GPIOH = _REG_BIT(0x64, 7), +}; + + +enum rcc_periph_clken { + /* AHB2 peripherals */ + RCC_GPIOA = _REG_BIT(0x8C, 0), + RCC_GPIOB = _REG_BIT(0x8C, 1), + RCC_GPIOC = _REG_BIT(0x8C, 2), + RCC_GPIOD = _REG_BIT(0x8C, 3), + RCC_GPIOE = _REG_BIT(0x8C, 4), + RCC_GPIOF = _REG_BIT(0x8C, 5), + RCC_GPIOG = _REG_BIT(0x8C, 6), + RCC_GPIOH = _REG_BIT(0x8C, 7), +}; +#undef _REG_BIT + +/*****************************************************************************/ +/* API Functions */ +/*****************************************************************************/ + +#include + +BEGIN_DECLS + +END_DECLS + +/**@}*/ + +#endif diff --git a/lib/stm32/u5/Makefile b/lib/stm32/u5/Makefile new file mode 100644 index 00000000..54e7a548 --- /dev/null +++ b/lib/stm32/u5/Makefile @@ -0,0 +1,43 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2013 Frantisek Burian +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . +## + +LIBNAME = libopencm3_stm32u5 +SRCLIBDIR ?= ../.. + +CC = $(PREFIX)gcc +AR = $(PREFIX)ar +TGT_CFLAGS = -Os \ + -Wall -Wextra -Wimplicit-function-declaration \ + -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ + -Wundef -Wshadow \ + -I../../../include -fno-common \ + -mcpu=cortex-m0 $(FP_FLAGS) -mthumb -Wstrict-prototypes \ + -ffunction-sections -fdata-sections -MD -DSTM32U5 +TGT_CFLAGS += $(DEBUG_FLAGS) +TGT_CFLAGS += $(STANDARD_FLAGS) + +ARFLAGS = rcs + +OBJS += gpio_common_all.o gpio_common_f0234.o +OBJS += rcc_common_all.o + +VPATH += ../:../../cm3:../common + +include ../../Makefile.include +