From 4a9ba30138141e40bd75682a4d9fc37a0ad250f8 Mon Sep 17 00:00:00 2001
From: TomasPech <44266722+TomasPech@users.noreply.github.com>
Date: Thu, 12 Dec 2019 00:32:00 +0100
Subject: [PATCH] stm32f4: rcc_clock_setup_pll() correctly enable PWR

Original code used the special macros for rcc_periph_clock_enable
instead of the appropraite APB1ENR bit definition.

Switch to the correct, simpler form, using the correct parameter.
---
 lib/stm32/f4/rcc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/stm32/f4/rcc.c b/lib/stm32/f4/rcc.c
index 3d0e00fa..e3a4f372 100644
--- a/lib/stm32/f4/rcc.c
+++ b/lib/stm32/f4/rcc.c
@@ -722,7 +722,7 @@ void rcc_clock_setup_pll(const struct rcc_clock_scale *clock)
 	}
 
 	/* Set the VOS scale mode */
-	rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_PWR);
+	rcc_periph_clock_enable(RCC_PWR);
 	pwr_set_vos_scale(clock->voltage_scale);
 
 	/*