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Merge branch 'generalizations' into efm32

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Conflicts:
	Makefile
This commit is contained in:
chrysn
2012-10-18 18:43:38 +02:00
parent b5de267b06 771f504757
commit 47c69695ce
154 changed files with 7142 additions and 2301 deletions
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136
include/libopencm3/cm3/assert.h Normal file
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/** @defgroup debugging Debugging
@brief Macros and functions to aid in debugging
@version 1.0.0
@date 25 September 2012
Two preprocessor defines control the behavior of assertion check macros in
this module. They allow the choice between generated code size and ease of
debugging.
If NDEBUG is defined, all assertion checks are disabled and macros do not
generate any code.
If CM3_ASSERT_VERBOSE is defined, information regarding the position of
assertion checks will be stored in the binary, allowing for more
informative error messages, but also significantly increased code size. As
default assertion checks do not use this information it is only useful if
the application linked with libopencm3 defines its own
cm3_assert_failed_verbose() implementation.
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Tomaz Solc <tomaz.solc@tablix.org>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#ifndef LIBOPENCM3_CM3_ASSERT_H
#define LIBOPENCM3_CM3_ASSERT_H
#include <libopencm3/cm3/common.h>
#define CM3_LIKELY(expr) (__builtin_expect (!!(expr), 1))
#ifdef NDEBUG
# define cm3_assert(expr) do { (void)0; } while(0)
# define cm3_assert_not_reached() while(1)
#else
# ifdef CM3_ASSERT_VERBOSE
# define cm3_assert(expr) do { \
if(CM3_LIKELY(expr)) { (void)0; } else { \
cm3_assert_failed_verbose( \
__FILE__, __LINE__, \
__func__, #expr); \
} \
} while(0)
# define cm3_assert_not_reached() do { \
cm3_assert_failed_verbose( \
__FILE__, __LINE__, \
__func__, 0); \
} while(0)
# else
/** @brief Check if assertion is true.
*
* If NDEBUG macro is defined, this macro generates no code. Otherwise
* cm3_assert_failed() or cm3_assert_failed_verbose() is called if assertion
* is false.
*
* The purpose of this macro is to aid in debugging libopencm3 and
* applications using it. It can be used for example to check if function
* arguments are within expected ranges and stop execution in case an
* unexpected state is reached.
*
* @param expr expression to check */
# define cm3_assert(expr) do { \
if(CM3_LIKELY(expr)) { (void)0; } else { \
cm3_assert_failed(); \
} \
} while(0)
/** @brief Check if unreachable code is reached.
*
* If NDEBUG macro is defined, this macro generates code for an infinite loop.
* Otherwise cm3_assert_failed() or cm3_assert_failed_verbose() is called if
* the macro is ever reached.
*
* The purpose of this macro is to aid in debugging libopencm3 and
* applications using it. It can be used for example to stop execution if an
* unreachable portion of code is reached. */
# define cm3_assert_not_reached() do { \
cm3_assert_failed(); \
} while(0)
# endif
#endif
BEGIN_DECLS
/** @brief Called on a failed assertion.
*
* Halts execution in an infinite loop. This function never returns.
*
* Defined as a weak symbol, so applications can define their own
* implementation. Usually, a custom implementation of this function should
* report an error in some way (print a message to a debug console, display,
* LED, ...) and halt execution or reboot the device. */
void cm3_assert_failed(void) __attribute__ ((__noreturn__));
/** @brief Called on a failed assertion with verbose messages enabled.
*
* Halts execution in an infinite loop. This function never returns.
*
* Defined as a weak symbol, so applications can define their own
* implementation. Usually, a custom implementation of this function should
* report an error in some way (print a message to a debug console, display,
* LED, ...) and halt execution or reboot the device.
*
* @param file File name where the failed assertion occurred
* @param line Line number where the failed assertion occurred
* @param func Name of the function where the failed assertion occurred
* @param assert_expr Expression that evaluated to false (can be NULL) */
void cm3_assert_failed_verbose(const char *file, int line, const char *func,
const char *assert_expr) __attribute__ ((__noreturn__));
END_DECLS
#endif
/**@}*/

22
include/libopencm3/cm3/doc-cm3.h Normal file
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/** @mainpage libopencm3 Core CM3
@version 1.0.0
@date 14 September 2012
API documentation for Cortex M3 core features.
LGPL License Terms @ref lgpl_license
*/
/** @defgroup CM3_defines CM3 Defines
@brief Defined Constants and Types for Cortex M3 core features
@version 1.0.0
@date 14 September 2012
LGPL License Terms @ref lgpl_license
*/

70
include/libopencm3/cm3/docmain.h
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/**
* @mainpage libopencm3 Developer Documentation
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies ksarkies@internode.on.net
@date 18 August 2012
* The libopencm3 project (previously known as libopenstm32) aims to create
* a free/libre/open-source (GPL v3, or later) firmware library for various
* ARM Cortex-M3 microcontrollers, including ST STM32, Toshiba TX03,
* Atmel SAM3U, NXP LPC1000 and others.
*
* @par ""
*
* See the <a href="http://www.libopencm3.org">libopencm3 wiki</a> for
* more information.
LGPL License Terms @ref lgpl_license
*/
/** @page lgpl_license libopencm3 License
libopencm3 is free software: you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as published by the Free
Software Foundation, either version 3 of the License, or (at your option) any
later version.
libopencm3 is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public License along with this
program. If not, see <http://www.gnu.org/licenses/>.
*/
/** @defgroup LM3S LM3S
Libraries for Texas instruments LM3S series.
*/
/** @defgroup LPC13xx LPC13xx
Libraries for NXP Semiconductor LPC13xx series.
*/
/** @defgroup LPC17xx LPC17xx
Libraries for NXP Semiconductor LPC17xx series.
*/
/** @defgroup STM32F STM32F
Libraries for ST Microelectronics STM32F series.
*/
/** @defgroup STM32F1xx STM32F1xx
@ingroup STM32F
Libraries for ST Microelectronics STM32F1xx series.
*/
/** @defgroup STM32F2xx STM32F2xx
@ingroup STM32F
Libraries for ST Microelectronics STM32F2xx series.
*/
/** @defgroup STM32F4xx STM32F4xx
@ingroup STM32F
Libraries for ST Microelectronics STM32F4xx series.
*/

52
include/libopencm3/stm32/nvic.h → include/libopencm3/cm3/nvic.h
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@@ -1,21 +1,9 @@
/** @defgroup STM32F_nvic_defines NVIC Defines
@brief <b>libopencm3 STM32F Nested Vectored Interrupt Controller</b>
@ingroup STM32F_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2010 Piotr Esden-Tempski <piotr@esden.net>
@date 18 August 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
@@ -30,13 +18,27 @@ LGPL License Terms @ref lgpl_license
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/** @defgroup CM3_nvic_defines NVIC Defines
@brief <b>libopencm3 Cortex Nested Vectored Interrupt Controller</b>
@ingroup CM3_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2010 Piotr Esden-Tempski <piotr@esden.net>
@date 18 August 2012
LGPL License Terms @ref lgpl_license
*/
/**@{*/
#ifndef LIBOPENCM3_NVIC_H
#define LIBOPENCM3_NVIC_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
#include <libopencm3/cm3/memorymap.h>
/* --- NVIC Registers ------------------------------------------------------ */
@@ -79,9 +81,9 @@ LGPL License Terms @ref lgpl_license
/* --- IRQ channel numbers-------------------------------------------------- */
/* Cortex M3 System Interrupts */
/** @defgroup nvic_sysint Cortex M3 System Interrupts
@ingroup STM32F_nvic_defines
/* Cortex M3 and M4 System Interrupts */
/** @defgroup nvic_sysint Cortex M3/M4 System Interrupts
@ingroup CM3_nvic_defines
IRQ numbers -3 and -6 to -9 are reserved
@{*/
@@ -98,21 +100,11 @@ IRQ numbers -3 and -6 to -9 are reserved
#define NVIC_SYSTICK_IRQ -1
/**@}*/
/* Note: User interrupts are family specific and are defined in a family
* specific header file in the corresponding subfolder.
*/
#if defined(STM32F1)
# include <libopencm3/stm32/f1/nvic_f1.h>
#elif defined(STM32F2)
# include <libopencm3/stm32/f2/nvic_f2.h>
#elif defined(STM32F4)
# include <libopencm3/stm32/f4/nvic_f4.h>
#else
# error "stm32 family not defined."
#endif
#include <libopencm3/dispatch/nvic.h>
/* --- NVIC functions ------------------------------------------------------ */
@@ -131,5 +123,3 @@ void nvic_generate_software_interrupt(u16 irqn);
END_DECLS
#endif
/**@}*/

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include/libopencm3/cm3/vector.h Normal file
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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 chrysn <chrysn@fsfe.org>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
*
* Definitions for handling vector tables.
*
* This implements d0002_efm32_cortex-m3_reference_manual.pdf's figure 2.2
* (from the EFM32 documentation at
* http://www.energymicro.com/downloads/datasheets), and was seen analogously
* in other ARM implementations' libopencm3 files.
*
* The structure of the vector table is implemented independently of the system
* vector table starting at memory position 0x0, as it can be relocated to
* other memory locations too.
*
* The exact size of a vector interrupt table depends on the number of
* interrupts IRQ_COUNT, which is defined per family.
*/
#ifndef LIBOPENCM3_VECTOR_H
#define LIBOPENCM3_VECTOR_H
#include <libopencm3/cm3/common.h>
#include <libopencm3/cm3/nvic.h>
/** Type of an interrupt function. Only used to avoid hard-to-read function
* pointers in the efm32_vector_table_t struct. */
typedef void (*vector_table_entry_t)(void);
typedef struct {
unsigned int *initial_sp_value; /**< The value the stack pointer is set to initially */
vector_table_entry_t reset;
vector_table_entry_t nmi;
vector_table_entry_t hard_fault;
vector_table_entry_t memory_manage_fault;
vector_table_entry_t bus_fault;
vector_table_entry_t usage_fault;
vector_table_entry_t reserved_x001c[4];
vector_table_entry_t sv_call;
vector_table_entry_t debug_monitor;
vector_table_entry_t reserved_x0034;
vector_table_entry_t pend_sv;
vector_table_entry_t systick;
vector_table_entry_t irq[NVIC_IRQ_COUNT];
} vector_table_t;
#endif

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include/libopencm3/dispatch/nvic.h Normal file
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@@ -0,0 +1,19 @@
#if defined(STM32F1)
# include <libopencm3/stm32/f1/nvic.h>
#elif defined(STM32F2)
# include <libopencm3/stm32/f2/nvic.h>
#elif defined(STM32F4)
# include <libopencm3/stm32/f4/nvic.h>
#elif defined(TINYGECKO)
# include <libopencm3/efm32/tinygecko/nvic.h>
#elif defined(LPC43XX)
# include <libopencm3/lpc43xx/nvic.h>
#else
# warning"no chipset defined; user interrupts are disabled"
#define NVIC_IRQ_COUNT 0
#endif

21
include/libopencm3/docmain.dox Normal file
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@@ -0,0 +1,21 @@
/** @mainpage libopencm3 Developer Documentation
@version 1.0.0
@date 7 September 2012
* The libopencm3 project (previously known as libopenstm32) aims to create
* a free/libre/open-source (GPL v3, or later) firmware library for various
* ARM Cortex-M3 microcontrollers, including ST STM32, Toshiba TX03,
* Atmel SAM3U, NXP LPC1000 and others.
*
* @par ""
*
* See the <a href="http://www.libopencm3.org">libopencm3 wiki</a> for
* more information.
LGPL License Terms @ref lgpl_license
*/

28
include/libopencm3/efm32/tinygecko/irq.yaml Normal file
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@@ -0,0 +1,28 @@
includeguard: LIBOPENCM3_EFM32_TINYGECKO_NVIC_H
partname_humanreadable: EFM32 Tiny Gecko series
partname_doxygen: EFM32TG
# The names and sequence are taken from d0034_efm32tg_reference_manual.pdf table 4.1.
irqs:
- dma
- gpio_even
- timer0
- usart0_rx
- usart0_tx
- acmp01
- adc0
- dac0
- i2c0
- gpio_odd
- timer1
- usart1_rx
- usart1_tx
- lesense
- leuart0
- letimer0
- pcnt0
- rtc
- cmu
- vcmp
- lcd
- msc
- aes

16
include/libopencm3/license.dox Normal file
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@@ -0,0 +1,16 @@
/** @page lgpl_license libopencm3 License
libopencm3 is free software: you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as published by the Free
Software Foundation, either version 3 of the License, or (at your option) any
later version.
libopencm3 is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public License along with this
program. If not, see <http://www.gnu.org/licenses/>.
*/

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include/libopencm3/lm3s/doc-lm3s.h Normal file
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@@ -0,0 +1,32 @@
/** @mainpage libopencm3 LM3S
@version 1.0.0
@date 14 September 2012
API documentation for TI Stellaris LM3S Cortex M3 series.
LGPL License Terms @ref lgpl_license
*/
/** @defgroup LM3S LM3S
Libraries for TI Stellaris LM3S series.
@version 1.0.0
@date 7 September 2012
LGPL License Terms @ref lgpl_license
*/
/** @defgroup LM3S_defines LM3S Defines
@brief Defined Constants and Types for the LM3S series
@version 1.0.0
@date 14 September 2012
LGPL License Terms @ref lgpl_license
*/

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include/libopencm3/lm3s/irq.yaml Normal file
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includeguard: LIBOPENCM3_LM3S_NVIC_H
partname_humanreadable: LM3S series
partname_doxygen: LM3S
irqs:
0: GPIOA
1: GPIOB
2: GPIOC
3: GPIOD
4: GPIOE
5: UART0
6: UART1
7: SSI0
8: I2C0
9: PWM0_FAULT
10: PWM0_0
11: PWM0_1
12: PWM0_2
13: QEI0
14: ADC0SS0
15: ADC0SS1
16: ADC0SS2
17: ADC0SS3
18: WATCHDOG
19: TIMER0A
20: TIMER0B
21: TIMER1A
22: TIMER1B
23: TIMER2A
24: TIMER2B
25: COMP0
26: COMP1
27: COMP2
28: SYSCTL
29: FLASH
30: GPIOF
31: GPIOG
32: GPIOH
33: UART2
34: SSI1
35: TIMER3A
36: TIMER3B
37: I2C1
38: QEI1
39: CAN0
40: CAN1
41: CAN2
42: ETH
43: HIBERNATE
44: USB0
45: PWM0_3
46: UDMA
47: UDMAERR
48: ADC1SS0
49: ADC1SS1
50: ADC1SS2
51: ADC1SS3
52: I2S0
53: EPI0
54: GPIOJ
55: GPIOK
56: GPIOL
57: SSI2
58: SSI3
59: UART3
60: UART4
61: UART5
62: UART6
63: UART7
# undefined: slot 64 - 67
68: I2C2
69: I2C3
70: TIMER4A
71: TIMER4B
# undefined: slot 72 - 91
92: TIMER5A
93: TIMER5B
94: WTIMER0A
95: WTIMER0B
96: WTIMER1A
97: WTIMER1B
98: WTIMER2A
99: WTIMER2B
100: WTIMER3A
101: WTIMER3B
102: WTIMER4A
103: WTIMER4B
104: WTIMER5A
105: WTIMER5B
106: SYSEXC
107: PECI0
108: LPC0
109: I2C4
110: I2C5
111: GPIOM
112: GPION
# undefined: slot 113
114: FAN0
# undefined: slot 115
116: GPIOP0
117: GPIOP1
118: GPIOP2
119: GPIOP3
120: GPIOP4
121: GPIOP5
122: GPIOP6
123: GPIOP7
124: GPIOQ0
125: GPIOQ1
126: GPIOQ2
127: GPIOQ3
128: GPIOQ4
129: GPIOQ5
130: GPIOQ6
131: GPIOQ7
# undefined: slot 132 - 133
134: PWM1_0
135: PWM1_1
136: PWM1_2
137: PWM1_3
138: PWM1_FAULT

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@@ -0,0 +1,32 @@
/** @mainpage libopencm3 LPC13xx
@version 1.0.0
@date 14 September 2012
API documentation for NXP Semiconductors LPC13xx Cortex M3 series.
LGPL License Terms @ref lgpl_license
*/
/** @defgroup LPC13xx LPC13xx
Libraries for NXP Semiconductors LPC13xx series.
@version 1.0.0
@date 14 September 2012
LGPL License Terms @ref lgpl_license
*/
/** @defgroup LPC13xx_defines LPC13xx Defines
@brief Defined Constants and Types for the LPC13xx series
@version 1.0.0
@date 14 September 2012
LGPL License Terms @ref lgpl_license
*/

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@@ -0,0 +1,32 @@
/** @mainpage libopencm3 LPC13xx
@version 1.0.0
@date 14 September 2012
API documentation for NXP Semiconductors LPC13xx Cortex M3 series.
LGPL License Terms @ref lgpl_license
*/
/** @defgroup LPC13xx LPC13xx
Libraries for NXP Semiconductors LPC13xx series.
@version 1.0.0
@date 14 September 2012
LGPL License Terms @ref lgpl_license
*/
/** @defgroup LPC13xx_defines LPC13xx Defines
@brief Defined Constants and Types for the LPC13xx series
@version 1.0.0
@date 14 September 2012
LGPL License Terms @ref lgpl_license
*/

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include/libopencm3/lpc43xx/doc-lpc43xx.h Normal file
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@@ -0,0 +1,32 @@
/** @mainpage libopencm3 LPC43xx
@version 1.0.0
@date 14 September 2012
API documentation for NXP Semiconductors LPC43xx Cortex M3 series.
LGPL License Terms @ref lgpl_license
*/
/** @defgroup LPC43xx LPC43xx
Libraries for NXP Semiconductors LPC43xx series.
@version 1.0.0
@date 14 September 2012
LGPL License Terms @ref lgpl_license
*/
/** @defgroup LPC43xx_defines LPC43xx Defines
@brief Defined Constants and Types for the LPC43xx series
@version 1.0.0
@date 14 September 2012
LGPL License Terms @ref lgpl_license
*/

55
include/libopencm3/lpc43xx/irq.yaml Normal file
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@@ -0,0 +1,55 @@
includeguard: LIBOPENCM3_LPC43xx_NVIC_H
partname_humanreadable: LPC 43xx series
partname_doxygen: LPC43xx
irqs:
0: dac
1: m0core
2: dma
# reserved: 3, 4
5: ethernet
6: sdio
7: lcd
8: usb0
9: usb1
10: sct
11: ritimer
12: timer0
13: timer1
14: timer2
15: timer3
16: mcpwm
17: adc0
18: i2c0
19: i2c1
20: spi
21: adc1
22: ssp0
23: ssp1
24: usart0
25: uart1
26: usart2
27: usart3
28: i2s0
29: i2s1
30: spifi
31: sgpio
32: pin_int0
33: pin_int1
34: pin_int2
35: pin_int3
36: pin_int4
37: pin_int5
38: pin_int6
39: pin_int7
40: gint0
41: gint1
42: eventrouter
43: c_can1
# reserved: 44, 45
46: atimer
47: rtc
# reserved: 48
49: wwdt
# reserved: 50
51: c_can0
52: qei

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include/libopencm3/lpc43xx/nvic.h
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@@ -1,151 +0,0 @@
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LPC43XX_NVIC_H
#define LPC43XX_NVIC_H
#include <libopencm3/cm3/common.h>
#include <libopencm3/cm3/memorymap.h>
#include <libopencm3/lpc43xx/memorymap.h>
/* --- NVIC Registers ------------------------------------------------------ */
/* ISER: Interrupt Set Enable Registers */
/* Note: 8 32bit Registers */
#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4))
/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */
/* ICER: Interrupt Clear Enable Registers */
/* Note: 8 32bit Registers */
#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4))
/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */
/* ISPR: Interrupt Set Pending Registers */
/* Note: 8 32bit Registers */
#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4))
/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */
/* ICPR: Interrupt Clear Pending Registers */
/* Note: 8 32bit Registers */
#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4))
/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */
/* IABR: Interrupt Active Bit Register */
/* Note: 8 32bit Registers */
#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4))
/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */
/* IPR: Interrupt Priority Registers */
/* Note: 240 8bit Registers */
#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id)
/* STIR: Software Trigger Interrupt Register */
#define NVIC_STIR MMIO32(STIR_BASE)
/* --- IRQ channel numbers-------------------------------------------------- */
/* Cortex M4 System Interrupts */
#define NVIC_NMI_IRQ -14
#define NVIC_HARD_FAULT_IRQ -13
#define NVIC_MEM_MANAGE_IRQ -12
#define NVIC_BUS_FAULT_IRQ -11
#define NVIC_USAGE_FAULT_IRQ -10
/* irq numbers -6 to -9 are reserved */
#define NVIC_SV_CALL_IRQ -5
#define DEBUG_MONITOR_IRQ -4
/* irq number -3 reserved */
#define NVIC_PENDSV_IRQ -2
#define NVIC_SYSTICK_IRQ -1
/* LPC43xx M4 specific user interrupts */
#define NVIC_M4_DAC_IRQ 0
#define NVIC_M4_M0CORE_IRQ 1
#define NVIC_M4_DMA_IRQ 2
#define NVIC_M4_ETHERNET_IRQ 5
#define NVIC_M4_SDIO_IRQ 6
#define NVIC_M4_LCD_IRQ 7
#define NVIC_M4_USB0_IRQ 8
#define NVIC_M4_USB1_IRQ 9
#define NVIC_M4_SCT_IRQ 10
#define NVIC_M4_RITIMER_IRQ 11
#define NVIC_M4_TIMER0_IRQ 12
#define NVIC_M4_TIMER1_IRQ 13
#define NVIC_M4_TIMER2_IRQ 14
#define NVIC_M4_TIMER3_IRQ 15
#define NVIC_M4_MCPWM_IRQ 16
#define NVIC_M4_ADC0_IRQ 17
#define NVIC_M4_I2C0_IRQ 18
#define NVIC_M4_I2C1_IRQ 19
#define NVIC_M4_SPI_IRQ 20
#define NVIC_M4_ADC1_IRQ 21
#define NVIC_M4_SSP0_IRQ 22
#define NVIC_M4_SSP1_IRQ 23
#define NVIC_M4_USART0_IRQ 24
#define NVIC_M4_UART1_IRQ 25
#define NVIC_M4_USART2_IRQ 26
#define NVIC_M4_USART3_IRQ 27
#define NVIC_M4_I2S0_IRQ 28
#define NVIC_M4_I2S1_IRQ 29
#define NVIC_M4_SPIFI_IRQ 30
#define NVIC_M4_SGPIO_IRQ 31
#define NVIC_M4_PIN_INT0_IRQ 32
#define NVIC_M4_PIN_INT1_IRQ 33
#define NVIC_M4_PIN_INT2_IRQ 34
#define NVIC_M4_PIN_INT3_IRQ 35
#define NVIC_M4_PIN_INT4_IRQ 36
#define NVIC_M4_PIN_INT5_IRQ 37
#define NVIC_M4_PIN_INT6_IRQ 38
#define NVIC_M4_PIN_INT7_IRQ 39
#define NVIC_M4_GINT0_IRQ 40
#define NVIC_M4_GINT1_IRQ 41
#define NVIC_M4_EVENTROUTER_IRQ 42
#define NVIC_M4_C_CAN1_IRQ 43
#define NVIC_M4_ATIMER_IRQ 46
#define NVIC_M4_RTC_IRQ 47
#define NVIC_M4_WWDT_IRQ 49
#define NVIC_M4_C_CAN0_IRQ 51
#define NVIC_M4_QEI_IRQ 52
/* LPC43xx M0 specific user interrupts */
//TODO
/* --- NVIC functions ------------------------------------------------------ */
BEGIN_DECLS
void nvic_enable_irq(u8 irqn);
void nvic_disable_irq(u8 irqn);
u8 nvic_get_pending_irq(u8 irqn);
void nvic_set_pending_irq(u8 irqn);
void nvic_clear_pending_irq(u8 irqn);
u8 nvic_get_active_irq(u8 irqn);
u8 nvic_get_irq_enabled(u8 irqn);
void nvic_set_priority(u8 irqn, u8 priority);
void nvic_generate_software_interrupt(u8 irqn);
END_DECLS
#endif

14
include/libopencm3/stm32/crc.h
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@@ -1,3 +1,17 @@
/** @defgroup crc_defines CRC Defines
@brief <b>libopencm3 Defined Constants and Types for the STM32F CRC Generator </b>
@ingroup STM32F_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
@date 18 August 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*

27
include/libopencm3/stm32/doc-stm32f.h
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@@ -1,24 +1,29 @@
/** @defgroup STM32F_defines STM32F Top Level Defines
@brief Defined Constants and Types for the STM32F series
@ingroup STM32F
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies ksarkies@internode.on.net
/** @mainpage libopencm3 STM32 Common
@version 1.0.0
@date 18 August 2012
@date 7 September 2012
API documentation for common files for ST Microelectronics STM32 Cortex M3 series.
LGPL License Terms @ref lgpl_license
*/
/** @defgroup STM32F_defines STM32F Common Defines
@brief Defined Constants and Types for the STM32F series
LGPL License Terms @ref lgpl_license
*/
/** @defgroup STM32F_files STM32F Top Level Files
/** @defgroup STM32F_files STM32F Common Files
@brief Common Files for ST Microelectronics STM32F series.
@ingroup STM32F
@version 1.0.0
@date 7 September 2012
LGPL License Terms @ref lgpl_license
*/

90
include/libopencm3/stm32/f1/adc.h
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@@ -252,7 +252,7 @@ LGPL License Terms @ref lgpl_license
#define ADC_CR1_DUALMOD_MASK (0xF << 16)
#define ADC_CR1_DUALMOD_SHIFT 16
/* DISCNUM[2:0]: Discontinous mode channel count. */
/* DISCNUM[2:0]: Discontinuous mode channel count. */
/****************************************************************************/
/** @defgroup adc_cr1_discnum ADC Number of channels in discontinuous mode.
@ingroup STM32F1xx_adc_defines
@@ -270,10 +270,10 @@ LGPL License Terms @ref lgpl_license
#define ADC_CR1_DISCNUM_MASK (0x7 << 13)
#define ADC_CR1_DISCNUM_SHIFT 13
/* JDISCEN: */ /** Discontinous mode on injected channels. */
/* JDISCEN: */ /** Discontinuous mode on injected channels. */
#define ADC_CR1_JDISCEN (1 << 12)
/* DISCEN: */ /** Discontinous mode on regular channels. */
/* DISCEN: */ /** Discontinuous mode on regular channels. */
#define ADC_CR1_DISCEN (1 << 11)
/* JAUTO: */ /** Automatic Injection Group conversion. */
@@ -557,7 +557,7 @@ LGPL License Terms @ref lgpl_license
/* --- ADC_SMPRx generic values -------------------------------------------- */
/****************************************************************************/
/* ADC_SMPRG ADC Sample Time Selection for Channels */
/** @defgroup adc_sample_rg ADC Sample Time Selection Generic
/** @defgroup adc_sample_rg ADC Sample Time Selection for All Channels
@ingroup STM32F1xx_adc_defines
@{*/
@@ -587,18 +587,11 @@ LGPL License Terms @ref lgpl_license
#define ADC_SQR1_SQ15_LSB 10
#define ADC_SQR1_SQ14_LSB 5
#define ADC_SQR1_SQ13_LSB 0
#define ADC_SQR1_L_MSK (0xf << ADC_L_LSB)
#define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQ16_LSB)
#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQ15_LSB)
#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQ14_LSB)
#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQ13_LSB)
/* TODO Fix error
#define ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB)
#define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQR1_SQ16_LSB)
#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQR1_SQ15_LSB)
#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQR1_SQ14_LSB)
#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQR1_SQ13_LSB)
*/
/* --- ADC_SQR2 values ----------------------------------------------------- */
@@ -608,20 +601,12 @@ LGPL License Terms @ref lgpl_license
#define ADC_SQR2_SQ9_LSB 10
#define ADC_SQR2_SQ8_LSB 5
#define ADC_SQR2_SQ7_LSB 0
#define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQ12_LSB)
#define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQ11_LSB)
#define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQ10_LSB)
#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQ9_LSB)
#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQ8_LSB)
#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQ7_LSB)
/* TODO Fix error
#define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQR2_SQ12_LSB)
#define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQR2_SQ11_LSB)
#define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQR2_SQ10_LSB)
#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQR2_SQ9_LSB)
#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQR2_SQ8_LSB)
#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQR2_SQ7_LSB)
*/
/* --- ADC_SQR3 values ----------------------------------------------------- */
@@ -631,20 +616,12 @@ LGPL License Terms @ref lgpl_license
#define ADC_SQR3_SQ3_LSB 10
#define ADC_SQR3_SQ2_LSB 5
#define ADC_SQR3_SQ1_LSB 0
#define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQ6_LSB)
#define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQ5_LSB)
#define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQ4_LSB)
#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQ3_LSB)
#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQ2_LSB)
#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQ1_LSB)
/* TODO Fix error
#define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQR3_SQ6_LSB)
#define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQR3_SQ5_LSB)
#define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQR3_SQ4_LSB)
#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQR3_SQ3_LSB)
#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQR3_SQ2_LSB)
#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQR3_SQ1_LSB)
*/
/* --- ADC_JSQR values ----------------------------------------------------- */
#define ADC_JSQR_JL_LSB 20
@@ -652,18 +629,24 @@ LGPL License Terms @ref lgpl_license
#define ADC_JSQR_JSQ3_LSB 10
#define ADC_JSQR_JSQ2_LSB 5
#define ADC_JSQR_JSQ1_LSB 0
#define ADC_JSQR_JL_MSK (0x2 << ADC_JL_LSB)
#define ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQ4_LSB)
#define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQ3_LSB)
#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQ2_LSB)
#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQ1_LSB)
/* TODO Fix error
/* JL[2:0]: Discontinous mode channel count injected channels. */
/****************************************************************************/
/** @defgroup adc_jsqr_jl ADC Number of channels in discontinuous mode fro injected channels.
@ingroup STM32F1xx_adc_defines
@{*/
#define ADC_JSQR_JL_1CHANNELS (0x0 << ADC_JSQR_JL_LSB)
#define ADC_JSQR_JL_2CHANNELS (0x1 << ADC_JSQR_JL_LSB)
#define ADC_JSQR_JL_3CHANNELS (0x2 << ADC_JSQR_JL_LSB)
#define ADC_JSQR_JL_4CHANNELS (0x3 << ADC_JSQR_JL_LSB)
/**@}*/
#define ADC_JSQR_JL_SHIFT 13
#define ADC_JSQR_JL_MSK (0x2 << ADC_JSQR_JL_LSB)
#define ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQR_JSQ4_LSB)
#define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQR_JSQ3_LSB)
#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQR_JSQ2_LSB)
#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQR_JSQ1_LSB)
*/
/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */
@@ -679,23 +662,31 @@ LGPL License Terms @ref lgpl_license
BEGIN_DECLS
/* TODO */
void adc_power_on(u32 adc);
void adc_start_conversion_direct(u32 adc);
void adc_set_single_channel(u32 adc, u8 channel);
void adc_set_dual_mode(u32 mode);
bool adc_eoc(u32 adc);
bool adc_eoc_injected(u32 adc);
u32 adc_read_regular(u32 adc);
u32 adc_read_injected(u32 adc, u8 reg);
void adc_set_injected_offset(u32 adc, u8 reg, u32 offset);
void adc_enable_analog_watchdog_regular(u32 adc);
void adc_disable_analog_watchdog_regular(u32 adc);
void adc_enable_analog_watchdog_injected(u32 adc);
void adc_disable_analog_watchdog_injected(u32 adc);
void adc_enable_discontinous_mode_regular(u32 adc);
void adc_disable_discontinous_mode_regular(u32 adc);
void adc_enable_discontinous_mode_injected(u32 adc);
void adc_disable_discontinous_mode_injected(u32 adc);
void adc_enable_discontinuous_mode_regular(u32 adc, u8 length);
void adc_disable_discontinuous_mode_regular(u32 adc);
void adc_enable_discontinuous_mode_injected(u32 adc);
void adc_disable_discontinuous_mode_injected(u32 adc);
void adc_enable_automatic_injected_group_conversion(u32 adc);
void adc_disable_automatic_injected_group_conversion(u32 adc);
void adc_enable_analog_watchdog_on_all_channels(u32 adc);
void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel);
void adc_enable_scan_mode(u32 adc);
void adc_disable_scan_mode(u32 adc);
void adc_enable_jeoc_interrupt(u32 adc);
void adc_disable_jeoc_interrupt(u32 adc);
void adc_enable_eoc_interrupt_injected(u32 adc);
void adc_disable_eoc_interrupt_injected(u32 adc);
void adc_enable_awd_interrupt(u32 adc);
void adc_disable_awd_interrupt(u32 adc);
void adc_enable_eoc_interrupt(u32 adc);
@@ -714,17 +705,28 @@ void adc_enable_dma(u32 adc);
void adc_disable_dma(u32 adc);
void adc_reset_calibration(u32 adc);
void adc_calibration(u32 adc);
void adc_set_continous_conversion_mode(u32 adc);
void adc_set_continuous_conversion_mode(u32 adc);
void adc_set_single_conversion_mode(u32 adc);
#ifdef __GNUC__
void adc_on(u32 adc) __attribute__ ((deprecated ("will be removed in the first release")));
#else
void adc_on(u32 adc);
#endif
void adc_off(u32 adc);
void adc_set_conversion_time(u32 adc, u8 channel, u8 time);
void adc_set_conversion_time_on_all_channels(u32 adc, u8 time);
void adc_set_sample_time(u32 adc, u8 channel, u8 time);
void adc_set_sample_time_on_all_channels(u32 adc, u8 time);
void adc_set_watchdog_high_threshold(u32 adc, u16 threshold);
void adc_set_watchdog_low_threshold(u32 adc, u16 threshold);
void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]);
void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]);
#ifdef __GNUC__
void adc_set_continous_conversion_mode(u32 adc) __attribute__ ((deprecated ("change to adc_set_continuous_conversion_mode")));
void adc_set_conversion_time(u32 adc, u8 channel, u8 time) __attribute__ ((deprecated ("change to adc_set_sample_time")));
void adc_set_conversion_time_on_all_channels(u32 adc, u8 time) __attribute__ ((deprecated ("change to adc_set_sample_time_on_all_channels")));
void adc_enable_jeoc_interrupt(u32 adc) __attribute__ ((deprecated ("change to adc_enable_eoc_interrupt_injected")));
void adc_disable_jeoc_interrupt(u32 adc) __attribute__ ((deprecated ("change to adc_disable_eoc_interrupt_injected")));
#endif
END_DECLS
#endif

29
include/libopencm3/stm32/f1/doc-stm32f1.h
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@@ -1,15 +1,32 @@
/** @mainpage libopencm3 STM32F1
@version 1.0.0
@date 7 September 2012
API documentation for ST Microelectronics STM32F1 Cortex M3 series.
LGPL License Terms @ref lgpl_license
*/
/** @defgroup STM32F1xx STM32F1xx
Libraries for ST Microelectronics STM32F1xx series.
@version 1.0.0
@date 7 September 2012
LGPL License Terms @ref lgpl_license
*/
/** @defgroup STM32F1xx_defines STM32F1xx Defines
@brief Defined Constants and Types for the STM32F1xx series
@ingroup STM32F1xx
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies ksarkies@internode.on.net
@version 1.0.0
@date 18 August 2012
@date 7 September 2012
LGPL License Terms @ref lgpl_license
*/
*/

72
include/libopencm3/stm32/f1/irq.yaml Normal file
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@@ -0,0 +1,72 @@
includeguard: LIBOPENCM3_STM32_F1_NVIC_H
partname_humanreadable: STM32 F1 series
partname_doxygen: STM32F1
irqs:
- wwdg
- pvd
- tamper
- rtc
- flash
- rcc
- exti0
- exti1
- exti2
- exti3
- exti4
- dma1_channel1
- dma1_channel2
- dma1_channel3
- dma1_channel4
- dma1_channel5
- dma1_channel6
- dma1_channel7
- adc1_2
- usb_hp_can_tx
- usb_lp_can_rx0
- can_rx1
- can_sce
- exti9_5
- tim1_brk
- tim1_up
- tim1_trg_com
- tim1_cc
- tim2
- tim3
- tim4
- i2c1_ev
- i2c1_er
- i2c2_ev
- i2c2_er
- spi1
- spi2
- usart1
- usart2
- usart3
- exti15_10
- rtc_alarm
- usb_wakeup
- tim8_brk
- tim8_up
- tim8_trg_com
- tim8_cc
- adc3
- fsmc
- sdio
- tim5
- spi3
- uart4
- uart5
- tim6
- tim7
- dma2_channel1
- dma2_channel2
- dma2_channel3
- dma2_channel4_5
- dma2_channel5
- eth
- eth_wkup
- can2_tx
- can2_rx0
- can2_rx1
- can2_sce
- otg_fs

114
include/libopencm3/stm32/f1/nvic_f1.h
View File

@@ -1,114 +0,0 @@
/** @brief <b>Defined Constants and Types for the STM32F1xx Nested Vectored Interrupt Controller</b>
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
@date 18 August 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_NVIC_F1_H
#define LIBOPENCM3_NVIC_F1_H
/* --- IRQ channel numbers-------------------------------------------------- */
/* Note: These F1 specific user interrupt definitions supplement the
* general NVIC definitions in ../nvic.h
*/
/* User Interrupts */
/** @defgroup nvic_stm32f1_userint STM32F1xx User Interrupts
@ingroup STM32F_nvic_defines
@{*/
#define NVIC_WWDG_IRQ 0
#define NVIC_PVD_IRQ 1
#define NVIC_TAMPER_IRQ 2
#define NVIC_RTC_IRQ 3
#define NVIC_FLASH_IRQ 4
#define NVIC_RCC_IRQ 5
#define NVIC_EXTI0_IRQ 6
#define NVIC_EXTI1_IRQ 7
#define NVIC_EXTI2_IRQ 8
#define NVIC_EXTI3_IRQ 9
#define NVIC_EXTI4_IRQ 10
#define NVIC_DMA1_CHANNEL1_IRQ 11
#define NVIC_DMA1_CHANNEL2_IRQ 12
#define NVIC_DMA1_CHANNEL3_IRQ 13
#define NVIC_DMA1_CHANNEL4_IRQ 14
#define NVIC_DMA1_CHANNEL5_IRQ 15
#define NVIC_DMA1_CHANNEL6_IRQ 16
#define NVIC_DMA1_CHANNEL7_IRQ 17
#define NVIC_ADC1_2_IRQ 18
#define NVIC_USB_HP_CAN_TX_IRQ 19
#define NVIC_USB_LP_CAN_RX0_IRQ 20
#define NVIC_CAN_RX1_IRQ 21
#define NVIC_CAN_SCE_IRQ 22
#define NVIC_EXTI9_5_IRQ 23
#define NVIC_TIM1_BRK_IRQ 24
#define NVIC_TIM1_UP_IRQ 25
#define NVIC_TIM1_TRG_COM_IRQ 26
#define NVIC_TIM1_CC_IRQ 27
#define NVIC_TIM2_IRQ 28
#define NVIC_TIM3_IRQ 29
#define NVIC_TIM4_IRQ 30
#define NVIC_I2C1_EV_IRQ 31
#define NVIC_I2C1_ER_IRQ 32
#define NVIC_I2C2_EV_IRQ 33
#define NVIC_I2C2_ER_IRQ 34
#define NVIC_SPI1_IRQ 35
#define NVIC_SPI2_IRQ 36
#define NVIC_USART1_IRQ 37
#define NVIC_USART2_IRQ 38
#define NVIC_USART3_IRQ 39
#define NVIC_EXTI15_10_IRQ 40
#define NVIC_RTC_ALARM_IRQ 41
#define NVIC_USB_WAKEUP_IRQ 42
#define NVIC_TIM8_BRK_IRQ 43
#define NVIC_TIM8_UP_IRQ 44
#define NVIC_TIM8_TRG_COM_IRQ 45
#define NVIC_TIM8_CC_IRQ 46
#define NVIC_ADC3_IRQ 47
#define NVIC_FSMC_IRQ 48
#define NVIC_SDIO_IRQ 49
#define NVIC_TIM5_IRQ 50
#define NVIC_SPI3_IRQ 51
#define NVIC_UART4_IRQ 52
#define NVIC_UART5_IRQ 53
#define NVIC_TIM6_IRQ 54
#define NVIC_TIM7_IRQ 55
#define NVIC_DMA2_CHANNEL1_IRQ 56
#define NVIC_DMA2_CHANNEL2_IRQ 57
#define NVIC_DMA2_CHANNEL3_IRQ 58
#define NVIC_DMA2_CHANNEL4_5_IRQ 59
#define NVIC_DMA2_CHANNEL5_IRQ 60
#define NVIC_ETH_IRQ 61
#define NVIC_ETH_WKUP_IRQ 62
#define NVIC_CAN2_TX_IRQ 63
#define NVIC_CAN2_RX0_IRQ 64
#define NVIC_CAN2_RX1_IRQ 65
#define NVIC_CAN2_SCE_IRQ 66
#define NVIC_OTG_FS_IRQ 67
/**@}*/
#endif

33
include/libopencm3/stm32/f2/doc-stm32f2.h Normal file
View File

@@ -0,0 +1,33 @@
/** @mainpage libopencm3 STM32F2
@version 1.0.0
@date 14 September 2012
API documentation for ST Microelectronics STM32F2 Cortex M3 series.
LGPL License Terms @ref lgpl_license
*/
/** @defgroup STM32F2xx STM32F2xx
Libraries for ST Microelectronics STM32F2xx series.
@version 1.0.0
@date 14 September 2012
LGPL License Terms @ref lgpl_license
*/
/** @defgroup STM32F2xx_defines STM32F2xx Defines
@brief Defined Constants and Types for the STM32F2xx series
@version 1.0.0
@date 14 September 2012
LGPL License Terms @ref lgpl_license
*/

85
include/libopencm3/stm32/f2/irq.yaml Normal file
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@@ -0,0 +1,85 @@
includeguard: LIBOPENCM3_STM32_F2_NVIC_H
partname_humanreadable: STM32 F2 series
partname_doxygen: STM32F2
irqs:
- nvic_wwdg
- pvd
- tamp_stamp
- rtc_wkup
- flash
- rcc
- exti0
- exti1
- exti2
- exti3
- exti4
- dma1_stream0
- dma1_stream1
- dma1_stream2
- dma1_stream3
- dma1_stream4
- dma1_stream5
- dma1_stream6
- adc
- can1_tx
- can1_rx0
- can1_rx1
- can1_sce
- exti9_5
- tim1_brk_tim9
- tim1_up_tim10
- tim1_trg_com_tim11
- tim1_cc
- tim2
- tim3
- tim4
- i2c1_ev
- i2c1_er
- i2c2_ev
- i2c2_er
- spi1
- spi2
- usart1
- usart2
- usart3
- exti15_10
- rtc_alarm
- usb_fs_wkup
- tim8_brk_tim12
- tim8_up_tim13
- tim8_trg_com_tim14
- tim8_cc
- dma1_stream7
- fsmc
- sdio
- tim5
- spi3
- uart4
- uart5
- tim6_dac
- tim7
- dma2_stream0
- dma2_stream1
- dma2_stream2
- dma2_stream3
- dma2_stream4
- eth
- eth_wkup
- can2_tx
- can2_rx0
- can2_rx1
- can2_sce
- otg_fs
- dma2_stream5
- dma2_stream6
- dma2_stream7
- usart6
- i2c3_ev
- i2c3_er
- otg_hs_ep1_out
- otg_hs_ep1_in
- otg_hs_wkup
- otg_hs
- dcmi
- cryp
- hash_rng

112
include/libopencm3/stm32/f2/nvic_f2.h
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@@ -1,112 +0,0 @@
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_NVIC_F2_H
#define LIBOPENCM3_NVIC_F2_H
/* --- IRQ channel numbers-------------------------------------------------- */
/* Note: These F2 specific user interrupt definitions supplement the
* general NVIC definitions in ../nvic.h
*/
/* User Interrupts */
#define NVIC_NVIC_WWDG_IRQ 0
#define NVIC_PVD_IRQ 1
#define NVIC_TAMP_STAMP_IRQ 2
#define NVIC_RTC_WKUP_IRQ 3
#define NVIC_FLASH_IRQ 4
#define NVIC_RCC_IRQ 5
#define NVIC_EXTI0_IRQ 6
#define NVIC_EXTI1_IRQ 7
#define NVIC_EXTI2_IRQ 8
#define NVIC_EXTI3_IRQ 9
#define NVIC_EXTI4_IRQ 10
#define NVIC_DMA1_STREAM0_IRQ 11
#define NVIC_DMA1_STREAM1_IRQ 12
#define NVIC_DMA1_STREAM2_IRQ 13
#define NVIC_DMA1_STREAM3_IRQ 14
#define NVIC_DMA1_STREAM4_IRQ 15
#define NVIC_DMA1_STREAM5_IRQ 16
#define NVIC_DMA1_STREAM6_IRQ 17
#define NVIC_ADC_IRQ 18
#define NVIC_CAN1_TX_IRQ 19
#define NVIC_CAN1_RX0_IRQ 20
#define NVIC_CAN1_RX1_IRQ 21
#define NVIC_CAN1_SCE_IRQ 22
#define NVIC_EXTI9_5_IRQ 23
#define NVIC_TIM1_BRK_TIM9_IRQ 24
#define NVIC_TIM1_UP_TIM10_IRQ 25
#define NVIC_TIM1_TRG_COM_TIM11_IRQ 26
#define NVIC_TIM1_CC_IRQ 27
#define NVIC_TIM2_IRQ 28
#define NVIC_TIM3_IRQ 29
#define NVIC_TIM4_IRQ 30
#define NVIC_I2C1_EV_IRQ 31
#define NVIC_I2C1_ER_IRQ 32
#define NVIC_I2C2_EV_IRQ 33
#define NVIC_I2C2_ER_IRQ 34
#define NVIC_SPI1_IRQ 35
#define NVIC_SPI2_IRQ 36
#define NVIC_USART1_IRQ 37
#define NVIC_USART2_IRQ 38
#define NVIC_USART3_IRQ 39
#define NVIC_EXTI15_10_IRQ 40
#define NVIC_RTC_ALARM_IRQ 41
#define NVIC_USB_FS_WKUP_IRQ 42
#define NVIC_TIM8_BRK_TIM12_IRQ 43
#define NVIC_TIM8_UP_TIM13_IRQ 44
#define NVIC_TIM8_TRG_COM_TIM14_IRQ 45
#define NVIC_TIM8_CC_IRQ 46
#define NVIC_DMA1_STREAM7_IRQ 47
#define NVIC_FSMC_IRQ 48
#define NVIC_SDIO_IRQ 49
#define NVIC_TIM5_IRQ 50
#define NVIC_SPI3_IRQ 51
#define NVIC_UART4_IRQ 52
#define NVIC_UART5_IRQ 53
#define NVIC_TIM6_DAC_IRQ 54
#define NVIC_TIM7_IRQ 55
#define NVIC_DMA2_STREAM0_IRQ 56
#define NVIC_DMA2_STREAM1_IRQ 57
#define NVIC_DMA2_STREAM2_IRQ 58
#define NVIC_DMA2_STREAM3_IRQ 59
#define NVIC_DMA2_STREAM4_IRQ 60
#define NVIC_ETH_IRQ 61
#define NVIC_ETH_WKUP_IRQ 62
#define NVIC_CAN2_TX_IRQ 63
#define NVIC_CAN2_RX0_IRQ 64
#define NVIC_CAN2_RX1_IRQ 65
#define NVIC_CAN2_SCE_IRQ 66
#define NVIC_OTG_FS_IRQ 67
#define NVIC_DMA2_STREAM5_IRQ 68
#define NVIC_DMA2_STREAM6_IRQ 69
#define NVIC_DMA2_STREAM7_IRQ 70
#define NVIC_USART6_IRQ 71
#define NVIC_I2C3_EV_IRQ 72
#define NVIC_I2C3_ER_IRQ 73
#define NVIC_OTG_HS_EP1_OUT_IRQ 74
#define NVIC_OTG_HS_EP1_IN_IRQ 75
#define NVIC_OTG_HS_WKUP_IRQ 76
#define NVIC_OTG_HS_IRQ 77
#define NVIC_DCMI_IRQ 78
#define NVIC_CRYP_IRQ 79
#define NVIC_HASH_RNG_IRQ 80
#endif

32
include/libopencm3/stm32/f4/doc-stm32f4.h Normal file
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@@ -0,0 +1,32 @@
/** @mainpage libopencm3 STM32F4
@version 1.0.0
@date 7 September 2012
API documentation for ST Microelectronics STM32F4 Cortex M3 series.
LGPL License Terms @ref lgpl_license
*/
/** @defgroup STM32F4xx STM32F4xx
Libraries for ST Microelectronics STM32F4xx series.
@version 1.0.0
@date 7 September 2012
LGPL License Terms @ref lgpl_license
*/
/** @defgroup STM32F4xx_defines STM32F4xx Defines
@brief Defined Constants and Types for the STM32F4xx series
@version 1.0.0
@date 7 September 2012
LGPL License Terms @ref lgpl_license
*/

85
include/libopencm3/stm32/f4/irq.yaml Normal file
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@@ -0,0 +1,85 @@
includeguard: LIBOPENCM3_STM32_F4_NVIC_H
partname_humanreadable: STM32 F4 series
partname_doxygen: STM32F4
irqs:
- nvic_wwdg
- pvd
- tamp_stamp
- rtc_wkup
- flash
- rcc
- exti0
- exti1
- exti2
- exti3
- exti4
- dma1_stream0
- dma1_stream1
- dma1_stream2
- dma1_stream3
- dma1_stream4
- dma1_stream5
- dma1_stream6
- adc
- can1_tx
- can1_rx0
- can1_rx1
- can1_sce
- exti9_5
- tim1_brk_tim9
- tim1_up_tim10
- tim1_trg_com_tim11
- tim1_cc
- tim2
- tim3
- tim4
- i2c1_ev
- i2c1_er
- i2c2_ev
- i2c2_er
- spi1
- spi2
- usart1
- usart2
- usart3
- exti15_10
- rtc_alarm
- usb_fs_wkup
- tim8_brk_tim12
- tim8_up_tim13
- tim8_trg_com_tim14
- tim8_cc
- dma1_stream7
- fsmc
- sdio
- tim5
- spi3
- uart4
- uart5
- tim6_dac
- tim7
- dma2_stream0
- dma2_stream1
- dma2_stream2
- dma2_stream3
- dma2_stream4
- eth
- eth_wkup
- can2_tx
- can2_rx0
- can2_rx1
- can2_sce
- otg_fs
- dma2_stream5
- dma2_stream6
- dma2_stream7
- usart6
- i2c3_ev
- i2c3_er
- otg_hs_ep1_out
- otg_hs_ep1_in
- otg_hs_wkup
- otg_hs
- dcmi
- cryp
- hash_rng

112
include/libopencm3/stm32/f4/nvic_f4.h
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@@ -1,112 +0,0 @@
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_NVIC_F4_H
#define LIBOPENCM3_NVIC_F4_H
/* --- IRQ channel numbers-------------------------------------------------- */
/* Note: These F4 specific user interrupt definitions supplement the
* general NVIC definitions in ../nvic.h
*/
/* User Interrupts */
#define NVIC_NVIC_WWDG_IRQ 0
#define NVIC_PVD_IRQ 1
#define NVIC_TAMP_STAMP_IRQ 2
#define NVIC_RTC_WKUP_IRQ 3
#define NVIC_FLASH_IRQ 4
#define NVIC_RCC_IRQ 5
#define NVIC_EXTI0_IRQ 6
#define NVIC_EXTI1_IRQ 7
#define NVIC_EXTI2_IRQ 8
#define NVIC_EXTI3_IRQ 9
#define NVIC_EXTI4_IRQ 10
#define NVIC_DMA1_STREAM0_IRQ 11
#define NVIC_DMA1_STREAM1_IRQ 12
#define NVIC_DMA1_STREAM2_IRQ 13
#define NVIC_DMA1_STREAM3_IRQ 14
#define NVIC_DMA1_STREAM4_IRQ 15
#define NVIC_DMA1_STREAM5_IRQ 16
#define NVIC_DMA1_STREAM6_IRQ 17
#define NVIC_ADC_IRQ 18
#define NVIC_CAN1_TX_IRQ 19
#define NVIC_CAN1_RX0_IRQ 20
#define NVIC_CAN1_RX1_IRQ 21
#define NVIC_CAN1_SCE_IRQ 22
#define NVIC_EXTI9_5_IRQ 23
#define NVIC_TIM1_BRK_TIM9_IRQ 24
#define NVIC_TIM1_UP_TIM10_IRQ 25
#define NVIC_TIM1_TRG_COM_TIM11_IRQ 26
#define NVIC_TIM1_CC_IRQ 27
#define NVIC_TIM2_IRQ 28
#define NVIC_TIM3_IRQ 29
#define NVIC_TIM4_IRQ 30
#define NVIC_I2C1_EV_IRQ 31
#define NVIC_I2C1_ER_IRQ 32
#define NVIC_I2C2_EV_IRQ 33
#define NVIC_I2C2_ER_IRQ 34
#define NVIC_SPI1_IRQ 35
#define NVIC_SPI2_IRQ 36
#define NVIC_USART1_IRQ 37
#define NVIC_USART2_IRQ 38
#define NVIC_USART3_IRQ 39
#define NVIC_EXTI15_10_IRQ 40
#define NVIC_RTC_ALARM_IRQ 41
#define NVIC_USB_FS_WKUP_IRQ 42
#define NVIC_TIM8_BRK_TIM12_IRQ 43
#define NVIC_TIM8_UP_TIM13_IRQ 44
#define NVIC_TIM8_TRG_COM_TIM14_IRQ 45
#define NVIC_TIM8_CC_IRQ 46
#define NVIC_DMA1_STREAM7_IRQ 47
#define NVIC_FSMC_IRQ 48
#define NVIC_SDIO_IRQ 49
#define NVIC_TIM5_IRQ 50
#define NVIC_SPI3_IRQ 51
#define NVIC_UART4_IRQ 52
#define NVIC_UART5_IRQ 53
#define NVIC_TIM6_DAC_IRQ 54
#define NVIC_TIM7_IRQ 55
#define NVIC_DMA2_STREAM0_IRQ 56
#define NVIC_DMA2_STREAM1_IRQ 57
#define NVIC_DMA2_STREAM2_IRQ 58
#define NVIC_DMA2_STREAM3_IRQ 59
#define NVIC_DMA2_STREAM4_IRQ 60
#define NVIC_ETH_IRQ 61
#define NVIC_ETH_WKUP_IRQ 62
#define NVIC_CAN2_TX_IRQ 63
#define NVIC_CAN2_RX0_IRQ 64
#define NVIC_CAN2_RX1_IRQ 65
#define NVIC_CAN2_SCE_IRQ 66
#define NVIC_OTG_FS_IRQ 67
#define NVIC_DMA2_STREAM5_IRQ 68
#define NVIC_DMA2_STREAM6_IRQ 69
#define NVIC_DMA2_STREAM7_IRQ 70
#define NVIC_USART6_IRQ 71
#define NVIC_I2C3_EV_IRQ 72
#define NVIC_I2C3_ER_IRQ 73
#define NVIC_OTG_HS_EP1_OUT_IRQ 74
#define NVIC_OTG_HS_EP1_IN_IRQ 75
#define NVIC_OTG_HS_WKUP_IRQ 76
#define NVIC_OTG_HS_IRQ 77
#define NVIC_DCMI_IRQ 78
#define NVIC_CRYP_IRQ 79
#define NVIC_HASH_RNG_IRQ 80
#endif

61
include/libopencm3/stm32/f4/rng.h Normal file
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@@ -0,0 +1,61 @@
/*
* This file is part of the libopencm3 project.
*
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_RNG_H
#define LIBOPENCM3_RNG_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
/* --- Random number generator registers ----------------------------------- */
/* Control register */
#define RNG_CR MMIO32(RNG_BASE + 0x00)
/* Status register */
#define RNG_SR MMIO32(RNG_BASE + 0x04)
/* Data register */
#define RNG_DR MMIO32(RNG_BASE + 0x08)
/* --- RNG_CR values ------------------------------------------------------- */
/* RNG ENABLE */
#define RNG_CR_EN (1 << 2)
/* RNG interupt enable */
#define RNG_CR_IE (1 << 3)
/* --- RNG_SR values ------------------------------------------------------- */
/* Data ready */
#define RNG_SR_DRDY (1 << 0)
/* Clock error current status */
#define RNG_SR_CECS (1 << 1)
/* Seed error current status */
#define RNG_SR_SECS (1 << 2)
/* Clock error interup status */
#define RNG_SR_CEIS (1 << 5)
/* Seed error interup status */
#define RNG_SR_SEIS (1 << 6)
#endif

69
include/libopencm3/stm32/f4/scb.h
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@@ -72,6 +72,63 @@
/* AFSR: Auxiliary Fault Status Register */
#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
/* ID_PFR0: Processor Feature Register 0 */
#define SCB_ID_PFR0 MMIO32(SCB_BASE + 0x40)
/* ID_PFR1: Processor Feature Register 1 */
#define SCB_ID_PFR1 MMIO32(SCB_BASE + 0x44)
/* ID_DFR0: Debug Features Register 0 */
#define SCB_ID_DFR0 MMIO32(SCB_BASE + 0x48)
/* ID_AFR0: Auxiliary Features Register 0 */
#define SCB_ID_AFR0 MMIO32(SCB_BASE + 0x4C)
/* ID_MMFR0: Memory Model Feature Register 0 */
#define SCB_ID_MMFR0 MMIO32(SCB_BASE + 0x50)
/* ID_MMFR1: Memory Model Feature Register 1 */
#define SCB_ID_MMFR1 MMIO32(SCB_BASE + 0x54)
/* ID_MMFR2: Memory Model Feature Register 2 */
#define SCB_ID_MMFR2 MMIO32(SCB_BASE + 0x58)
/* ID_MMFR3: Memory Model Feature Register 3 */
#define SCB_ID_MMFR3 MMIO32(SCB_BASE + 0x5C)
/* ID_ISAR0: Instruction Set Attributes Register 0 */
#define SCB_ID_ISAR0 MMIO32(SCB_BASE + 0x60)
/* ID_ISAR1: Instruction Set Attributes Register 1 */
#define SCB_ID_ISAR1 MMIO32(SCB_BASE + 0x64)
/* ID_ISAR2: Instruction Set Attributes Register 2 */
#define SCB_ID_ISAR2 MMIO32(SCB_BASE + 0x68)
/* ID_ISAR3: Instruction Set Attributes Register 3 */
#define SCB_ID_ISAR3 MMIO32(SCB_BASE + 0x6C)
/* ID_ISAR4: Instruction Set Attributes Register 4 */
#define SCB_ID_ISAR4 MMIO32(SCB_BASE + 0x70)
/* CPACR: Coprocessor Access Control Register */
#define SCB_CPACR MMIO32(SCB_BASE + 0x88)
/* FPCCR: Floating-Point Context Control Register */
#define SCB_FPCCR MMIO32(SCB_BASE + 0x234)
/* FPCAR: Floating-Point Context Address Register */
#define SCB_FPCAR MMIO32(SCB_BASE + 0x238)
/* FPDSCR: Floating-Point Default Status Control Register */
#define SCB_FPDSCR MMIO32(SCB_BASE + 0x23C)
/* MVFR0: Media and Floating-Point Feature Register 0 */
#define SCB_MVFR0 MMIO32(SCB_BASE + 0x240)
/* MVFR1: Media and Floating-Point Feature Register 1 */
#define SCB_MVFR1 MMIO32(SCB_BASE + 0x244)
/* --- SCB values ---------------------------------------------------------- */
/* --- SCB_CPUID values ---------------------------------------------------- */
@@ -292,6 +349,18 @@
/* BFAR [31:0]: Bus fault address */
/* --- SCB_CPACR values ---------------------------------------------------- */
/* CPACR CPn: Access privileges values */
#define SCB_CPACR_NONE 0 /* Access denied */
#define SCB_CPACR_PRIV 1 /* Privileged access only */
#define SCB_CPACR_FULL 3 /* Full access */
/* CPACR [20:21]: Access privileges for coprocessor 10 */
#define SCB_CPACR_CP10 (1 << 20)
/* CPACR [22:23]: Access privileges for coprocessor 11 */
#define SCB_CPACR_CP11 (1 << 22)
/* --- SCB functions ------------------------------------------------------- */
BEGIN_DECLS

38
include/libopencm3/stm32/i2c.h
View File

@@ -1,3 +1,19 @@
/** @defgroup i2c_defines I2C Defines
@ingroup STM32F_defines
@brief <b>libopencm3 Defined Constants and Types for the STM32 I2C </b>
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
@date 12 October 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
@@ -23,11 +39,19 @@
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
/**@{*/
/* --- Convenience macros -------------------------------------------------- */
/* I2C register base adresses (for convenience) */
/****************************************************************************/
/** @defgroup i2c_reg_base I2C register base address
@ingroup i2c_defines
@{*/
#define I2C1 I2C1_BASE
#define I2C2 I2C2_BASE
/**@}*/
/* --- I2C registers ------------------------------------------------------- */
@@ -146,6 +170,11 @@
/* Note: Bits [7:6] are reserved, and forced to 0 by hardware. */
/* FREQ[5:0]: Peripheral clock frequency (valid values: 2-36 MHz) */
/****************************************************************************/
/** @defgroup i2c_clock I2C clock frequency settings
@ingroup i2c_defines
@{*/
#define I2C_CR2_FREQ_2MHZ 0x02
#define I2C_CR2_FREQ_3MHZ 0x03
#define I2C_CR2_FREQ_4MHZ 0x04
@@ -181,6 +210,7 @@
#define I2C_CR2_FREQ_34MHZ 0x22
#define I2C_CR2_FREQ_35MHZ 0x23
#define I2C_CR2_FREQ_36MHZ 0x24
/**@}*/
/* --- I2Cx_OAR1 values ---------------------------------------------------- */
@@ -311,8 +341,14 @@
/* --- I2C const definitions ----------------------------------------------- */
/****************************************************************************/
/** @defgroup i2c_rw I2C Read/Write bit
@ingroup i2c_defines
@{*/
#define I2C_WRITE 0
#define I2C_READ 1
/**@}*/
/* --- I2C funtion prototypes----------------------------------------------- */
@@ -336,3 +372,5 @@ void i2c_send_data(u32 i2c, u8 data);
END_DECLS
#endif
/**@}*/

62
include/libopencm3/stm32/spi.h
View File

@@ -1,3 +1,19 @@
/** @defgroup spi_defines SPI Defines
@ingroup STM32F_defines
@brief <b>libopencm3 Defined Constants and Types for the STM32 SPI </b>
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
@date 12 October 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
@@ -23,13 +39,21 @@
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
/**@{*/
/* Registers can be accessed as 16bit or 32bit values. */
/* --- Convenience macros -------------------------------------------------- */
/****************************************************************************/
/** @defgroup spi_reg_base SPI Register base address
@ingroup spi_defines
@{*/
#define SPI1 SPI1_BASE
#define SPI2 SPI2_I2S_BASE
#define SPI3 SPI3_I2S_BASE
/**@}*/
/* --- SPI registers ------------------------------------------------------- */
@@ -110,8 +134,14 @@
#define SPI_CR1_CRCNEXT (1 << 12)
/* DFF: Data frame format */
/****************************************************************************/
/** @defgroup spi_dff SPI data frame format
@ingroup spi_defines
@{*/
#define SPI_CR1_DFF_8BIT (0 << 11)
#define SPI_CR1_DFF_16BIT (1 << 11)
/**@}*/
#define SPI_CR1_DFF (1 << 11)
/* RXONLY: Receive only */
@@ -124,13 +154,24 @@
#define SPI_CR1_SSI (1 << 8)
/* LSBFIRST: Frame format */
/****************************************************************************/
/** @defgroup spi_lsbfirst SPI lsb/msb first
@ingroup spi_defines
@{*/
#define SPI_CR1_MSBFIRST (0 << 7)
#define SPI_CR1_LSBFIRST (1 << 7)
/**@}*/
/* SPE: SPI enable */
#define SPI_CR1_SPE (1 << 6)
/* BR[2:0]: Baud rate control */
/****************************************************************************/
/** @defgroup spi_baudrate SPI peripheral baud rates
@ingroup spi_defines
@{*/
#define SPI_CR1_BAUDRATE_FPCLK_DIV_2 (0x00 << 3)
#define SPI_CR1_BAUDRATE_FPCLK_DIV_4 (0x01 << 3)
#define SPI_CR1_BAUDRATE_FPCLK_DIV_8 (0x02 << 3)
@@ -139,6 +180,12 @@
#define SPI_CR1_BAUDRATE_FPCLK_DIV_64 (0x05 << 3)
#define SPI_CR1_BAUDRATE_FPCLK_DIV_128 (0x06 << 3)
#define SPI_CR1_BAUDRATE_FPCLK_DIV_256 (0x07 << 3)
/**@}*/
/****************************************************************************/
/** @defgroup spi_br_pre SPI peripheral baud rate prescale values
@ingroup spi_defines
@{*/
#define SPI_CR1_BR_FPCLK_DIV_2 0x0
#define SPI_CR1_BR_FPCLK_DIV_4 0x1
#define SPI_CR1_BR_FPCLK_DIV_8 0x2
@@ -147,18 +194,31 @@
#define SPI_CR1_BR_FPCLK_DIV_64 0x5
#define SPI_CR1_BR_FPCLK_DIV_128 0x6
#define SPI_CR1_BR_FPCLK_DIV_256 0x7
/**@}*/
/* MSTR: Master selection */
#define SPI_CR1_MSTR (1 << 2)
/* CPOL: Clock polarity */
/****************************************************************************/
/** @defgroup spi_cpol SPI clock polarity
@ingroup spi_defines
@{*/
#define SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE (0 << 1)
#define SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE (1 << 1)
/**@}*/
#define SPI_CR1_CPOL (1 << 1)
/* CPHA: Clock phase */
/****************************************************************************/
/** @defgroup spi_cpha SPI clock phase
@ingroup spi_defines
@{*/
#define SPI_CR1_CPHA_CLK_TRANSITION_1 (0 << 0)
#define SPI_CR1_CPHA_CLK_TRANSITION_2 (1 << 0)
/**@}*/
#define SPI_CR1_CPHA (1 << 0)
/* --- SPI_CR2 values ------------------------------------------------------ */
@@ -347,4 +407,6 @@ void spi_disable_rx_dma(u32 spi);
END_DECLS
/**@}*/
#endif

28
include/libopencm3/stm32/timer.h
View File

@@ -1,6 +1,6 @@
/** @defgroup STM32F_tim_defines Timers Defines
@brief <b>libopencm3 Defined Constants and Types for the STM32F1xx Timers</b>
@brief <b>libopencm3 Defined Constants and Types for the STM32 Timers</b>
@ingroup STM32F_defines
@@ -44,7 +44,7 @@ LGPL License Terms @ref lgpl_license
/* Timer register base adresses (for convenience) */
/****************************************************************************/
/** @defgroup tim_reg_base Timer register base addresses
@ingroup STM32F1xx_tim_defines
@ingroup STM32F_tim_defines
@{*/
#define TIM1 TIM1_BASE
@@ -251,7 +251,7 @@ LGPL License Terms @ref lgpl_license
/****************************************************************************/
/** @defgroup tim_x_cr1_cdr TIMx_CR1 CKD[1:0] Clock Division Ratio
@ingroup STM32F1xx_tim_defines
@ingroup STM32F_tim_defines
@{*/
/* CKD[1:0]: Clock division */
@@ -267,7 +267,7 @@ LGPL License Terms @ref lgpl_license
/* CMS[1:0]: Center-aligned mode selection */
/****************************************************************************/
/** @defgroup tim_x_cr1_cms TIMx_CR1 CMS[1:0]: Center-aligned Mode Selection
@ingroup STM32F1xx_tim_defines
@ingroup STM32F_tim_defines
@{*/
#define TIM_CR1_CMS_EDGE (0x0 << 5)
@@ -280,7 +280,7 @@ LGPL License Terms @ref lgpl_license
/* DIR: Direction */
/****************************************************************************/
/** @defgroup tim_x_cr1_dir TIMx_CR1 DIR: Direction
@ingroup STM32F1xx_tim_defines
@ingroup STM32F_tim_defines
@{*/
#define TIM_CR1_DIR_UP (0 << 4)
@@ -303,7 +303,7 @@ LGPL License Terms @ref lgpl_license
/****************************************************************************/
/** @defgroup tim_x_cr2_ois TIMx_CR2_OIS: Force Output Idle State Control Values
@ingroup STM32F1xx_tim_defines
@ingroup STM32F_tim_defines
@{*/
/* OIS4:*//** Output idle state 4 (OC4 output) */
@@ -335,7 +335,7 @@ LGPL License Terms @ref lgpl_license
/* MMS[2:0]: Master mode selection */
/****************************************************************************/
/** @defgroup tim_mastermode TIMx_CR2 MMS[6:4]: Master Mode Selection
@ingroup STM32F1xx_tim_defines
@ingroup STM32F_tim_defines
@{*/
#define TIM_CR2_MMS_RESET (0x0 << 4)
@@ -397,7 +397,7 @@ LGPL License Terms @ref lgpl_license
/* TS[2:0]: Trigger selection */
/** @defgroup tim_ts TS Trigger selection
@ingroup STM32F1xx_tim_defines
@ingroup STM32F_tim_defines
@{*/
/** Internal Trigger 0 (ITR0) */
@@ -421,7 +421,7 @@ LGPL License Terms @ref lgpl_license
/* SMS[2:0]: Slave mode selection */
/** @defgroup tim_sms SMS Slave mode selection
@ingroup STM32F1xx_tim_defines
@ingroup STM32F_tim_defines
@{*/
/** Slave mode disabled */
@@ -451,7 +451,7 @@ and generates an update of the registers. */
/****************************************************************************/
/** @defgroup tim_irq_enable TIMx_DIER Timer DMA and Interrupt Enable Values
@ingroup STM32F1xx_tim_defines
@ingroup STM32F_tim_defines
@{*/
/* TDE:*//** Trigger DMA request enable */
@@ -503,7 +503,7 @@ and generates an update of the registers. */
/* --- TIMx_SR values ------------------------------------------------------ */
/****************************************************************************/
/** @defgroup tim_sr_values TIMx_SR Timer Status Register Flags
@ingroup STM32F1xx_tim_defines
@ingroup STM32F_tim_defines
@{*/
@@ -548,7 +548,7 @@ and generates an update of the registers. */
/****************************************************************************/
/** @defgroup tim_event_gen TIMx_EGR Timer Event Generator Values
@ingroup STM32F1xx_tim_defines
@ingroup STM32F_tim_defines
@{*/
@@ -908,7 +908,7 @@ and generates an update of the registers. */
/* LOCK[1:0]: Lock configuration */
/****************************************************************************/
/** @defgroup tim_lock TIM_BDTR_LOCK Timer Lock Values
@ingroup STM32F1xx_tim_defines
@ingroup STM32F_tim_defines
@{*/
#define TIM_BDTR_LOCK_OFF (0x0 << 8)
@@ -1028,6 +1028,7 @@ BEGIN_DECLS
void timer_reset(u32 timer_peripheral);
void timer_enable_irq(u32 timer_peripheral, u32 irq);
void timer_disable_irq(u32 timer_peripheral, u32 irq);
bool timer_return_interrupt_source(u32 timer_peripheral, u32 flag);
bool timer_get_flag(u32 timer_peripheral, u32 flag);
void timer_clear_flag(u32 timer_peripheral, u32 flag);
void timer_set_mode(u32 timer_peripheral, u32 clock_div,
@@ -1090,6 +1091,7 @@ void timer_set_break_lock(u32 timer_peripheral, u32 lock);
void timer_set_deadtime(u32 timer_peripheral, u32 deadtime);
void timer_generate_event(u32 timer_peripheral, u32 event);
u32 timer_get_counter(u32 timer_peripheral);
void timer_set_counter(u32 timer_peripheral, u32 count);
void timer_ic_set_filter(u32 timer, enum tim_ic_id ic, enum tim_ic_filter flt);
void timer_ic_set_prescaler(u32 timer, enum tim_ic_id ic, enum tim_ic_psc psc);

83
include/libopencm3/stm32/usart.h
View File

@@ -1,3 +1,18 @@
/** @defgroup STM32F_usart_defines USART Defines
@brief <b>libopencm3 Defined Constants and Types for the STM32F Digital to Analog Converter </b>
@ingroup STM32F_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
@date 1 September 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
@@ -17,6 +32,8 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#ifndef LIBOPENCM3_USART_H
#define LIBOPENCM3_USART_H
@@ -25,9 +42,15 @@
/* --- Convenience macros -------------------------------------------------- */
/****************************************************************************/
/** @defgroup usart_reg_base USART register base addresses
@ingroup STM32F_usart_defines
@{*/
#define USART1 USART1_BASE
#define USART2 USART2_BASE
#define USART3 USART3_BASE
/**@}*/
#define UART4 UART4_BASE
#define UART5 UART5_BASE
@@ -90,37 +113,43 @@
#define UART5_GTPR USART_GTPR(UART5_BASE)
/* --- USART_SR values ----------------------------------------------------- */
/****************************************************************************/
/** @defgroup usart_sr_flags USART Status register Flags
@ingroup STM32F_usart_defines
/* CTS: CTS flag */
/* Note: N/A on UART4/5 */
@{*/
/** CTS: CTS flag */
/** @note: undefined on UART4 and UART5 */
#define USART_SR_CTS (1 << 9)
/* LBD: LIN break detection flag */
/** LBD: LIN break detection flag */
#define USART_SR_LBD (1 << 8)
/* TXE: Transmit data buffer empty */
/** TXE: Transmit data buffer empty */
#define USART_SR_TXE (1 << 7)
/* TC: Transmission complete */
/** TC: Transmission complete */
#define USART_SR_TC (1 << 6)
/* RXNE: Read data register not empty */
/** RXNE: Read data register not empty */
#define USART_SR_RXNE (1 << 5)
/* IDLE: Idle line detected */
/** IDLE: Idle line detected */
#define USART_SR_IDLE (1 << 4)
/* ORE: Overrun error */
/** ORE: Overrun error */
#define USART_SR_ORE (1 << 3)
/* NE: Noise error flag */
/** NE: Noise error flag */
#define USART_SR_NE (1 << 2)
/* FE: Framing error */
/** FE: Framing error */
#define USART_SR_FE (1 << 1)
/* PE: Parity error */
/** PE: Parity error */
#define USART_SR_PE (1 << 0)
/**@}*/
/* --- USART_DR values ----------------------------------------------------- */
@@ -269,27 +298,51 @@
/* --- Convenience defines ------------------------------------------------- */
/* CR1_PCE / CR1_PS combined values */
/****************************************************************************/
/** @defgroup usart_cr1_parity USART Parity Selection
@ingroup STM32F_usart_defines
@{*/
#define USART_PARITY_NONE 0x00
#define USART_PARITY_EVEN USART_CR1_PCE
#define USART_PARITY_ODD (USART_CR1_PS | USART_CR1_PCE)
/**@}*/
#define USART_PARITY_MASK (USART_CR1_PS | USART_CR1_PCE)
/* CR1_TE/CR1_RE combined values */
/****************************************************************************/
/** @defgroup usart_cr1_mode USART Tx/Rx Mode Selection
@ingroup STM32F_usart_defines
@{*/
#define USART_MODE_RX USART_CR1_RE
#define USART_MODE_TX USART_CR1_TE
#define USART_MODE_TX_RX (USART_CR1_RE | USART_CR1_TE)
/**@}*/
#define USART_MODE_MASK (USART_CR1_RE | USART_CR1_TE)
/****************************************************************************/
/** @defgroup usart_cr2_stopbits USART Stop Bit Selection
@ingroup STM32F_usart_defines
@{*/
#define USART_STOPBITS_1 USART_CR2_STOPBITS_1 /* 1 stop bit */
#define USART_STOPBITS_0_5 USART_CR2_STOPBITS_0_5 /* 0.5 stop bits */
#define USART_STOPBITS_2 USART_CR2_STOPBITS_2 /* 2 stop bits */
#define USART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5 /* 1.5 stop bits */
/**@}*/
/* CR3_CTSE/CR3_RTSE combined values */
/****************************************************************************/
/** @defgroup usart_cr3_flowcontrol USART Hardware Flow Control Selection
@ingroup STM32F_usart_defines
@{*/
#define USART_FLOWCONTROL_NONE 0x00
#define USART_FLOWCONTROL_RTS USART_CR3_RTSE
#define USART_FLOWCONTROL_CTS USART_CR3_CTSE
#define USART_FLOWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
/**@}*/
#define USART_FLOWCONTROL_MASK (USART_CR3_RTSE | USART_CR3_CTSE)
/* --- Function prototypes ------------------------------------------------- */
@@ -314,7 +367,15 @@ void usart_enable_rx_dma(u32 usart);
void usart_disable_rx_dma(u32 usart);
void usart_enable_tx_dma(u32 usart);
void usart_disable_tx_dma(u32 usart);
void usart_enable_rx_interrupt(u32 usart);
void usart_disable_rx_interrupt(u32 usart);
void usart_enable_tx_interrupt(u32 usart);
void usart_disable_tx_interrupt(u32 usart);
bool usart_get_flag(u32 usart, u32 flag);
bool usart_get_interrupt_source(u32 usart, u32 flag);
END_DECLS
#endif
/**@}*/